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Change subject: mb/starlabs/byte: Update the VBT from 249 to 251
......................................................................
mb/starlabs/byte: Update the VBT from 249 to 251
This silences a few warnings in FSP.
Change-Id: I3bef919d1c6fcb9abff4fc49300321c9d471cb82
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/byte_adl/variants/mk_ii/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85706/3
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Change subject: mb/starlabs/*: Select TPM2 so PPI is generated
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Change subject: intel/common/rtd3: Allow emitting PSD0 Method for CPU Root Ports
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Change subject: mb/starlabs/*: Use the new Intel Bluetooth driver
......................................................................
Patch Set 24:
(1 comment)
Patchset:
PS24:
> Just to clarify - it only affects CNVi cards, right?
No, works for full PCI too.
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Change subject: mb/starlabs/*: Unify WiFi driver settings
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Change subject: mb/starlabs/*: Tweak the performance profiles
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Change subject: mb/starlabs/starlite_adl: Add SSDT entry for volume keys
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Change subject: mb/starlabs/*: Configure GPIO UPDs for eSPI
......................................................................
mb/starlabs/*: Configure GPIO UPDs for eSPI
FSP defaults to using pins that are used for LPC; given that
coreboot and these boards only supports eSPI, set these pins
accordingly.
Change-Id: Ide4d92211fa7ab496c38ce1c4e895337c269d247
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/byte_adl/variants/mk_ii/Makefile.mk
A src/mainboard/starlabs/byte_adl/variants/mk_ii/ramstage.c
M src/mainboard/starlabs/starbook/variants/adl/ramstage.c
M src/mainboard/starlabs/starbook/variants/rpl/ramstage.c
M src/mainboard/starlabs/starfighter/variants/rpl/ramstage.c
M src/mainboard/starlabs/starlite_adl/variants/mk_v/Makefile.mk
A src/mainboard/starlabs/starlite_adl/variants/mk_v/ramstage.c
7 files changed, 53 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/85691/4
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Change subject: mb/google/nissa/var/telith: Disable stylus function
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/telith/gpio.c:
https://review.coreboot.org/c/coreboot/+/85738/comment/0f64dde1_3e7be66f?us… :
PS2, Line 46: PAD_CFG_GPO
> Why GPO and not NC?
Because the external environment is floating, EE requires setting GPIO output to be pulled high or low
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