coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjo: Add new supported memory part
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85735?usp=email ) Change subject: mb/google/nissa/var/pujjo: Add new supported memory part ...................................................................... mb/google/nissa/var/pujjo: Add new supported memory part Add pujjo new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Hynix H58G56CK8BX146 BUG=b:385659484 TEST=Use part_id_gen to generate related settings Change-Id: Idb48e849424aac79ef9af29f21b84194455c813e Signed-off-by: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85735 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/pujjo/memory/Makefile.mk M src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjo/memory/Makefile.mk index 3993dc6..6eb1600 100644 --- a/src/mainboard/google/brya/variants/pujjo/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjo/memory/Makefile.mk @@ -10,3 +10,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 3(0b0011) Parts = MT62F1G32D4DR-031 WT:B SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 4(0b0100) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 5(0b0101) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 6(0b0110) Parts = H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt index 93edc7d..d6ddf1b 100644 --- a/src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjo/memory/dram_id.generated.txt @@ -14,3 +14,4 @@ K3KL6L60GM-MGCT 5 (0101) K3KL8L80CM-MGCT 4 (0100) MT62F1G32D2DS-026 WT:B 4 (0100) +H58G56CK8BX146 6 (0110) diff --git a/src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt index 61d49b8..15857dd 100644 --- a/src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt @@ -19,3 +19,4 @@ K3KL6L60GM-MGCT K3KL8L80CM-MGCT MT62F1G32D2DS-026 WT:B +H58G56CK8BX146 -- To view, visit https://review.coreboot.org/c/coreboot/+/85735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb48e849424aac79ef9af29f21b84194455c813e Gerrit-Change-Number: 85735 Gerrit-PatchSet: 5 Gerrit-Owner: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85656?usp=email ) Change subject: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree ...................................................................... mb/google/nissa/var/rull: Add G2 touchscreen to devicetree Add G2 touchscreen override devicetree. BUG=b:384871815 BRANCH=None TEST=1. emerge-nissa coreboot chromeos-bootimage 2. touchpanel function is normal and 'evtest' command displays the touch point Change-Id: I0d68b8d09f2fd280dea17a0542243b88618b5fa1 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85656 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index 633d5bc..d4b773a 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -354,6 +354,20 @@ register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2 Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end device ref i2c3 on chip drivers/i2c/rt5645 -- To view, visit https://review.coreboot.org/c/coreboot/+/85656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d68b8d09f2fd280dea17a0542243b88618b5fa1 Gerrit-Change-Number: 85656 Gerrit-PatchSet: 4 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Enable FPS
by Subrata Banik (Code Review) 24 Dec '24

24 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85687?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Enable FPS ...................................................................... mb/google/fatcat/var/fatcat: Enable FPS Lists of changes: - GPIO programmimg when FW_CONFIG bit 17 is set FPMCU_PWREN -> GPP_E19 -> OUTPUT SOC_INT_L -> GPP_D1 -> INPUT FPMCU_FW_UPDATE -> GPP_E20 -> NF1 FPS_RST_N -> GPP_C15 -> OUTPUT GPP_F16_GSPI0A_CLK -> GPP_F16 -> SPI CLK -> NF8 GPP_F15_GSPI0A_MISO -> GPP_F15 -> SPI MISO -> NF8 GPP_F14_GPSI0A_MOSI -> GPP_F14 -> SPI MOSI -> NF8 GPP_F18_GSPI0A_CS0 -> GPP_F18 -> SPI CS -> NF8 - GPIO programmimg when FW_CONFIG bit 17 is not set GPP_E19 -> NC MOD_TCSS1_TYP_A_VBUS_EN -> GPP_D1 -> OUTPUT GPP_E20 -> NC GPP_C15 -> NC GPP_F16 -> NC GPP_F15 -> NC GPP_F14 -> NC GPP_F18 -> NC - ACPI Entry - Keep ISH (0x12.0) enable for GSPI0A to be operational - Keep GSPI0/1 disable and GSPI0A enable (PCI) BUG=b:377595986 TEST=TBD Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85687 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 3 files changed, 70 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index b061f7c..728d0f9 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -474,6 +474,42 @@ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF8), }; +static const struct pad_config fp_disable_pads[] = { + PAD_NC(GPP_C15, NONE), + /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F18, NONE), +}; + +static const struct pad_config fp_enable_pads[] = { + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO_LOCK(GPP_C15, 1, LOCK_CONFIG), + /* GPP_D01: FPS_SOC_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D01, NONE, PWROK, LEVEL, INVERT), + /* GPP_E19: FPMCU_PWREN */ + PAD_CFG_GPO(GPP_E19, 1, DEEP), + /* GPP_E20: FPMCU_FW_UPDATE */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_F14: GPSI0A_MOSI */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF8), + /* GPP_F15: GSPI0A_MISO */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF8), + /* GPP_F16: GPSI0A_CLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF8), + /* GPP_F18: GSPI0A_CS0 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF8), +}; + +static const struct pad_config pre_mem_fp_enable_pads[] = { + /* GPP_C15: FPS_RST_N */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), +}; + void fw_config_configure_pre_mem_gpio(void) { if (!fw_config_is_provisioned()) { @@ -517,6 +553,10 @@ */ if (!fw_config_probe(FW_CONFIG(CELLULAR, CELLULAR_ABSENT))) GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads); + + if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) + GPIO_CONFIGURE_PADS(pre_mem_fp_enable_pads); + } void fw_config_gpio_padbased_override(struct pad_config *padbased_table) @@ -607,4 +647,9 @@ /* NOTE: disable PEG (x8 slot) and x4 slot wake for now */ GPIO_PADBASED_OVERRIDE(padbased_table, peg_x4slot_wake_disable_pads); + + if (fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) + GPIO_CONFIGURE_PADS(fp_enable_pads); + else + GPIO_CONFIGURE_PADS(fp_disable_pads); } diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 47a5c3a..a5a1be1 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -130,8 +130,6 @@ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - /* GPP_C15: CRD1_CLK_EN */ - PAD_CFG_GPO(GPP_C15, 1, PLTRST), /* GPP_C16: TBT_LSX0_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GPP_C17: TBT_LSX0_RXD */ @@ -151,8 +149,6 @@ /* GPP_D00: IMGCLKOUT_1 */ PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), - /* GPP_D01: MOD_TCSS1_TYP_A_VBUS_EN */ - PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPP_D02: Not used */ PAD_NC(GPP_D02, NONE), /* GPP_D03: M.2_WWAN_PERST_GPIO_N */ @@ -234,10 +230,6 @@ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), - /* GPP_E19: PEG_SLOT_DGPU_SEL_N */ - PAD_CFG_GPO(GPP_E19, 1, PLTRST), - /* GPP_E20: PEG_SLOT_DGPU_PWR_OK */ - PAD_CFG_GPI(GPP_E20, NONE, PLTRST), /* GPP_E21: I2C_PMC_PD_INT_N */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22: THC0_SPI1_DSYNC */ @@ -277,16 +269,8 @@ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), - /* GPP_F14: Not used */ - PAD_NC(GPP_F14, NONE), - /* GPP_F15: Not used */ - PAD_NC(GPP_F15, NONE), - /* GPP_F16: Not used */ - PAD_NC(GPP_F16, NONE), /* GPP_F17: Not used */ PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH), - /* GPP_F18: TCH_PAD_INT_N */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), /* GPP_F19: GPP_PRIVACY_LED_CAM2 */ PAD_CFG_GPO(GPP_F19, 0, PLTRST), /* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */ diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index ca2ebb0..60fb95f 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -107,6 +107,12 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0A] = PchSerialIoPci, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -357,12 +363,31 @@ device ref ish on probe ISH ISH_ENABLE + probe FP FP_PRESENT chip drivers/intel/ish register "add_acpi_dma_property" = "true" device generic 0 on end end end + device ref gspi0a on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)" + register "wake" = "GPE0_DW1_01" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + register "enable_delay_ms" = "3" + device spi 0 on + probe FP FP_PRESENT + end + end # FPMCU + end + device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on -- To view, visit https://review.coreboot.org/c/coreboot/+/85687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifced5c779407b4ffcc69a7ed1297704def09b554 Gerrit-Change-Number: 85687 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat/var/francka: Fix early pad configuration for TPM
by Pranava Y N (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dtrain Hsu, Ian Feng, Subrata Banik. Pranava Y N has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/85736?usp=email ) Change subject: mb/google/fatcat/var/francka: Fix early pad configuration for TPM ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85736?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id08575d28f6f3bced74c0b301756fc8239cfd190 Gerrit-Change-Number: 85736 Gerrit-PatchSet: 4 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 06:54:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjo: Add new supported memory part
by Eric Lai (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Luca Lai, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Luca Lai. ( https://review.coreboot.org/c/coreboot/+/85735?usp=email ) Change subject: mb/google/nissa/var/pujjo: Add new supported memory part ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb48e849424aac79ef9af29f21b84194455c813e Gerrit-Change-Number: 85735 Gerrit-PatchSet: 4 Gerrit-Owner: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 06:44:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Disable stylus function
by Eric Lai (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kun Liu, Nick Vaccaro. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85738?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/telith: Disable stylus function ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85738/comment/22a270dd_3114848b?us… : PS3, Line 7: Disable disable or remove the stylus from this project? -- To view, visit https://review.coreboot.org/c/coreboot/+/85738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Gerrit-Change-Number: 85738 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 06:44:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
by Eric Lai (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kun Liu, Nick Vaccaro, Rui Zhou, Subrata Banik. Eric Lai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85656?usp=email ) Change subject: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d68b8d09f2fd280dea17a0542243b88618b5fa1 Gerrit-Change-Number: 85656 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 06:42:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Yidi Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 06:41:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85630?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/mt6316.c: https://review.coreboot.org/c/coreboot/+/85630/comment/baed86bf_e6065262?us… : PS10, Line 163: !!mod ? true : false; > just `return !!mode;` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 24 Dec 2024 06:39:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 24 Dec '24

24 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85630?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Code-Review+1 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6316 driver Add MT6316 driver in SoC folder. TEST=Build pass BUG=b:317009620 Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6316.h A src/soc/mediatek/common/mt6316.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6316.c 4 files changed, 1,155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85630/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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