coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/amd/birman_plus: Kconfig
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85493?usp=email ) Change subject: mb/amd/birman_plus: Kconfig ...................................................................... mb/amd/birman_plus: Kconfig Clean up WLAN and WWAN configuration flags based on the schematics Doc. 105-D99700-00C. Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman_plus/Kconfig 1 file changed, 30 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85493/1 diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index 462fece..a6c1999 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -99,11 +99,12 @@ help Enable the 19V rail for Eval Card PCIe slot +if BOARD_AMD_BIRMANPLUS_GLINDA choice prompt "DT SLOT/M.2 SSD1 ENABLE" default ENABLE_DT_SLOT_BIRMANPLUS help - Either DT slot or M.2 SSD1 can be used, as they are sharing PCIe lanes. + Either DT slot or M.2 SSD1 can be used, as they are sharing PCIe lanes. config ENABLE_DT_SLOT_BIRMANPLUS bool "Enable DT slot" @@ -113,25 +114,42 @@ config DISABLE_DT_M2_BIRMANPLUS bool "Disable both DT and M.2 slot" - endchoice choice - prompt "WLAN/WWAN Selection" - default WLAN0_WWAN0_BIRMANPLUS + prompt "GBE Enable/WWAN LANE1 Selection" + default ENABLE_GBE_BIRMANPLUS help - WLAN and WWAN lane configuration + When the M.2 x2 WLAN slot is enabled, the SD Card Reader is disabled. -config WLAN0_WWAN0_BIRMANPLUS - bool "Both WLAN and WWAN Enabled (1 lane each)" +config ENABLE_GBE_BIRMANPLUS + bool "Enable GBE (1 Lane WWAN)" -config WLAN01_BIRMANPLUS - bool "Only WLAN Enabled (2 lanes WLAN, 0 lanes WWAN)" +config ENABLE_WWAN02_BIRMANPLUS + bool "Enable WWAN (2 Lanes WWAN)" -config WWAN01_BIRMANPLUS - bool "Only WWAN Enabled (2 lanes WWAN, 0 lanes WLAN)" - +config DISABLE_WWAN_BIRMANPLUS + bool "Disable WWAN" endchoice + +choice + prompt "SD Card Enable/WLAN LANE1 Selection" + default ENABLE_SDCARD_BIRMANPLUS + help + When the M.2 x2 WWAN slot is enabled, the GbE LAN is disabled. + +config ENABLE_SDCARD_BIRMANPLUS + bool "Enable GBE (1 Lane WLAN)" + +config ENABLE_WLAN02_BIRMANPLUS + bool "Enable WLAN LANE1 (2 Lanes WLAN)" + +config DISABLE_WLAN_BIRMANPLUS + bool "Disable WLAN" +endchoice + +endif # BOARD_AMD_BIRMANPLUS_GLINDA + if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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[S] Change in coreboot[main]: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
by Subrata Banik (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Naveen M, Paul Menzel, Pranava Y N, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85282?usp=email ) Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Gerrit-Change-Number: 85282 Gerrit-PatchSet: 11 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:26:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Paul Menzel (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 12: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85362/comment/bbc59134_8c573be7?us… : PS12, Line 8: > The Booker's protocol is generally similar to CI-700, with some MTK modifications. […] Yes, I found a Web site for CI-700. Still, you should add a paragraph about the device. Especially as no other MediaTek device in coreboot seems to have used it until now. https://review.coreboot.org/c/coreboot/+/85362/comment/a71cafc4_5d03b115?us… : PS12, Line 20: [booker_init] AP hash rule: 0xbe00. > Hash rule is an algorithm that implements different hash functions for a device in MTK. How can I decode the value? -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:21:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Naveen M, Paul Menzel, Pranava Y N, Subrata Banik. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85282?usp=email ) Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs ...................................................................... Patch Set 11: (1 comment) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/85282/comment/2df22841_6761fd13?us… : PS9, Line 111: acpigen_write_ADR_soundwire_device(&config->alc711_address); > This CL should only include adlrvp and mtlrvp changes to ensure the existing platform behavior isn't […] Sure , keeping only adlrvp and mtlrvp in this CL and separate CL for fatcat. -- To view, visit https://review.coreboot.org/c/coreboot/+/85282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Gerrit-Change-Number: 85282 Gerrit-PatchSet: 11 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:21:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Update Soundwire codec address based on devicetree
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Naveen M, Pranava Y N, Subrata Banik. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85440?usp=email ) Change subject: mb/google/fatcat: Update Soundwire codec address based on devicetree ...................................................................... Patch Set 6: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9 Gerrit-Change-Number: 85440 Gerrit-PatchSet: 6 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:19:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Filip Lewiński (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Christian Walter, Julius Werner, Michał Żygowski, Yu-Ping Wu. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82695?usp=email ) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... Patch Set 9: (1 comment) Patchset: PS4: > [Done](https://review.coreboot.org/c/coreboot/+/82695/7..8/src/security/vboo…. […] Done [here*](https://review.coreboot.org/c/coreboot/+/82695/4..5/src/security/vbo…, my bad -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 9 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:19:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Filip Lewiński <filip.lewinski(a)3mdeb.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Naveen M, Paul Menzel, Pranava Y N, Varun Upadhyay. Hello Karthik Ramasubramanian, Naveen M, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85282?usp=email to look at the new patch set (#11). Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs ...................................................................... drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs - Use common config DRIVERS_SOUNDWIRE_ALC_BASE_7XX for ALC7xx variants - Introduce soundwire codec address in soundwire chip.h to calculate device address for acpi table based on overridetree. - Update devicetree and Kconfig to use common config. BUG=b:368495490 TEST=build coreboot image and boot on Intel RVP board. Disassemble SSDT and confirm ACPI entries are correct for alc7xx device. Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> Signed-off-by: Naveen M <naveen.m(a)intel.com> --- M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/alc711/chip.h M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 8 files changed, 22 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/85282/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Gerrit-Change-Number: 85282 Gerrit-PatchSet: 11 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: security: Allow vboot when INTEL_TXT enabled
by Filip Lewiński (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Christian Walter, Michał Żygowski, Yu-Ping Wu. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82695?usp=email ) Change subject: security: Allow vboot when INTEL_TXT enabled ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781 Gerrit-Change-Number: 82695 Gerrit-PatchSet: 9 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:16:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Fix register lock
by Patrick Rudolph (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85439?usp=email ) Change subject: soc/intel/xeon_sp/cpx: Fix register lock ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/85439/comment/5d04ff52_f88607d3?us… : PS2, Line 118: /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions > Comment is no longer true Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563 Gerrit-Change-Number: 85439 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:00:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Patrick Rudolph (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Johnny Lin, Morgan Jang. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email ) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... mb/ocp/tiogapass: Wait for BMC The mainboard code relies on IPMI communication with the BMC. Since the x86 and BMC start booting at the same time on ACPI G3 exit and the x86 is a bit faster, wait for the BMC to signal it's done booting by pulling GPP_F4 low. Fixes lot's of error messages about not working IPMI. TEST: Once GPP_F4 is low IPMI communication over the KCS is also working on ocp/tiogapass. Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/tiogapass/romstage.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85492/1 diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 283d5f1..a72a37d 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <delay.h> #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> #include <fsp/api.h> @@ -10,6 +11,7 @@ #include <soc/romstage.h> #include <string.h> #include <skxsp_tp_iio.h> +#include <timer.h> #include "ipmi.h" @@ -52,8 +54,32 @@ oem_update_iio(mupd); } +static void mainboard_wait_for_bmc_ready(void) +{ + struct stopwatch sw; + static const long timeout = 180 * 1000; + + printk(BIOS_DEBUG, "Waiting for BMC ready\n"); + gpio_input(GPP_F4); + + stopwatch_init_msecs_expire(&sw, timeout); + while (gpio_get(GPP_F4)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "BMC not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(100); + } + printk(BIOS_DEBUG, "BMC ready after %lld ms\n", + stopwatch_duration_msecs(&sw)); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { + /* Need to wait for BMC ready so that IPMI works. */ + mainboard_wait_for_bmc_ready(); + /* It's better to run get BMC selftest result first */ if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { ipmi_set_post_start(CONFIG_BMC_KCS_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>

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coreboot-gerrit December 2024