coreboot-gerrit December 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp/lbg: Add support to hide HDA
by Patrick Rudolph (Code Review) 04 Dec '24

04 Dec '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85496?usp=email ) Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA ...................................................................... soc/intel/xeon_sp/lbg: Add support to hide HDA The azalia audio device is usually unused on server platforms. Add code to hide it since FSP lacks this option and there's no official bit in the IFD to disable it. TEST: No HDA PCI device visible on ocp/tiogapass. Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lbg/Makefile.mk A src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h M src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/lbg/include/soc/pmc.h M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/skx/romstage.c 8 files changed, 56 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85496/1 diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 25dc4f6..82657f9 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -10,6 +10,7 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> +#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include <string.h> @@ -107,6 +108,10 @@ /* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); + + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); } uint32_t get_max_capacity_mib(void) diff --git a/src/soc/intel/xeon_sp/lbg/Makefile.mk b/src/soc/intel/xeon_sp/lbg/Makefile.mk index 5dedc83..c855003 100644 --- a/src/soc/intel/xeon_sp/lbg/Makefile.mk +++ b/src/soc/intel/xeon_sp/lbg/Makefile.mk @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += soc_pch.c soc_gpio.c -romstage-y += soc_pmutil.c soc_gpio.c +romstage-y += soc_pmutil.c soc_pch.c soc_gpio.c ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c lockdown.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h b/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h new file mode 100644 index 0000000..cfe74e8 --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DEVICE_AZALIA_H +#define DEVICE_AZALIA_H + +#define HDA_PCS 0x54 +#define HDA_PCS_PS_D3HOT 3 +#define HDA_FNCFG 0x530 + +#endif /* DEVICE_AZALIA_H */ diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h index 8c0b669..d365eb5 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h @@ -6,6 +6,7 @@ #define PID_CSME0 0x90 #define PID_ITSS 0xC4 #define PID_RTC 0xC3 +#define PID_PSF3 0xBC #define PID_DMI 0xEF #define PID_GPIOCOM5 0x11 #define PID_GPIOCOM4 0xAB diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h index 88a9b10..133703a 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h @@ -49,4 +49,7 @@ #define GPE0_DW_SHIFT(x) (4 * (x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 + +#define NST_PG_FDIS1 0x628 +#define NST_FDIS_DSP (1 << 23) #endif diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h index 2d87be3..acb1785 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -4,5 +4,6 @@ #define _SOC_SOC_PCH_H_ void pch_lock_dmictl(void); +void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c index 83ed20a..fc7dc8d 100644 --- a/src/soc/intel/xeon_sp/lbg/soc_pch.c +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/p2sb.h> +#include <soc/azalia_device.h> #include <soc/bootblock.h> #include <soc/soc_pch.h> +#include <soc/pch_pci_devs.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <soc/pmc.h> #include <console/console.h> @@ -56,3 +59,26 @@ uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } + +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) +#define PSF3_HDA_BASE_ADDRESS 0x1800 + +void pch_disable_hda(void) +{ + /* Ensure memory, io, and bus master are all disabled */ + pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + /* Put controller to D3 */ + pci_or_config32(PCH_DEV_HDA, HDA_PCS, HDA_PCS_PS_D3HOT); + /* Lock and disable everything */ + pci_write_config8(PCH_DEV_HDA, HDA_FNCFG, 0x15); + + /* Disable DSP in PMC */ + pmc_or_mmio32(NST_PG_FDIS1, NST_FDIS_DSP); + /* Hide PCI function */ + pcr_or32(PID_PSF3, PSF3_HDA_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, + PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); + + printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index f66022d..819fcc8 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,11 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/romstage.h> +#include <device/pci_def.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> +#include <soc/pch_pci_devs.h> +#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> - #include "chip.h" void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) @@ -24,6 +26,10 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; + + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); } uint8_t get_error_correction_type(const uint8_t RasModesEnabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/85496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Gerrit-Change-Number: 85496 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: mb/amd/birman_plus: port_descriptors
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Ana Carolina Cabral has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85495?usp=email ) Change subject: mb/amd/birman_plus: port_descriptors ...................................................................... Abandoned Moving to e920ba7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd66586504d869fe0ec01c9257fd506bab2763f Gerrit-Change-Number: 85495 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/amd/birman_plus: ec.c
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Ana Carolina Cabral has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85494?usp=email ) Change subject: mb/amd/birman_plus: ec.c ...................................................................... Abandoned Moving to e920ba7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4158995dc086b24a6c3d616b9127c790fdc276b5 Gerrit-Change-Number: 85494 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/amd/birman_plus: Kconfig
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Ana Carolina Cabral, Felix Held. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85493?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/amd/birman_plus: Kconfig ...................................................................... mb/amd/birman_plus: Kconfig Clean up WLAN and WWAN configuration flags based on the schematics Doc. 105-D99700-00C. Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman_plus/Kconfig M src/mainboard/amd/birman_plus/ec.c M src/mainboard/amd/birman_plus/port_descriptors_glinda.c M src/mainboard/amd/birman_plus/port_descriptors_phoenix.c 4 files changed, 42 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85493/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85493?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia310ea616006479b9a052afb99d08df6a11431f4 Gerrit-Change-Number: 85493 Gerrit-PatchSet: 4 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
by Angel Pons (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Johnny Lin, Morgan Jang, Patrick Rudolph. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85318?usp=email ) Change subject: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists ...................................................................... Patch Set 7: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85318/comment/30310464_e3fd1345?us… : PS7, Line 9: The board has 12 slots, each holding one DDR4 ECC RDIMM, on each socket. Nit: rephrase to avoid confusion: > The board has 12 DIMM slots per socket, each holding one DDR4 ECC RDIMM. File src/mainboard/ocp/tiogapass/romstage.c: https://review.coreboot.org/c/coreboot/+/85318/comment/66620f70_88a7a1bb?us… : PS6, Line 75: if (dimm >= 2) > 2 sockets, each with 6 channels, each with 2 dimms per channel. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/85318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Gerrit-Change-Number: 85318 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 15:04:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
by Angel Pons (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85139?usp=email ) Change subject: soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d726b5ae620282dd4c9036d536e5e51d19a0a0b Gerrit-Change-Number: 85139 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 15:00:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: arch/x86: Add breakpoint to stack canary
by Angel Pons (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Alicja Michalska, Andrey Petrov, Jeremy Compostella, Jérémy Compostella, Patrick Rudolph, Ronak Kanabar, Shuo Liu. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84833?usp=email ) Change subject: arch/x86: Add breakpoint to stack canary ...................................................................... Patch Set 17: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Gerrit-Change-Number: 84833 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 15:00:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp/skx: Fix CPU init
by Patrick Rudolph (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85289?usp=email ) Change subject: soc/intel/xeon_sp/skx: Fix CPU init ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/skx/cpu.c: https://review.coreboot.org/c/coreboot/+/85289/comment/a1c473c8_327e9622?us… : PS4, Line 123: msr.hi |= BIT20; > Do we know what this does? It's not officially documented. Looking at haswell: `Enable decay mode on C-state entry.` ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/85289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c Gerrit-Change-Number: 85289 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 14:57:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/amd/birman_plus: port_descriptors
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85495?usp=email ) Change subject: mb/amd/birman_plus: port_descriptors ...................................................................... mb/amd/birman_plus: port_descriptors Correct configuration flags based on previous patch. Change-Id: I7bd66586504d869fe0ec01c9257fd506bab2763f Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman_plus/port_descriptors_glinda.c M src/mainboard/amd/birman_plus/port_descriptors_phoenix.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85495/1 diff --git a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c index ae6f668..3fa2e9f 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_glinda.c @@ -41,7 +41,7 @@ .engine_type = PCIE_ENGINE, \ .port_present = true, \ .start_logical_lane = 15, \ - .end_logical_lane = 15, \ + .end_logical_lane = CONFIG(ENABLE_WLAN02_BIRMANPLUS) ? 14 : 15, \ .device_number = 2, \ .function_number = 2, \ .link_speed_capability = GEN_MAX, \ @@ -55,7 +55,7 @@ .engine_type = PCIE_ENGINE, \ .port_present = true, \ .start_logical_lane = 12, \ - .end_logical_lane = 12, \ + .end_logical_lane = CONFIG(ENABLE_WWAN02_BIRMANPLUS) ? 13 : 12, \ .device_number = 2, \ .function_number = 5, \ .link_speed_capability = GEN_MAX, \ @@ -68,7 +68,7 @@ #define glinda_gbe_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ + .port_present = CONFIG(ENABLE_GBE_BIRMANPLUS), \ .start_logical_lane = 13, \ .end_logical_lane = 13, \ .device_number = 2, \ @@ -83,7 +83,7 @@ #define glinda_sd_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ + .port_present = CONFIG(ENABLE_SDCARD_BIRMANPLUS), \ .start_logical_lane = 14, \ .end_logical_lane = 14, \ .device_number = 2, \ diff --git a/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c b/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c index dc23790..3ec4bb9 100644 --- a/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman_plus/port_descriptors_phoenix.c @@ -40,7 +40,7 @@ .engine_type = PCIE_ENGINE, \ .port_present = true, \ .start_lane = 15, \ - .end_lane = 15, \ + .end_lane = CONFIG(ENABLE_WLAN02_BIRMANPLUS) ? 14 : 15, \ .device_number = 2, \ .function_number = 2, \ .link_speed_capability = GEN_MAX, \ @@ -69,7 +69,7 @@ .engine_type = PCIE_ENGINE, \ .port_present = true, \ .start_lane = 12, \ - .end_lane = 12, \ + .end_lane = CONFIG(ENABLE_WWAN02_BIRMANPLUS) ? 13 : 12, \ .device_number = 2, \ .function_number = 3, \ .link_speed_capability = GEN_MAX, \ @@ -82,7 +82,7 @@ #define gbe_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = true, \ + .port_present = CONFIG(ENABLE_GBE_BIRMANPLUS), \ .start_lane = 13, \ .end_lane = 13, \ .device_number = 1, \ @@ -97,7 +97,7 @@ #define sd_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ - .port_present = false, \ + .port_present = CONFIG(ENABLE_SDCARD_BIRMANPLUS), \ .start_lane = 14, \ .end_lane = 14, \ .device_number = 2, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/85495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7bd66586504d869fe0ec01c9257fd506bab2763f Gerrit-Change-Number: 85495 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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[XS] Change in coreboot[main]: mb/amd/birman_plus: ec.c
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85494?usp=email ) Change subject: mb/amd/birman_plus: ec.c ...................................................................... mb/amd/birman_plus: ec.c Correct WLAN and WWAN configuration flags based on previous patch. Change-Id: I4158995dc086b24a6c3d616b9127c790fdc276b5 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman_plus/ec.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/85494/1 diff --git a/src/mainboard/amd/birman_plus/ec.c b/src/mainboard/amd/birman_plus/ec.c index 2ddc049..3d79116 100644 --- a/src/mainboard/amd/birman_plus/ec.c +++ b/src/mainboard/amd/birman_plus/ec.c @@ -171,12 +171,12 @@ tmp |= ECE_LOM_PWR_EN | ECE_SSD0_PWR_EN | ECE_SD_PWR_EN; tmp |= ECE_CAM_PWR_EN | ECE_FPR_N_GBE_SEL; tmp &= ~ECE_BT_N_TPNL_SEL; - if (CONFIG(WLAN01_BIRMANPLUS)) { // no WWAN, turn off WWAN power + if (CONFIG(DISABLE_WWAN_BIRMANPLUS)) { // no WWAN, turn off WWAN power tmp &= ~ECE_WWAN_PWR_EN; } else { tmp |= ECE_WWAN_PWR_EN; } - if (CONFIG(WWAN01_BIRMANPLUS)) { // no WLAN, turn off WLAN power + if (CONFIG(DISABLE_WLAN_BIRMANPLUS)) { // no WLAN, turn off WLAN power tmp &= ~ECE_WLAN_PWR_EN; } else { tmp |= ECE_WLAN_PWR_EN; @@ -185,12 +185,12 @@ ec_write(EC_GPIO_E_ADDR, tmp); tmp = ec_read(EC_GPIO_F_ADDR); - if (CONFIG(WLAN01_BIRMANPLUS)) { + if (CONFIG(ENABLE_WLAN02_BIRMANPLUS)) { tmp |= ECF_WWAN0_N_WLAN1_SW; } else { tmp &= ~ECF_WWAN0_N_WLAN1_SW; } - if (CONFIG(WWAN01_BIRMANPLUS)) { + if (CONFIG(ENABLE_WWAN02_BIRMANPLUS)) { tmp |= ECF_WLAN0_N_WWAN1_SW; } else { tmp &= ~ECF_WLAN0_N_WWAN1_SW; -- To view, visit https://review.coreboot.org/c/coreboot/+/85494?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4158995dc086b24a6c3d616b9127c790fdc276b5 Gerrit-Change-Number: 85494 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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