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[S] Change in coreboot[main]: mb/google/fatcat: Update flash layout
by Subrata Banik (Code Review) 04 Dec '24

04 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85497?usp=email ) Change subject: mb/google/fatcat: Update flash layout ...................................................................... mb/google/fatcat: Update flash layout This patch updates the flash layout for Fatcat variants to ensure the flash layout is in alignment with the previous generation CrOS devices like Rex. SI_ALL: 9MB -> 8MB SI_BIOS: 23MB -> 24MB BUG=b:382247229 TEST=Able to build and boot google/fatcat. Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd M src/mainboard/google/fatcat/chromeos.fmd 2 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85497/1 diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd index 8d41977..0e1e636 100644 --- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd @@ -1,23 +1,14 @@ FLASH 32M { - SI_ALL 9M { + SI_ALL 8M { SI_DESC 16K SI_ME } - SI_BIOS 23M { + SI_BIOS 24M { RW_SECTION_A 7680K { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7680K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -31,8 +22,17 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7680K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_LEGACY(CBFS) 1M - RW_UNUSED 2M + RW_UNUSED 3M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd index 4b42403..ca29bbc 100644 --- a/src/mainboard/google/fatcat/chromeos.fmd +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -1,23 +1,14 @@ FLASH 32M { - SI_ALL 9M { + SI_ALL 8M { SI_DESC 16K SI_ME } - SI_BIOS 23M { + SI_BIOS 24M { RW_SECTION_A 7M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -31,8 +22,17 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_LEGACY(CBFS) 1M - RW_UNUSED 3M + RW_UNUSED 4M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M { -- To view, visit https://review.coreboot.org/c/coreboot/+/85497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I716fae09dee0c05b8b840dc80647d7959aa03a50 Gerrit-Change-Number: 85497 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: util/intelp2m: Rework platform packages
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Maxim. David Hendricks has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/71167?usp=email ) Change subject: util/intelp2m: Rework platform packages ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: Hi @max.senia.poliak@gmail.com, would you like to rebase this patch chain? We'll try to get this all merged during our new fortnightly patch review meetings. -- To view, visit https://review.coreboot.org/c/coreboot/+/71167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e0aa56efa2430ac6524c6977f8b6fd13113edf9 Gerrit-Change-Number: 71167 Gerrit-PatchSet: 12 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 18:22:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: util/intelp2m: Print the current project version
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67321?usp=email ) Change subject: util/intelp2m: Print the current project version ...................................................................... util/intelp2m: Print the current project version Print the current project version in the console and in the generated file with the pad configuration. This makes support easier, since we know which version of the utility was used and whether we need to re-generate the configuration file if an error was made in the latest changes in the code. The version string includes several parts: {major}.{minor}-{last commit in the intelp2m directory}-{?dirty} The major is incremented if a new platform is added, minor - if changes in functionality are made. Add dirty if the changes were not taken into account using git. Use the following command to print the version: make version Change-Id: Id2fd0757c003004af976309a44dbbfff0eb517a7 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67321 Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/intelp2m/Makefile M util/intelp2m/main.go A util/intelp2m/scripts/linux/version.sh A util/intelp2m/version.txt 4 files changed, 54 insertions(+), 20 deletions(-) Approvals: David Hendricks: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelp2m/Makefile b/util/intelp2m/Makefile index ea44db4..5f6bc29 100644 --- a/util/intelp2m/Makefile +++ b/util/intelp2m/Makefile @@ -1,15 +1,23 @@ ## SPDX-License-Identifier: GPL-2.0-only -# simple makefile for the project -OUTPUT_DIR = generate -PROJECT_NAME = intelp2m +PROJECT_NAME := intelp2m +THIS_FILE := $(lastword $(MAKEFILE_LIST)) +THIS_DIR := $(abspath $(dir $(THIS_FILE))) +SCRIPTS_DIR := $(THIS_DIR)/scripts/linux -default: +OUTPUT_DIR := $(THIS_DIR)/generate +VERSION ?= $(shell $(SCRIPTS_DIR)/version.sh) +LDFLAGS = "-X main.Version=$(VERSION)" + +default: version go version - go build -v -o $(PROJECT_NAME) + go build -ldflags=$(LDFLAGS) -v test: go test ./... -v -count=1 clean: - rm -Rf $(PROJECT_NAME) $(OUTPUT_DIR) + rm -Rf $(THIS_DIR)/$(PROJECT_NAME) $(OUTPUT_DIR) + +version: + @echo $(VERSION) diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index 38a3b5fc..1f3333b 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -9,19 +9,29 @@ "review.coreboot.org/coreboot.git/util/intelp2m/parser" ) +var ( + // Version is injected into main during project build + Version string = "Unknown" +) + +// printVersion - print the utility version in the console +func printVersion() { + fmt.Printf("[ intelp2m ] Version: %s\n", Version) +} + // generateOutputFile - generates include file // parser : parser data structure func generateOutputFile(parser *parser.ParserData) (err error) { - - config.OutputGenFile.WriteString(`/* SPDX-License-Identifier: GPL-2.0-only */ + header := fmt.Sprintf(`/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef CFG_GPIO_H #define CFG_GPIO_H #include <gpio.h> -/* Pad configuration was generated automatically using intelp2m utility */ -static const struct pad_config gpio_table[] = {`) +/* Pad configuration was generated automatically using intelp2m %s */ +static const struct pad_config gpio_table[] = {`, Version) + config.OutputGenFile.WriteString(header + "\n") // Add the pads map parser.PadMapFprint() config.OutputGenFile.WriteString(`}; @@ -48,14 +58,14 @@ nonCheckFlag := flag.Bool("n", false, - "Generate macros without checking.\n" + - "\tIn this case, some fields of the configuration registers\n" + - "\tDW0 will be ignored.\n") + "Generate macros without checking.\n"+ + "\tIn this case, some fields of the configuration registers\n"+ + "\tDW0 will be ignored.\n") - infoLevels := []*bool { - flag.Bool("i", false, "Show pads function in the comments"), - flag.Bool("ii", false, "Show DW0/DW1 value in the comments"), - flag.Bool("iii", false, "Show ignored bit fields in the comments"), + infoLevels := []*bool{ + flag.Bool("i", false, "Show pads function in the comments"), + flag.Bool("ii", false, "Show DW0/DW1 value in the comments"), + flag.Bool("iii", false, "Show ignored bit fields in the comments"), flag.Bool("iiii", false, "Show target PAD_CFG() macro in the comments"), } @@ -64,7 +74,7 @@ "\t1 - gpio.h\n"+ "\t2 - your template\n\t") - platform := flag.String("p", "snr", "set platform:\n"+ + platform := flag.String("p", "snr", "set platform:\n"+ "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ "\tapl - Apollo Lake SoC\n"+ @@ -75,11 +85,12 @@ "\tmtl - MeteorLake SoC\n"+ "\tebg - Emmitsburg PCH with Xeon SP\n") - fieldstyle := flag.String("fld", "none", "set fields macros style:\n"+ + fieldstyle := flag.String("fld", "none", "set fields macros style:\n"+ "\tcb - use coreboot style for bit fields macros\n"+ "\tfsp - use fsp style\n"+ "\traw - do not convert, print as is\n") + printVersion() flag.Parse() config.IgnoredFieldsFlagSet(*ignFlag) @@ -88,7 +99,7 @@ for level, flag := range infoLevels { if *flag { config.InfoLevelSet(level + 1) - fmt.Printf("Info level: Use level %d!\n", level + 1) + fmt.Printf("Info level: Use level %d!\n", level+1) break } } diff --git a/util/intelp2m/scripts/linux/version.sh b/util/intelp2m/scripts/linux/version.sh new file mode 100755 index 0000000..565063a --- /dev/null +++ b/util/intelp2m/scripts/linux/version.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env sh + +SCRIPTS_DIR=$(cd "$(dirname "$0")" && pwd) +PROJECT_DIR="${SCRIPTS_DIR}/../.." + +VERSION=$(cat ${PROJECT_DIR}/version.txt) +LAST_COMMIT=$(git log --oneline -n 1 --pretty=format:%h ${PROJECT_DIR}) +DIFF=$(git diff ${PROJECT_DIR}) + +if [ -z "$DIFF" ]; then + echo "${VERSION}-${LAST_COMMIT}" +else + echo "${VERSION}-${LAST_COMMIT}-dirty" +fi diff --git a/util/intelp2m/version.txt b/util/intelp2m/version.txt new file mode 100644 index 0000000..9459d4b --- /dev/null +++ b/util/intelp2m/version.txt @@ -0,0 +1 @@ +1.1 -- To view, visit https://review.coreboot.org/c/coreboot/+/67321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2fd0757c003004af976309a44dbbfff0eb517a7 Gerrit-Change-Number: 67321 Gerrit-PatchSet: 21 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: util/intelp2m: Print the current project version
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Maxim, Paul Menzel. David Hendricks has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/67321?usp=email ) Change subject: util/intelp2m: Print the current project version ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/67321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2fd0757c003004af976309a44dbbfff0eb517a7 Gerrit-Change-Number: 67321 Gerrit-PatchSet: 20 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 04 Dec 2024 18:17:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: intelp2m/patform/sunrise: Add unit tests
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67132?usp=email ) ( 19 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: intelp2m/patform/sunrise: Add unit tests ...................................................................... intelp2m/patform/sunrise: Add unit tests - The generated map of long and short macros should correspond to the reference ones for all pads (INTEL-SUNRISE-PCH/PAD-MAP). The test suite is based on the generated macros of a real platform. - generated field macros should correspond to the RO_FIELDS mask (INTEL-SUNRISE-PCH/MASK); - macros generated from the zero values bits of the DW registers should correspond to the reference ones (INTEL-SUNRISE-PCH/EMRTY). Use the following command in the console to run all the tests in the project: make test Change-Id: I15c7483f120a330849d4bad036427be205b0911c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67132 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- M util/intelp2m/Makefile A util/intelp2m/platforms/snr/snr_test.go A util/intelp2m/platforms/test/suite.go 3 files changed, 274 insertions(+), 0 deletions(-) Approvals: Maximilian Brune: Looks good to me, but someone else must approve build bot (Jenkins): Verified Alicja Michalska: Looks good to me, but someone else must approve David Hendricks: Looks good to me, approved diff --git a/util/intelp2m/Makefile b/util/intelp2m/Makefile index 2731bc7..ea44db4 100644 --- a/util/intelp2m/Makefile +++ b/util/intelp2m/Makefile @@ -8,5 +8,8 @@ go version go build -v -o $(PROJECT_NAME) +test: + go test ./... -v -count=1 + clean: rm -Rf $(PROJECT_NAME) $(OUTPUT_DIR) diff --git a/util/intelp2m/platforms/snr/snr_test.go b/util/intelp2m/platforms/snr/snr_test.go new file mode 100644 index 0000000..8a52396 --- /dev/null +++ b/util/intelp2m/platforms/snr/snr_test.go @@ -0,0 +1,209 @@ +package snr_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + sunrise := snr.PlatformSpecific{} + test.Suite{ + { /* GPP_A1 - LAD0 */ + Pad: test.Pad{ID: "GPP_A1", DW0: 0x84000402, DW1: 0x00003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, UP_20K, PLTRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),", + }, + }, + { /* GPP_A5 - LFRAME# */ + Pad: test.Pad{ID: "GPP_A5", DW0: 0x84000600, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPP_A22 - GPIO */ + Pad: test.Pad{ID: "GPP_A22", DW0: 0x84000102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, PLTRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_B3 - GPIO */ + Pad: test.Pad{ID: "GPP_B3", DW0: 0x44000201, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO(GPP_B3, 1, DEEP),", + Long: "_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),", + }, + }, + { /* GPP_B5 - GPIO */ + Pad: test.Pad{ID: "GPP_B5", DW0: 0x84000100, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, PLTRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),", + }, + }, + { /* GPP_B8 - NC */ + Pad: test.Pad{ID: "GPP_B8", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_NC(GPP_B8, NONE),", + Long: "_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),", + }, + }, + { /* GPP_C2 - GPIO */ + Pad: test.Pad{ID: "GPP_C2", DW0: 0x44000201, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO(GPP_C2, 1, DEEP),", + Long: "_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0),", + }, + }, + { /* GPP_C10 - GPIO */ + Pad: test.Pad{ID: "GPP_C10", DW0: 0x04000000, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),", + }, + }, + { /* GPP_C22 - UART2_RTS# */ + Pad: test.Pad{ID: "GPP_C22", DW0: 0x84000600, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPP_C23 - GPIO */ + Pad: test.Pad{ID: "GPP_C23", DW0: 0x40880102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT),", + Long: "_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_D0 - GPIO */ + Pad: test.Pad{ID: "GPP_D0", DW0: 0x84000200, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO(GPP_D0, 0, PLTRST),", + Long: "_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPP_D16 - GPIO */ + Pad: test.Pad{ID: "GPP_D16", DW0: 0x84000100, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),", + }, + }, + { /* GPP_E0 - SATAXPCIE0 */ + Pad: test.Pad{ID: "GPP_E0", DW0: 0x84000502, DW1: 0x00003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_E0, UP_20K, PLTRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),", + }, + }, + { /* GPP_E7 - GPIO */ + Pad: test.Pad{ID: "GPP_E7", DW0: 0x84000102, DW1: 0x00000000, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, OFF, DRIVER),", + Long: "_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPP_F2 - GPIO */ + Pad: test.Pad{ID: "GPP_F2", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_NC(GPP_F2, NONE),", + Long: "_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),", + }, + }, + { /* GPP_F12 - GPIO */ + Pad: test.Pad{ID: "GPP_F12", DW0: 0x80900102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST),", + Long: "_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_F13 - GPIO */ + Pad: test.Pad{ID: "GPP_F13", DW0: 0x80100102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST),", + Long: "_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_F14 - GPIO */ + Pad: test.Pad{ID: "GPP_F14", DW0: 0x40900102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_APIC_LOW(GPP_F14, NONE, DEEP),", + Long: "_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_H13 - GPIO */ + Pad: test.Pad{ID: "GPP_H13", DW0: 0x80100102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_APIC_HIGH(GPP_H13, NONE, PLTRST),", + Long: "_PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPD1 - GPIO */ + Pad: test.Pad{ID: "GPD1", DW0: 0x04000200, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO(GPD1, 0, PWROK),", + Long: "_PAD_CFG_STRUCT(GPD1, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPD2 - LAN_WAKE# */ + Pad: test.Pad{ID: "GPD2", DW0: 0x00080602, DW1: 0x00003c00, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),", + Long: "_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),", + }, + }, + { /* GPD3 - PWRBTN# */ + Pad: test.Pad{ID: "GPD3", DW0: 0x04000502, DW1: 0x00003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),", + Long: "_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),", + }, + }, + { /* GPD7 - GPIO */ + Pad: test.Pad{ID: "GPD7", DW0: 0x84000103, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PLTRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) | 1, 0),", + }, + }, + { /* GPP_I1 - DDPC_HPD1 */ + Pad: test.Pad{ID: "GPP_I1", DW0: 0x84000502, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_I8 - DDPC_CTRLDATA */ + Pad: test.Pad{ID: "GPP_I8", DW0: 0x84000500, DW1: 0x00001000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_I8, DN_20K, PLTRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),", + }, + }, + }.Run(t, "INTEL-SUNRISE-PCH/PAD-MAP", sunrise) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_Axx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_Axx, NATIVE, PLTRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_Axx, PAD_FUNC(NF7) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + }.Run(t, "INTEL-SUNRISE-PCH/MASK", sunrise) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_Bxx", DW0: 0x00000000, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPP_Bxx, 0, NONE, RSMRST, LEVEL, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_Bxx, PAD_FUNC(GPIO) | PAD_RESET(RSMRST), 0),", + }, + }, + }.Run(t, "INTEL-SUNRISE-PCH/EMRTY", sunrise) +} diff --git a/util/intelp2m/platforms/test/suite.go b/util/intelp2m/platforms/test/suite.go new file mode 100644 index 0000000..8ec4886 --- /dev/null +++ b/util/intelp2m/platforms/test/suite.go @@ -0,0 +1,62 @@ +package test + +import ( + "fmt" + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/config" +) + +type ( + Pad struct { + ID string + DW0 uint32 + DW1 uint32 + Ownership uint8 + } + Macro struct { + Short string + Long string + } + TestCase struct { + Pad + Macro + } + PlatformSpecificIf interface { + GenMacro(string, uint32, uint32, uint8) string + } + Suite []TestCase +) + +func (p Pad) toShortMacro(platform PlatformSpecificIf) string { + config.FldStyleSet("none") + config.NonCheckingFlagSet(true) + return platform.GenMacro(p.ID, p.DW0, p.DW1, p.Ownership) +} + +func (p Pad) toLongMacro(platform PlatformSpecificIf) string { + config.FldStyleSet("cb") + config.NonCheckingFlagSet(false) + return platform.GenMacro(p.ID, p.DW0, p.DW1, p.Ownership) +} + +func (m *Macro) checkFor(platform PlatformSpecificIf, pad Pad) error { + var format string = "%s macro\nExpects: '%s'\nActually: '%s'\n\n" + if actually := pad.toLongMacro(platform); m.Long != "" && m.Long != actually { + return fmt.Errorf(format, "LONG", m.Long, actually) + } + if actually := pad.toShortMacro(platform); m.Short != "" && m.Short != actually { + return fmt.Errorf(format, "SHORT", m.Short, actually) + } + return nil +} + +func (suite Suite) Run(t *testing.T, label string, platform PlatformSpecificIf) { + t.Run(label, func(t *testing.T) { + for _, testcase := range suite { + if err := testcase.Macro.checkFor(platform, testcase.Pad); err != nil { + t.Errorf("Test failed for pad %s\n%v", testcase.Pad.ID, err) + } + } + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/67132?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15c7483f120a330849d4bad036427be205b0911c Gerrit-Change-Number: 67132 Gerrit-PatchSet: 21 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Maxim Polyakov <m.poliakov(a)yahoo.com>

1 0

[M] Change in coreboot[main]: intelp2m/patform/lewisburg: Add unit tests
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67133?usp=email ) ( 19 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: intelp2m/patform/lewisburg: Add unit tests ...................................................................... intelp2m/patform/lewisburg: Add unit tests - The generated map of long and short macros should correspond to the reference ones for all pads (INTEL-LEWISBURG-PCH/PAD-MAP). The test suite is based on the generated macros of a real platform. - generated field macros should correspond to the RO_FIELDS mask (INTEL-LEWISBURG-PCH/MASK); - macros generated from the zero values bits of the DW registers should correspond to the reference ones (INTEL-LEWISBURG-PCH/EMRTY). Change-Id: Iec18462be8428c3f37d546332211a730ee589a2d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67133 Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- A util/intelp2m/platforms/lbg/lbg_test.go 1 file changed, 175 insertions(+), 0 deletions(-) Approvals: Alicja Michalska: Looks good to me, but someone else must approve David Hendricks: Looks good to me, approved Maximilian Brune: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/util/intelp2m/platforms/lbg/lbg_test.go b/util/intelp2m/platforms/lbg/lbg_test.go new file mode 100644 index 0000000..62eba804 --- /dev/null +++ b/util/intelp2m/platforms/lbg/lbg_test.go @@ -0,0 +1,175 @@ +package lbg_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/lbg" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + lewisburg := lbg.PlatformSpecific{InheritanceMacro: snr.PlatformSpecific{}} + test.Suite{ + { /* GPP_A1 - ESPI_ALERT1# */ + Pad: test.Pad{ID: "GPP_A1", DW0: 0x44000c00, DW1: 0x00003000, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPP_A12 - LFRAME# */ + Pad: test.Pad{ID: "GPP_A12", DW0: 0x80880102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_SCI(GPP_A12, NONE, PLTRST, LEVEL, INVERT),", + Long: "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_A16 - GPIO */ + Pad: test.Pad{ID: "GPP_A16", DW0: 0x44000201, DW1: 0x00000000, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO_GPIO_DRIVER(GPP_A16, 1, DEEP, NONE),", + Long: "_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPP_A20 - GPIO */ + Pad: test.Pad{ID: "GPP_A20", DW0: 0x04000100, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, RSMRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),", + }, + }, + { /* GPP_B10 - GPIO */ + Pad: test.Pad{ID: "GPP_B10", DW0: 0x04000102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, RSMRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_B20 - GPIO */ + Pad: test.Pad{ID: "GPP_B20", DW0: 0x04000200, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO(GPP_B20, 0, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPP_B23 - PCHHOT# */ + Pad: test.Pad{ID: "GPP_B23", DW0: 0x04000a00, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_B23, NONE, RSMRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPP_F0 - SATAXPCIE3 */ + Pad: test.Pad{ID: "GPP_F0", DW0: 0x04000502, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_F0, NONE, RSMRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_C10 - GPIO */ + Pad: test.Pad{ID: "GPP_C10", DW0: 0x04000000, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPP_C10, 0, NONE, RSMRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF), 0),", + }, + }, + { /* GPP_C23 - GPIO */ + Pad: test.Pad{ID: "GPP_C23", DW0: 0x40880102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT),", + Long: "_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_D1 - GPIO */ + Pad: test.Pad{ID: "GPP_D1", DW0: 0x04000200, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPO(GPP_D1, 0, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + { /* GPP_D16 - GPIO */ + Pad: test.Pad{ID: "GPP_D16", DW0: 0x84000100, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),", + }, + }, + { /* GPP_E0 - SATAXPCIE0 */ + Pad: test.Pad{ID: "GPP_E0", DW0: 0x04000502, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_E0, NONE, RSMRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_E7 - GPIO */ + Pad: test.Pad{ID: "GPP_E7", DW0: 0x40840102, DW1: 0x00000000, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, INVERT),", + Long: "_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPP_F2 - GPIO */ + Pad: test.Pad{ID: "GPP_F2", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_NC(GPP_F2, NONE),", + Long: "_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),", + }, + }, + { /* GPP_F12 - GPIO */ + Pad: test.Pad{ID: "GPP_F12", DW0: 0x80900102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_APIC_LOW(GPP_F12, NONE, PLTRST),", + Long: "_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_F13 - GPIO */ + Pad: test.Pad{ID: "GPP_F13", DW0: 0x80100102, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_APIC_HIGH(GPP_F13, NONE, PLTRST),", + Long: "_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),", + }, + }, + { /* GPP_H10 - NC */ + Pad: test.Pad{ID: "GPP_H10", DW0: 0x44000300, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_NC(GPP_H10, NONE),", + Long: "_PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),", + }, + }, + { /* GPP_L1 - CSME_INTR_OUT */ + Pad: test.Pad{ID: "GPP_L1", DW0: 0x44000700, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_L1, NONE, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_L1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),", + }, + }, + { /* GPP_L19 - TESTCH1_CLK */ + Pad: test.Pad{ID: "GPP_L19", DW0: 0x04000600, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_L19, NONE, RSMRST, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_L19, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),", + }, + }, + }.Run(t, "INTEL-LEWISBURG-PCH/PAD-MAP", lewisburg) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_Axx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_Axx, NATIVE, PLTRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_Axx, PAD_FUNC(NF7) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + }.Run(t, "INTEL-LEWISBURG-PCH/MASK", lewisburg) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_Bxx", DW0: 0x00000000, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPP_Bxx, 0, NONE, RSMRST, LEVEL, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_Bxx, PAD_FUNC(GPIO) | PAD_RESET(RSMRST), 0),", + }, + }, + }.Run(t, "INTEL-LEWISBURG-PCH/EMRTY", lewisburg) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/67133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec18462be8428c3f37d546332211a730ee589a2d Gerrit-Change-Number: 67133 Gerrit-PatchSet: 21 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intelp2m/patform/apollolake: Add unit tests
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67134?usp=email ) ( 20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: intelp2m/patform/apollolake: Add unit tests ...................................................................... intelp2m/patform/apollolake: Add unit tests - The generated map of long and short macros should correspond to the reference ones for all pads (INTEL-APOLLO-PCH/PAD-MAP). The test suite is based on the generated macros of a real platform. - generated field macros should correspond to the RO_FIELDS mask (INTEL-APOLLO-PCH/MASK); - macros generated from the zero values bits of the DW registers should correspond to the reference ones (INTEL-APOLLO-PCH/EMRTY). Change-Id: I1c47edb31d24930068486c74147c5fbc9b18b4b6 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67134 Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A util/intelp2m/platforms/apl/apl_test.go 1 file changed, 167 insertions(+), 0 deletions(-) Approvals: Alicja Michalska: Looks good to me, but someone else must approve build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/util/intelp2m/platforms/apl/apl_test.go b/util/intelp2m/platforms/apl/apl_test.go new file mode 100644 index 0000000..42d15ba4 --- /dev/null +++ b/util/intelp2m/platforms/apl/apl_test.go @@ -0,0 +1,167 @@ +package apl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/apl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + apollolake := apl.PlatformSpecific{} + test.Suite{ + { /* GPIO_0 - GPIO */ + Pad: test.Pad{ID: "GPIO_0", DW0: 0x44000300, DW1: 0x1003d000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME),", + Long: "_PAD_CFG_STRUCT(GPIO_0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)),", + }, + }, + { /* GPIO_15 - GPIO */ + Pad: test.Pad{ID: "GPIO_15", DW0: 0x44000000, DW1: 0x10001000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPIO_15, 0, DN_20K, DEEP, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPIO_15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K)),", + }, + }, + { /* GPIO_16 - GPIO */ + Pad: test.Pad{ID: "GPIO_16", DW0: 0x44000003, DW1: 0x10003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPIO_16, 1, UP_20K, DEEP, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPIO_16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1) | 1, PAD_PULL(UP_20K)),", + }, + }, + { /* GPIO_18 - GPIO */ + Pad: test.Pad{ID: "GPIO_18", DW0: 0x44000102, DW1: 0x10003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_OWN(GPIO_18, UP_20K, DEEP, OFF, ACPI),", + Long: "_PAD_CFG_STRUCT(GPIO_18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),", + }, + }, + { /* GPIO_21 - GPIO */ + Pad: test.Pad{ID: "GPIO_21", DW0: 0x44000102, DW1: 0x10027000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_21, UP_20K, DEEP, OFF, TxDRxE, ACPI),", + Long: "_PAD_CFG_STRUCT(GPIO_21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE)),", + }, + }, + { /* GPIO_22 - GPIO */ + Pad: test.Pad{ID: "GPIO_22", DW0: 0x44800102, DW1: 0x10024100, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_22, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER),", + Long: "_PAD_CFG_STRUCT(GPIO_22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPIO_25 - GPIO */ + Pad: test.Pad{ID: "GPIO_25", DW0: 0x40880102, DW1: 0x00027100, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_SCI_IOS(GPIO_25, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),", + Long: "_PAD_CFG_STRUCT(GPIO_25, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { /* GPIO_26 - SATA_LEDN */ + Pad: test.Pad{ID: "GPIO_26", DW0: 0x44001400, DW1: 0x00003c00, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPIO_26, NATIVE, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPIO_26, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(NATIVE) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPIO_27 - GPIO */ + Pad: test.Pad{ID: "GPIO_27", DW0: 0x42880102, DW1: 0x00024100, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_SCI_IOS(GPIO_27, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD),", + Long: "_PAD_CFG_STRUCT(GPIO_27, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { /* TDI - JTAG_TDI */ + Pad: test.Pad{ID: "TDI", DW0: 0x44000700, DW1: 0x00c00000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(TDI, NONE, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(TDI, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0),", + }, + }, + { /* CNV_BRI_DT - GPIO */ + Pad: test.Pad{ID: "CNV_BRI_DT", DW0: 0x44000100, DW1: 0x1003d000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, ACPI),", + Long: "_PAD_CFG_STRUCT(CNV_BRI_DT, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K) | PAD_IOSSTATE(IGNORE)),", + }, + }, + { /* CNV_BRI_RSP - GPIO */ + Pad: test.Pad{ID: "CNV_BRI_RSP", DW0: 0x44000201, DW1: 0x10003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_20K, DEEP),", + Long: "_PAD_CFG_STRUCT(CNV_BRI_RSP, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(UP_20K)),", + }, + }, + { /* GPIO_188 - DDI0_DDC_SCL */ + Pad: test.Pad{ID: "GPIO_188", DW0: 0x44000400, DW1: 0x0003fc00, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_188, NATIVE, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPIO_188, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)),", + }, + }, + { /* GPIO_172 - SDCARD_CLK */ + Pad: test.Pad{ID: "GPIO_172", DW0: 0x44000400, DW1: 0x00021100, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD),", + Long: "_PAD_CFG_STRUCT(GPIO_172, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { /* GPIO_176 - SDCARD_D3 */ + Pad: test.Pad{ID: "GPIO_176", DW0: 0x44000400, DW1: 0x00021000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_IOSSTATE(GPIO_176, DN_20K, DEEP, NF1, HIZCRx1),", + Long: "_PAD_CFG_STRUCT(GPIO_176, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx1)),", + }, + }, + { /* GPIO_177 - GPIO */ + Pad: test.Pad{ID: "GPIO_177", DW0: 0x46000102, DW1: 0x10027000, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, UP_20K, DEEP, EDGE_BOTH, TxDRxE, DRIVER),", + Long: "_PAD_CFG_STRUCT(GPIO_177, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { /* GPIO_186 - SDCARD_LVL_WP */ + Pad: test.Pad{ID: "GPIO_186", DW0: 0x44000402, DW1: 0x00003000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPIO_186, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),", + }, + }, + { /* GPIO_182 - EMMC_RCLK */ + Pad: test.Pad{ID: "GPIO_182", DW0: 0x44000400, DW1: 0x0001d000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0),", + Long: "_PAD_CFG_STRUCT(GPIO_182, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(DN_20K) | PAD_IOSSTATE(HIZCRx0)),", + }, + }, + { /* LPC_CLKOUT0 - LPC_CLKOUT0 */ + Pad: test.Pad{ID: "LPC_CLKOUT0", DW0: 0x44000400, DW1: 0x00020100, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD),", + Long: "_PAD_CFG_STRUCT(LPC_CLKOUT0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-APOLLO-PCH/PAD-MAP", apollolake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_1xx", DW0: 0xBFFFFFFF, DW1: 0xFFFFFFFF, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_IOSSTATE_IOSTERM(GPP_1xx, NATIVE, PLTRST, NF7, IGNORE, ENPU),", + Long: "_PAD_CFG_STRUCT(GPP_1xx, PAD_FUNC(NF7) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + }.Run(t, "INTEL-APOLLO-PCH/MASK", apollolake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_2xx", DW0: 0x00000000, DW1: 0x00000000, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_GPIO_BIDIRECT(GPP_2xx, 0, NONE, PWROK, LEVEL, ACPI),", + Long: "_PAD_CFG_STRUCT(GPP_2xx, PAD_FUNC(GPIO), 0),", + }, + }, + }.Run(t, "INTEL-APOLLO-PCH/EMRTY", apollolake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/67134?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c47edb31d24930068486c74147c5fbc9b18b4b6 Gerrit-Change-Number: 67134 Gerrit-PatchSet: 22 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/intelp2m/parser/template: Add unit test
by David Hendricks (Code Review) 04 Dec '24

04 Dec '24

David Hendricks has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67135?usp=email ) ( 18 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: util/intelp2m/parser/template: Add unit test ...................................................................... util/intelp2m/parser/template: Add unit test Change-Id: I1612a7d18bf53479cbe53ca0ba761b67e795c16b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67135 Reviewed-by: Alicja Michalska <ahplka19(a)gmail.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/intelp2m/parser/parser.go M util/intelp2m/parser/template.go A util/intelp2m/parser/template_test.go 3 files changed, 43 insertions(+), 3 deletions(-) Approvals: Alicja Michalska: Looks good to me, but someone else must approve David Hendricks: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index fd3191d..f6ed047 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -117,7 +117,7 @@ var function, id string var dw0, dw1 uint32 var template = map[int]template{ - config.TempInteltool: useInteltoolLogTemplate, + config.TempInteltool: UseInteltoolLogTemplate, config.TempGpioh : useGpioHTemplate, config.TempSpec : useYourTemplate, } diff --git a/util/intelp2m/parser/template.go b/util/intelp2m/parser/template.go index 3248152..fc67e73 100644 --- a/util/intelp2m/parser/template.go +++ b/util/intelp2m/parser/template.go @@ -6,6 +6,8 @@ "unicode" ) +const INTSEL_MASK uint32 = 0xffffff00 + type template func(string, *string, *string, *uint32, *uint32) int // extractPadFuncFromComment @@ -38,7 +40,7 @@ // *dw1 : DW1 register value // return // error status -func useInteltoolLogTemplate(line string, function *string, +func UseInteltoolLogTemplate(line string, function *string, id *string, dw0 *uint32, dw1 *uint32) int { var val uint64 @@ -57,7 +59,7 @@ *function += "/" + fields[i] } // clear RO Interrupt Select (INTSEL) - *dw1 &= 0xffffff00 + *dw1 &= INTSEL_MASK } return 0 } diff --git a/util/intelp2m/parser/template_test.go b/util/intelp2m/parser/template_test.go new file mode 100644 index 0000000..98ccb3f --- /dev/null +++ b/util/intelp2m/parser/template_test.go @@ -0,0 +1,38 @@ +package parser_test + +import ( + "fmt" + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/parser" +) + +func TestTemp(t *testing.T) { + t.Run("TEMPLATE/INTELTOOL-LINE", func(t *testing.T) { + const ( + ref_fn string = "SLP_S0#" + ref_id string = "GPP_B12" + ref_dw0 uint32 = 0x44000600 + ref_dw1 uint32 = 0x0000003c + ) + var ( + fn, id string + dw0, dw1 uint32 + ) + line := fmt.Sprintf("0x0520: 0x%08x%08x %s %s", ref_dw1, ref_dw0, ref_id, ref_fn) + _ = parser.UseInteltoolLogTemplate(line, &fn, &id, &dw0, &dw1) + if fn != ref_fn { + t.Errorf("function from '%s':\nExpects: '%s'\nActually: '%s'\n\n", + line, ref_fn, fn) + } else if id != ref_id { + t.Errorf("id from '%s':\nExpects: '%s'\nActually: '%s'\n\n", + line, ref_id, id) + } else if dw0 != ref_dw0 { + t.Errorf("dw0 from '%s':\nExpects: '0x%08x'\nActually: '0x%08x'\n\n", + line, ref_dw0, dw0) + } else if dw1 != (ref_dw1 & parser.INTSEL_MASK) { + t.Errorf("dw1 from '%s':\nExpects: '0x%08x'\nActually: '0x%08x'\n\n", + line, (ref_dw1 & parser.INTSEL_MASK), dw1) + } + }) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/67135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1612a7d18bf53479cbe53ca0ba761b67e795c16b Gerrit-Change-Number: 67135 Gerrit-PatchSet: 20 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: drivers/ipmi/ocp: Add missing include
by Elyes Haouas (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Patrick Rudolph. Elyes Haouas has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85317?usp=email ) Change subject: drivers/ipmi/ocp: Add missing include ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccd131295263460a4939e51e12ece87ea22c417c Gerrit-Change-Number: 85317 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 17:44:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls
by Martin Roth (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk, Matt DeVillier, Nick Kochlowski, Paul Menzel. Martin Roth has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/84915?usp=email ) Change subject: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/84915/comment/4577a1c1_05d4c7d6?us… : PS7, Line 103: PLATFORM_USES_OPENSIL > do we want this declared at the SoC level? […] Yeah, I think that seems reasonable. For the FSP it's in drivers/intel/[FSP1_1/FSP2_0]/Kconfig, but we don't have a driver for opensil at this point. Maybe we should create drivers/amd/opensil and put it there? -- To view, visit https://review.coreboot.org/c/coreboot/+/84915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Gerrit-Change-Number: 84915 Gerrit-PatchSet: 7 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Wed, 04 Dec 2024 17:38:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com>

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