coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Disable FP_MCU based on fw_config
by YH Lin (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Subrata Banik, Tarun, Tyler Wang. YH Lin has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85365?usp=email ) Change subject: mb/google/rex/var/kanix: Disable FP_MCU based on fw_config ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I087f082c051bc3a97f2514dd121b279e27738022 Gerrit-Change-Number: 85365 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 05 Dec 2024 01:23:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Name of user not set (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Felix Singer, Paul Menzel. Name of user not set #1004406 has posted comments on this change by Name of user not set #1004406. ( https://review.coreboot.org/c/coreboot/+/65225?usp=email ) Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: should i fix the suspend and m.2 sata issue here? or is it okay to create two new tickets for that, after this is merged? -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 19 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 05 Dec 2024 01:19:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Name of user not set (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Felix Singer, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65225?usp=email to look at the new patch set (#19). Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) I tested my code on a Intel i3-9100F under Ubuntu 24.04 and Windows 10 with SeaBIOS. the following things are working flawlessly: * all PCIe slots * all USB ports * VGA init in SeaBIOS (discrete nvida gpu) * onboard sound * both Ethernet ports * all SATA ports (besides m.2) * WLAN card: + WiFi works + Bluetooth works what was not tested: * front audio jacks whats not working: * suspend to ram, it won't poweroff correctly * edk2 with Windows 10+ * m.2 sata port/pcie is working romstage changes: * corrects resistor cfg (see 573387) * removes unused dq/dqs mappings * adds default config for Asrock H370M-ITX * uses devicetree pci aliases * removes unncesseray keys in devicetree.cb * rename Makefile.inc to Makefile.mk * load gpio config after FSP-S init * move gpio_table to C file * cleanup gpio.c Change-Id: I79302247311471153ebbba991081365d9265791b Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- A configs/config.asrock_h370m_itx A src/mainboard/asrock/h370m/Kconfig A src/mainboard/asrock/h370m/Kconfig.name A src/mainboard/asrock/h370m/Makefile.mk A src/mainboard/asrock/h370m/board_info.txt A src/mainboard/asrock/h370m/bootblock.c A src/mainboard/asrock/h370m/cmos.default A src/mainboard/asrock/h370m/cmos.layout A src/mainboard/asrock/h370m/devicetree.cb A src/mainboard/asrock/h370m/dsdt.asl A src/mainboard/asrock/h370m/gpio.c A src/mainboard/asrock/h370m/include/gpio.h A src/mainboard/asrock/h370m/ramstage.c A src/mainboard/asrock/h370m/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/65225/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 19 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Name of user not set (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Felix Singer, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65225?usp=email to look at the new patch set (#18). Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) I tested my code on a Intel i3-9100F under Ubuntu 24.04 and Windows 10 with SeaBIOS. the following things are working flawlessly: * all PCIe slots * all USB ports * VGA init in SeaBIOS (discrete nvida gpu) * WiFi and onboard sound * both Ethernet ports * all SATA ports (besides m.2) * WLAN card: + WiFi works + Bluetooth works what was not tested: * front audio jacks whats not working: * suspend to ram, it won't poweroff correctly * edk2 with Windows 10+ * m.2 sata port/pcie is working romstage changes: * corrects resistor cfg (see 573387) * removes unused dq/dqs mappings * adds default config for Asrock H370M-ITX * uses devicetree pci aliases * removes unncesseray keys in devicetree.cb * rename Makefile.inc to Makefile.mk * load gpio config after FSP-S init * move gpio_table to C file * cleanup gpio.c Change-Id: I79302247311471153ebbba991081365d9265791b Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- A configs/config.asrock_h370m_itx A src/mainboard/asrock/h370m/Kconfig A src/mainboard/asrock/h370m/Kconfig.name A src/mainboard/asrock/h370m/Makefile.mk A src/mainboard/asrock/h370m/board_info.txt A src/mainboard/asrock/h370m/bootblock.c A src/mainboard/asrock/h370m/cmos.default A src/mainboard/asrock/h370m/cmos.layout A src/mainboard/asrock/h370m/devicetree.cb A src/mainboard/asrock/h370m/dsdt.asl A src/mainboard/asrock/h370m/gpio.c A src/mainboard/asrock/h370m/include/gpio.h A src/mainboard/asrock/h370m/ramstage.c A src/mainboard/asrock/h370m/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/65225/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 18 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Name of user not set (Code Review) 05 Dec '24

05 Dec '24

Attention is currently required from: Felix Singer, Paul Menzel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/65225?usp=email to look at the new patch set (#17). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) I tested my code on a Intel i3-9100F under Ubuntu 24.04 and Windows 10 with SeaBIOS. the following things are working flawlessly: * all PCIe slots * all USB ports * VGA init in SeaBIOS (discrete nvida gpu) * WiFi and onboard sound * both Ethernet ports * all SATA ports (besides m.2) what was not tested: * front audio jacks whats not working: * suspend to ram, it won't poweroff correctly * edk2 with Windows 10+ * m.2 sata port/pcie is working romstage changes: * corrects resistor cfg (see 573387) * removes unused dq/dqs mappings * adds default config for Asrock H370M-ITX * uses devicetree pci aliases * removes unncesseray keys in devicetree.cb * rename Makefile.inc to Makefile.mk * load gpio config after FSP-S init * move gpio_table to C file * cleanup gpio.c Change-Id: I79302247311471153ebbba991081365d9265791b Signed-off-by: Max Fritz <antischmock(a)googlemail.com> --- A configs/config.asrock_h370m_itx A src/mainboard/asrock/h370m/Kconfig A src/mainboard/asrock/h370m/Kconfig.name A src/mainboard/asrock/h370m/Makefile.mk A src/mainboard/asrock/h370m/board_info.txt A src/mainboard/asrock/h370m/bootblock.c A src/mainboard/asrock/h370m/cmos.default A src/mainboard/asrock/h370m/cmos.layout A src/mainboard/asrock/h370m/devicetree.cb A src/mainboard/asrock/h370m/dsdt.asl A src/mainboard/asrock/h370m/gpio.c A src/mainboard/asrock/h370m/include/gpio.h A src/mainboard/asrock/h370m/ramstage.c A src/mainboard/asrock/h370m/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/65225/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 17 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: cbfstool: Add hash to more than one region
by Julius Werner (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Bao Zheng, Zheng Bao. Julius Werner has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/85468?usp=email ) Change subject: cbfstool: Add hash to more than one region ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can you explain what you're trying to do here? What is `COREBOOTB`? -- To view, visit https://review.coreboot.org/c/coreboot/+/85468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9a5baa2699468380b942b3bdc104cab78adf5f Gerrit-Change-Number: 85468 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Wed, 04 Dec 2024 22:32:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: libpayload: configs: Add new config.featuretest to broaden CI
by Julius Werner (Code Review) 04 Dec '24

04 Dec '24

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81362?usp=email ) Change subject: libpayload: configs: Add new config.featuretest to broaden CI ...................................................................... libpayload: configs: Add new config.featuretest to broaden CI This patch adds a new config to libpayload whose sole purpose it is to be as different as possible from the defconfig, in order to try to get the CI to exercise more code paths and thus catch more issues. Change-Id: Ia6bd7572056b7a02acb686542810e661e015cc69 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81362 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A payloads/libpayload/configs/config.featuretest 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/payloads/libpayload/configs/config.featuretest b/payloads/libpayload/configs/config.featuretest new file mode 100644 index 0000000..7044d59 --- /dev/null +++ b/payloads/libpayload/configs/config.featuretest @@ -0,0 +1,32 @@ +# The goal of this config is to be as different as possible from the defaults, +# to exercise more code paths in the CI. + +CONFIG_LP_GPL=y +CONFIG_LP_DEVELOPER=y +CONFIG_LP_LTO=y +CONFIG_LP_REMOTEGDB=y +CONFIG_LP_MEMMAP_RAM_ONLY=y +CONFIG_LP_MULTIBOOT=y +CONFIG_LP_TINYCURSES=y +# CONFIG_LP_LZMA is not set +# CONFIG_LP_LZ4 is not set +CONFIG_LP_SKIP_CONSOLE_INIT=y +# CONFIG_LP_CBMEM_CONSOLE is not set +# CONFIG_LP_SERIAL_CONSOLE is not set +# CONFIG_LP_VGA_VIDEO_CONSOLE is not set +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +CONFIG_LP_COREBOOT_VIDEO_CENTERED=y +CONFIG_LP_CBGFX_FAST_RESAMPLE=y +# CONFIG_LP_PC_I8042 is not set +# CONFIG_LP_PC_MOUSE is not set +# CONFIG_LP_PC_KEYBOARD is not set +# CONFIG_LP_PCI is not set +# CONFIG_LP_NVRAM is not set +CONFIG_LP_RTC_PORT_EXTENDED_VIA=y +# CONFIG_LP_SPEAKER is not set +# CONFIG_LP_STORAGE is not set +# CONFIG_LP_USB is not set +CONFIG_LP_UDC_CI=y +CONFIG_LP_UDC_DWC2=y +CONFIG_LP_DEBUG_MALLOC=y +CONFIG_LP_ENABLE_APIC=y -- To view, visit https://review.coreboot.org/c/coreboot/+/81362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6bd7572056b7a02acb686542810e661e015cc69 Gerrit-Change-Number: 81362 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: commonlib/device_tree: Make END token part of struct_size
by Julius Werner (Code Review) 04 Dec '24

04 Dec '24

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85462?usp=email ) Change subject: commonlib/device_tree: Make END token part of struct_size ...................................................................... commonlib/device_tree: Make END token part of struct_size According to the FDT specification the FDT_END token is supposed to be the last token in the structure block, not a free-floating token immediately outside of it. That means we're supposed to count it in struct_size. It seems that the kernel never cared about this, but some FDT parsing utilities like `fdtgrep` do. Change-Id: Icdeadbeefcafed00dbabefeed1337c0debc86836 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85462 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/device_tree.c 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c index cb7a596..b2daac9 100644 --- a/src/commonlib/device_tree.c +++ b/src/commonlib/device_tree.c @@ -935,12 +935,11 @@ uint8_t *struct_start = dest; header->structure_offset = htobe32(dest - (uint8_t *)start_dest); + be32enc(&dest[struct_size], FDT_TOKEN_END); + struct_size += sizeof(uint32_t); header->structure_size = htobe32(struct_size); dest += struct_size; - *((uint32_t *)dest) = htobe32(FDT_TOKEN_END); - dest += sizeof(uint32_t); - uint8_t *strings_start = dest; header->strings_offset = htobe32(dest - (uint8_t *)start_dest); header->strings_size = htobe32(strings_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/85462?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdeadbeefcafed00dbabefeed1337c0debc86836 Gerrit-Change-Number: 85462 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/amb/birman*: gpio.c
by Felix Held (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Ana Carolina Cabral, Fred Reitberger, Jason Glenesk. Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*: gpio.c ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85498/comment/95a50b92_08935416?us… : PS1, Line 7: mb/amb/birman*: gpio.c maybe: mb/amb/birman*/gpio: use native functions for VDD_MEM_VID[0,1] File src/mainboard/amd/birman/gpio.c: https://review.coreboot.org/c/coreboot/+/85498/comment/b2558859_635cbe8f?us… : PS1, Line 33: PULL_NONE from the schematic, i'd expect this to be PULL_UP. same for the other instances -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Wed, 04 Dec 2024 21:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/amb/birman*: gpio.c
by Ana Carolina Cabral (Code Review) 04 Dec '24

04 Dec '24

Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*: gpio.c ...................................................................... mb/amb/birman*: gpio.c Fix VDD_MEM_VID[0,1] pin assignments that was causing boot issues. Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman/gpio.c M src/mainboard/amd/birman_plus/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85498/1 diff --git a/src/mainboard/amd/birman/gpio.c b/src/mainboard/amd/birman/gpio.c index 74d929d..96d970d 100644 --- a/src/mainboard/amd/birman/gpio.c +++ b/src/mainboard/amd/birman/gpio.c @@ -30,7 +30,7 @@ /* SD_CARD_PRSNT_L */ PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ /* VDD_MEM_VID0 */ - PAD_GPO(GPIO_10, HIGH), + PAD_NF(GPIO_10, DF_VRCONTEXT_0, PULL_NONE), /* HP_MIC_DET_L */ PAD_GPI(GPIO_11, PULL_UP), /* ALIGN_FLAG_MU_L */ @@ -77,7 +77,7 @@ PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), /* GPIO_41: Not available */ /* VDD_MEM_VID1 */ - PAD_GPO(GPIO_42, HIGH), + PAD_NF(GPIO_42, DF_VRCONTEXT_1, PULL_NONE), /* GPIO_43 - GPIO_66: Not available */ /* SPI_ROM_REQ */ PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), diff --git a/src/mainboard/amd/birman_plus/gpio.c b/src/mainboard/amd/birman_plus/gpio.c index 74d929d..96d970d 100644 --- a/src/mainboard/amd/birman_plus/gpio.c +++ b/src/mainboard/amd/birman_plus/gpio.c @@ -30,7 +30,7 @@ /* SD_CARD_PRSNT_L */ PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ /* VDD_MEM_VID0 */ - PAD_GPO(GPIO_10, HIGH), + PAD_NF(GPIO_10, DF_VRCONTEXT_0, PULL_NONE), /* HP_MIC_DET_L */ PAD_GPI(GPIO_11, PULL_UP), /* ALIGN_FLAG_MU_L */ @@ -77,7 +77,7 @@ PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), /* GPIO_41: Not available */ /* VDD_MEM_VID1 */ - PAD_GPO(GPIO_42, HIGH), + PAD_NF(GPIO_42, DF_VRCONTEXT_1, PULL_NONE), /* GPIO_43 - GPIO_66: Not available */ /* SPI_ROM_REQ */ PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 1 Gerrit-Owner: Ana Carolina Cabral

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coreboot-gerrit December 2024