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Change subject: soc/mediatek/mt8196: Add booker driver
......................................................................
Patch Set 12:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85362/comment/d4d42f35_0e94c915?us… :
PS12, Line 8:
> Can you please start by describing MediaTek Booker device? Is it newly introduced with MT8196? What […]
The Booker's protocol is generally similar to CI-700, with some MTK modifications. It does not require a blob and is mainly used by MTE (Memory Tagging Extension) and SLC (System Level Cache).
https://review.coreboot.org/c/coreboot/+/85362/comment/ea3db652_fcd3e09b?us… :
PS12, Line 20: [booker_init] AP hash rule: 0xbe00.
> What is this hash rule?
Hash rule is an algorithm that implements different hash functions for a device in MTK.
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Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS4:
> > and then in ramstage again […]
[Done](https://review.coreboot.org/c/coreboot/+/82695/7..8/src/security/vboo…
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Attention is currently required from: Christian Walter, Filip Lewiński, Julius Werner, Yu-Ping Wu.
Hello Christian Walter, Michał Żygowski, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82695?usp=email
to look at the new patch set (#8).
Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
security: Allow vboot when INTEL_TXT enabled
INTEL_TXT mandates usage of TPM_MEASURED_BOOT_INIT_BOOTBLOCK, which
is not compatible with VBOOT. This essentially making VBOOT and
INTEL_TXT mutually exclusive, but they do not have to be.
Do not call tpm_setup in bootblock_main if vboot starts in bootblock,
it would only start the TPM slightly faster. Most platforms probably
start vboot in bootblock, so there will be no loss of tpm_setup
state.
If vboot does not start in bootblock and
TPM_MEASURED_BOOT_INIT_BOOTBLOCK is enabled, skip the tpm_setup and
simply initialize the TLCL library.
TEST=Run VP4670 with INTEL_TXT and VBOOT enabled.
Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/lib/bootblock.c
M src/security/tpm/Kconfig
M src/security/vboot/tpm_common.c
3 files changed, 23 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82695/8
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Change subject: cpu/x86/mp_init: Add code to restart APs
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82696/comment/a06ca4f0_ba24b3d5?us… :
PS7, Line 14: Intle
> Intel
Done
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Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
security: Allow vboot when INTEL_TXT enabled
INTEL_TXT mandates usage of TPM_MEASURED_BOOT_INIT_BOOTBLOCK, which
is not compatible with VBOOT. This essentially making VBOOT and
INTEL_TXT mutually exclusive, but they do not have to be.
Do not call tpm_setup in bootblock_main if vboot starts in bootblock,
it would only start the TPM slightly faster. Most platforms probably
start vboot in bootblock, so there will be no loss of tpm_setup
state.
If vboot does not start in bootblock and
TPM_MEASURED_BOOT_INIT_BOOTBLOCK is enabled, skip the tpm_setup and
simply initialize the TLCL library.
TEST=Run VP4670 with INTEL_TXT and VBOOT enabled.
Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/lib/bootblock.c
M src/security/tpm/Kconfig
M src/security/vboot/tpm_common.c
3 files changed, 19 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82695/7
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 7: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85170/comment/2e943eba_497e99e7?us… :
PS7, Line 10: all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs,
> `'excat' may be misspelled - perhaps 'exact'?`
Please fix.
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/af2b5c44_facdbfb3?us… :
PS7, Line 42: /* Assign socket specific GSI_BASE */
: if (dn.socket == 0) {
: gsi_base = 24 + dn.stack * 8;
: } else {
: gsi_base = 72 + dn.stack * 8;
: }
Out of curiosity, is there any reason for the magic numbers 24 and 72? AIUI this wouldn't work properly for more than 2 sockets, how about:
```suggestion
/* Assign socket specific GSI_BASE */
const u32 gsi_base = 24 + dn.socket * 48 + dn.stack * 8;
```
Note that this seems to assume `dn.stack < 6` (which may be guaranteed by how many stacks a socket can have).
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Change subject: cpu/x86/mp_init: Add code to restart APs
......................................................................
cpu/x86/mp_init: Add code to restart APs
When INTEL_TXT is enabled, the APs are stopped before a SCHECK call
to ACM is invoked. However, SCHECK happens before the final MTRRs
are programmed on APs. This results in MTRR programming failure on
APs on platforms using INTEL_TXT.
Add API to restart the APs that can be used by Intel TXT driver.
TEST=Run coreboot with INTEL_TXT enabled on Protectli VP4670 and
see coreboot no longer complains on inability to run a MTRR
programming task on APs.
Change-Id: Ief2a7629d3075de29b363d05330e3a76cef48971
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/cpu/x86/mp_init.c
M src/include/cpu/x86/mp.h
2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/82696/8
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Change subject: soc/intel/xeon_sp: Fix debug print
......................................................................
Patch Set 4: Code-Review+2
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Change subject: soc/intel/xeon_sp/skx: Fix CPU init
......................................................................
Patch Set 4: Code-Review+1
(3 comments)
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/85289/comment/7bc3f02f_a807fdd8?us… :
PS4, Line 321: CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) ||
: CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) ||
: CONFIG(SOC_INTEL_BROADWELL) || CONFIG(SOC_INTEL_SKYLAKE_SP)
For another patch: introduce a Kconfig for this
File src/soc/intel/xeon_sp/skx/cpu.c:
https://review.coreboot.org/c/coreboot/+/85289/comment/fb46f7cb_c5ecb4b5?us… :
PS4, Line 123: msr.hi |= BIT20;
Do we know what this does?
https://review.coreboot.org/c/coreboot/+/85289/comment/fc4a96b1_931051ad?us… :
PS4, Line 153: /* Enable Fast Strings */
That's a bit redundant given the macro name, but if this is to bring CPU code closer between Xeon-SP generations I don't mind (can be removed later).
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