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Change subject: soc/intel/xeon_sp/cpx: Fix register lock
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/85439/comment/6bef7815_f3da01c6?us… :
PS2, Line 118: /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
Comment is no longer true
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Change subject: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
File src/mainboard/ocp/tiogapass/romstage.c:
https://review.coreboot.org/c/coreboot/+/85318/comment/152cfc3a_c8de3c2e?us… :
PS6, Line 75: if (dimm >= 2)
Does this board have 1 or 2 DIMMs per channel?
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Change subject: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
......................................................................
Patch Set 6: Code-Review+2
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Change subject: arch/x86: Enable support for IOAPIC devices
......................................................................
Patch Set 4:
(2 comments)
File src/acpi/acpi_apic.c:
https://review.coreboot.org/c/coreboot/+/85226/comment/4bd94b7e_53416e37?us… :
PS2, Line 244: assert(!CONFIG(ACPI_COMMON_MADT_IOAPIC) || dev->path.ioapic.gsi_base != 0);
> Should we have a comment here to indicate the IOAPIC gsi0 don't need to have a devicetree object? Or […]
Done
File src/arch/x86/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85226/comment/d2f08ccd_ba25982b?us… :
PS1, Line 190: struct device dummy;
> What about using `struct device_path path = {0};` instead ?
Done
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Change subject: arch/x86: Enable support for IOAPIC devices
......................................................................
arch/x86: Enable support for IOAPIC devices
On platforms with multiple IOAPICs the GSI base must not be
linear, which is currently assumed by acpi_create_madt_ioapic_from_hw().
Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow
to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices
into the MADT table if any.
For now, since no platform adds IOAPIC devices, the existing behaviour
remains the same. Allows to get rid of soc_get_ioapic_info().
Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/acpi/acpi_apic.c
M src/arch/x86/include/arch/ioapic.h
M src/arch/x86/ioapic.c
M src/device/device_const.c
M src/include/device/path.h
5 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85226/4
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Change subject: soc/intel/xeon_sp: Fix debug print
......................................................................
soc/intel/xeon_sp: Fix debug print
Fix debug prints that use non-thread safe dev_path(). Since the code
is part of MPinit, it's using multiple threads and one threads modifies
the only buffer used, resulting in path being printed that do not belong
to the current thread.
Drop the call since printing the APIC ID is sufficient and thread safe.
Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/cpx/cpu.c
M src/soc/intel/xeon_sp/skx/cpu.c
2 files changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/85288/4
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 6:
(3 comments)
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/b08fff2c_aacc10e8?us… :
PS4, Line 47: }
> Is there special reason that in SKX, the linear GSI assignment is not usable? I guess is to match th […]
It cannot be assigned, can it?
But yes, it would match what is advertised using _PRT.
https://review.coreboot.org/c/coreboot/+/85170/comment/2ea1d136_55d823d7?us… :
PS4, Line 49: i
> So, do we need to rebase this patch on https://review.coreboot. […]
Done
https://review.coreboot.org/c/coreboot/+/85170/comment/2944eca0_4083f359?us… :
PS4, Line 61: .enable_resources = pci_dev_enable_resources,
> Are 0x2036/0x2026 PCI root port devices?
0x2036 and 0x2026 are the IOAPIC PCI IDs.
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Attention is currently required from: Christian Walter, Filip Lewiński, Julius Werner, Yu-Ping Wu.
Hello Christian Walter, Michał Żygowski, Yu-Ping Wu, build bot (Jenkins),
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Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
security: Allow vboot when INTEL_TXT enabled
INTEL_TXT mandates usage of TPM_MEASURED_BOOT_INIT_BOOTBLOCK, which
is not compatible with VBOOT. This essentially making VBOOT and
INTEL_TXT mutually exclusive, but they do not have to be.
Do not call tpm_setup in bootblock_main if vboot starts in bootblock,
it would only start the TPM slightly faster. Most platforms probably
start vboot in bootblock, so there will be no loss of tpm_setup
state.
If vboot does not start in bootblock and
TPM_MEASURED_BOOT_INIT_BOOTBLOCK is enabled, skip the tpm_setup and
simply initialize the TLCL library.
TEST=Run VP4670 with INTEL_TXT and VBOOT enabled.
Change-Id: I19dc3d910c23fcfd8732465c488f47dd86a96781
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
---
M src/lib/bootblock.c
M src/security/tpm/Kconfig
M src/security/vboot/tpm_common.c
3 files changed, 23 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/82695/6
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