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[XS] Change in coreboot[main]: mb/intel/mtlrvp: Update Soundwire codec address based on devicetree
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Varun Upadhyay has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85472?usp=email ) Change subject: mb/intel/mtlrvp: Update Soundwire codec address based on devicetree ...................................................................... mb/intel/mtlrvp: Update Soundwire codec address based on devicetree This change adds soundwire codec addresses in the devicetree to calculate addresses for the ACPI table instead of previous kconfig which allows single board to select multiple soundwire codecs at runtime based on FW_CONFIG. TEST=build coreboot image and boot on intel mtlrvp. Disassemble SSDT and confirm ACPI entries are correct for alc711 device. Change-Id: I17ae29bf14f30cfa135347e7b95977ed9d2c52f3 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85472/1 diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 84ebade..dfe5e44 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -13,7 +13,7 @@ select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_SOUNDWIRE_ALC5682 - select DRIVERS_SOUNDWIRE_ALC711 + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_USB_ACPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 9ba7118..3b17bce 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -604,6 +604,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on probe AUDIO MTL_ALC711_SNDW end -- To view, visit https://review.coreboot.org/c/coreboot/+/85472?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I17ae29bf14f30cfa135347e7b95977ed9d2c52f3 Gerrit-Change-Number: 85472 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[S] Change in coreboot[main]: mb/intel/adlrvp: Update Soundwire codec address based on devicetree
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Varun Upadhyay has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85471?usp=email ) Change subject: mb/intel/adlrvp: Update Soundwire codec address based on devicetree ...................................................................... mb/intel/adlrvp: Update Soundwire codec address based on devicetree This change adds soundwire codec addresses in the devicetree to calculate addresses for the ACPI table instead of previous kconfig. TEST=build coreboot image and boot on intel adlrvp. Disassemble SSDT and confirm ACPI entries are correct for alc711 device. Change-Id: Iddb85037f710afc417383a36854e91b3ae7eae4f Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb 4 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85471/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 0171ebc..279a8f9 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -10,7 +10,7 @@ select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_SOUNDWIRE - select DRIVERS_SOUNDWIRE_ALC711 + select DRIVERS_SOUNDWIRE_ALC_BASE_7XX select DRIVERS_SPI_ACPI select DRIVERS_USB_ACPI select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a6bad13..a3b3c93 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -456,6 +456,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on end end end diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 922b673..9ddc651 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -393,6 +393,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721" device generic 0.1 on end end end diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index db859a1..7e66656 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -390,6 +390,9 @@ chip drivers/soundwire/alc711 # SoundWire Link 0 ID 1 register "desc" = ""Headset Codec"" + register "alc711_address.version" = "SOUNDWIRE_VERSION_1_1" + register "alc711_address.class" = "MIPI_CLASS_NONE" + register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC711" device generic 0.1 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85471?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iddb85037f710afc417383a36854e91b3ae7eae4f Gerrit-Change-Number: 85471 Gerrit-PatchSet: 1 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[S] Change in coreboot[main]: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Naveen M, Paul Menzel, Pranava Y N, Varun Upadhyay. Hello Karthik Ramasubramanian, Naveen M, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85282?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs ...................................................................... drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs - Use common config DRIVERS_SOUNDWIRE_ALC_BASE_7XX for ALC7xx variants - Introduce soundwire codec address in soundwire chip.h to calculate device address for acpi table based on overridetree. BUG=b:368495490 TEST=build coreboot image and boot on Intel RVP board. Disassemble SSDT and confirm ACPI entries are correct for alc7xx device. Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> Signed-off-by: Naveen M <naveen.m(a)intel.com> --- M src/drivers/soundwire/alc711/alc711.c M src/drivers/soundwire/alc711/chip.h 2 files changed, 8 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/85282/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Gerrit-Change-Number: 85282 Gerrit-PatchSet: 9 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Update Soundwire codec address based on devicetree
by Varun Upadhyay (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Naveen M, Paul Menzel, Pranava Y N, Subrata Banik. Hello Karthik Ramasubramanian, Naveen M, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85440?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Update Soundwire codec address based on devicetree ...................................................................... mb/google/fatcat: Update Soundwire codec address based on devicetree This change adds soundwire codec addresses in the devicetree to calculate addresses for the ACPI table instead of previous kconfig which allows single board to select multiple soundwire codecs at runtime based on FW_CONFIG. BUG=b:368495490 TEST=build coreboot image and boot on google fatcat. Disassemble SSDT and confirm ACPI entries are correct for alc7xx device. Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> Signed-off-by: Naveen M <naveen.m(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85440/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85440?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3322ae2d106d3628dbf627aacf999056d82ee7a9 Gerrit-Change-Number: 85440 Gerrit-PatchSet: 5 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/google/nissa: Create pujjogatwin variant
by Eric Lai (Code Review) 04 Dec '24

04 Dec '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85329?usp=email ) Change subject: mb/google/nissa: Create pujjogatwin variant ...................................................................... mb/google/nissa: Create pujjogatwin variant Create the pujjogatwin variant of nissa reference board by copying the pujjoga files to a new directory named for the variant. The difference between pujjoga and pujjogatwin is that pujjogatwin use Twin Lake CPU and firmware config, so copying the pujjoga setting files to create new variant. BUG=b:381152086 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PUJJOGATWIN Change-Id: I345ce463699840b10016555bb104a16968e7a8c1 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Signed-off-by: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85329 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk M src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/pujjoga/overridetree_pujjogatwin.cb 6 files changed, 502 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 6f9f5b5..8f5c8dc 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -442,6 +442,15 @@ select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select HAVE_WWAN_POWER_SEQUENCE +config BOARD_GOOGLE_PUJJOGATWIN + select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select HAVE_WWAN_POWER_SEQUENCE + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -763,6 +772,7 @@ default 0x0 if BOARD_GOOGLE_YAVILLA default 0x1 if BOARD_GOOGLE_ZYDRON default 0x0 if BOARD_GOOGLE_TELITH + default 0x0 if BOARD_GOOGLE_PUJJOGATWIN config DRIVER_TPM_I2C_ADDR hex @@ -839,8 +849,10 @@ default 13 if BOARD_GOOGLE_YAVILLA default 13 if BOARD_GOOGLE_ZYDRON default 13 if BOARD_GOOGLE_TELITH + default 13 if BOARD_GOOGLE_PUJJOGATWIN config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree_pujjogatwin.cb" if BOARD_GOOGLE_PUJJOGATWIN default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_DIR @@ -923,6 +935,7 @@ default "Zydron" if BOARD_GOOGLE_ZYDRON default "Pujjoga" if BOARD_GOOGLE_PUJJOGA default "Telith" if BOARD_GOOGLE_TELITH + default "Pujjogatwin" if BOARD_GOOGLE_PUJJOGATWIN config VARIANT_DIR default "agah" if BOARD_GOOGLE_AGAH @@ -993,6 +1006,7 @@ default "yavista" if BOARD_GOOGLE_YAVISTA default "pujjoga" if BOARD_GOOGLE_PUJJOGA default "telith" if BOARD_GOOGLE_TELITH + default "pujjoga" if BOARD_GOOGLE_PUJJOGATWIN config VBOOT select VBOOT_EARLY_EC_SYNC if !(BOARD_GOOGLE_BASEBOARD_NISSA || BOARD_GOOGLE_BASEBOARD_TRULO) diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 9bc68bb..eb0b006 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -200,6 +200,9 @@ config BOARD_GOOGLE_PUJJOGA bool "-> Pujjoga" +config BOARD_GOOGLE_PUJJOGATWIN + bool "-> Pujjogatwin" + config BOARD_GOOGLE_ORISA bool "-> Orisa" diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk index c6e0a1c..54cd4b0 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk @@ -7,3 +7,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 3(0b0011) Parts = H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt index adec69c..40724af 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt @@ -9,3 +9,4 @@ K3KL6L60GM-MGCT 2 (0010) K3KL8L80CM-MGCT 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) +H58G56CK8BX146 3 (0011) diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt index b962c72..98df9d2 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt @@ -14,3 +14,4 @@ K3KL6L60GM-MGCT K3KL8L80CM-MGCT MT62F1G32D2DS-026 WT:B +H58G56CK8BX146 diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree_pujjogatwin.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree_pujjogatwin.cb new file mode 100644 index 0000000..a10ae5f --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/overridetree_pujjogatwin.cb @@ -0,0 +1,482 @@ +fw_config + field WWAN 3 4 + option WWAN_ABSENT 0 + option LTE_PRESENT 1 + option 5G_PRESENT 2 + end + field WIFI_SAR_ID 18 21 + option WIFI_SAR_TABLE_AX211 0 + option WIFI_SAR_TABLE_AX203 1 + end +end + +chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "100" + + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN + + # Configure external V1P05/Vnn/VnnSx Rails for Pujjoga + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""DDR"" + register "options.tsr[2].desc" = ""5VCharger"" + + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 60000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2000 }, + [2] = { 16, 1500 }, + [3] = { 8, 1000 } + }" + device generic 0 on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "3" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0a" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x19" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x08" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe WWAN LTE_PRESENT + end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pcie_rp7 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on + probe WWAN LTE_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on + probe WWAN LTE_PRESENT + end + end + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85329?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I345ce463699840b10016555bb104a16968e7a8c1 Gerrit-Change-Number: 85329 Gerrit-PatchSet: 19 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lauren Ting <lauren.ting(a)lcfc.corp-partner.google.com> Gerrit-CC: Lucien Kao <lucien.kao(a)lcfc.corp-partner.google.com> Gerrit-CC: Mike Lee <mike.lee(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Yidi Lin (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: @jarried.lin@mediatek.com please fix ``` aarch64-elf-ld.bfd: Bootblock exceeded its allotted size! (75K) make[2]: *** [src/arch/arm64/Makefile.mk:47: /cb-build/coreboot-gerrit.0/clang-chromeos/GOOGLE_HYLIA/cbfs/fallback/bootblock.debug] Error 1 make[2]: Leaving directory '/home/coreboot/node-root/workspace/coreboot-gerrit' ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 07:37:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: .checkpatch.conf: Set max line length to 96
by Yidi Lin (Code Review) 04 Dec '24

04 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85435?usp=email ) Change subject: .checkpatch.conf: Set max line length to 96 ...................................................................... .checkpatch.conf: Set max line length to 96 Linux upstream's checkpatch.pl has a default max line length of 100. Since coreboot uses 96, add --max-line-length=96 to the config file. Change-Id: I7737f3d2e0d016b0f0dd82df2865a6b51b667066 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85435 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M .checkpatch.conf 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/.checkpatch.conf b/.checkpatch.conf index ac261a4..f57474d 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -1,3 +1,6 @@ +# Override checkpatch's default max line length 100 +--max-line-length=96 + # Not Linux, so don't expect a Linux tree. --no-tree -- To view, visit https://review.coreboot.org/c/coreboot/+/85435?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7737f3d2e0d016b0f0dd82df2865a6b51b667066 Gerrit-Change-Number: 85435 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Require DRAM blob to exist
by Yidi Lin (Code Review) 04 Dec '24

04 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85441?usp=email ) Change subject: soc/mediatek/mt8196: Require DRAM blob to exist ...................................................................... soc/mediatek/mt8196: Require DRAM blob to exist The SoC won't be able to boot without dram.elf. Therefore, we should always expect the file to exist in build time. BUG=none TEST=emerge-rauru coreboot BRANCH=none Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85441 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Makefile.mk 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 82a9076..9d00a2e 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -60,9 +60,8 @@ $(DRAM_CBFS)-file := $(MT8196_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage $(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) -ifneq ($(wildcard $($(DRAM_CBFS)-file)),) - cbfs-files-y += $(DRAM_CBFS) -endif +cbfs-files-y += $(DRAM_CBFS) + $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/85441?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib902dc4778f34a144dddf847c283fe77d4c776f6 Gerrit-Change-Number: 85441 Gerrit-PatchSet: 3 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Update blobs submodule to upstream main
by Yidi Lin (Code Review) 04 Dec '24

04 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85444?usp=email ) Change subject: Update blobs submodule to upstream main ...................................................................... Update blobs submodule to upstream main Updating from commit id 45f1b757402f: 2024-08-29 11:51:27 +0200 - (soc/intel/raptorlake: Add microcode for 06-b7-01) to commit id 14f8fcc1b426: 2024-11-28 05:07:49 +0000 - (soc/mediatek/mt8196: Update SSPM firmware to v2.0) This brings in 8 new commits: 14f8fcc1b426 soc/mediatek/mt8196: Update SSPM firmware to v2.0 754f7ad6c808 soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration 612f93620740 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries 3180f6d462a0 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries eb48279e69eb 3rdparty/blobs/mb/google/zork: Update PSP signing token 002ee2ca6e04 soc/mediatek/mt8196: Add MCUPM firmware v1.0 ce5fcc5a745e soc/mediatek/mt8196: Add dpm.pm and dpm.dm version 1.0 ae17d7f52c68 soc/mediatek/mt8196: Add SSPM firmware v1.0 Change-Id: Ia9bf331e4482d7b2a231f4b67552eea80207018e Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85444 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/blobs b/3rdparty/blobs index 45f1b75..14f8fcc 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 45f1b757402f9a0ae8a4e021a8f5745318515308 +Subproject commit 14f8fcc1b426cb0884a21a9b715da6e0c1c7f434 -- To view, visit https://review.coreboot.org/c/coreboot/+/85444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia9bf331e4482d7b2a231f4b67552eea80207018e Gerrit-Change-Number: 85444 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Yidi Lin (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 06:51:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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