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Change subject: amdfwtool: Set address mode as relative table
......................................................................
amdfwtool: Set address mode as relative table
For the family new than Cezanne, the upper 2 bits defines the address
mode. In table header, the address mode of the table is set.
In the old code, if the header defines address mode as relative table,
the entry address mode is not set. That is not correct.
For A/B recovery, the address mode in Level 2 PSP/BIOS table should be
"relative table", including the entry BIOS binary(0x62).
Identidal binary test passes on platforms which are not based on
Cezanne, V2000A, Genoa. Booting test passes on Majolica/Cezanne.
Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 4 insertions(+), 3 deletions(-)
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Change subject: amdfwtool: Add injection corruption to call if necessary
......................................................................
amdfwtool: Add injection corruption to call if necessary
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Change subject: amdfwtool: Address mode is relative table
......................................................................
amdfwtool: Address mode is relative table
The address mode of all L2 table for A/B recovery should be relative
table, otherwise the addresses would be different.
For Cezanne, the L1 should be still relative BIOS or physical. So when
we create level 2 tables, save address mode and restore.
Change-Id: I85db43cde15e5b4b26fe9f38e647b31870ea51ac
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/84535/4
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Change subject: amdfwtool: Move L1 before L2
......................................................................
amdfwtool: Move L1 before L2
It is more reasonable.
Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
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Change subject: amdfwtool: Clean up the code to make it more logical
......................................................................
amdfwtool: Clean up the code to make it more logical
TEST=Identical test on all AMD platform
Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
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Change subject: soc/mediatek/mt8196: Add booker driver
......................................................................
Patch Set 10:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85362/comment/860f9723_305cfd5c?us… :
PS10, Line 10: e(
space
https://review.coreboot.org/c/coreboot/+/85362/comment/a95403a0_40e73c40?us… :
PS10, Line 16: set bit[3]
it is needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of each SBSX node in order to propagate the CMO command.
File src/soc/mediatek/mt8196/booker.c:
https://review.coreboot.org/c/coreboot/+/85362/comment/822b454a_d48bc152?us… :
PS10, Line 11: OFF_REG_POR_SBSX_CFG_CTL
POR_SBSX_CFG_CTL_OFFSET
https://review.coreboot.org/c/coreboot/+/85362/comment/2f47f3a4_f1f2df4b?us… :
PS10, Line 25: 64p
I think it is a 32-bit register ?
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Change subject: mb/google/brox: remove config for ISH UART and GP3.
......................................................................
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Change subject: soc/mediatek/mt8196: Add booker driver
......................................................................
Patch Set 10:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85362/comment/7097422e_64333d43?us… :
PS9, Line 9: The MTK booker
> Okay, This will be modified in the next release.
Done
https://review.coreboot.org/c/coreboot/+/85362/comment/f4b319e2_05a7fcd4?us… :
PS9, Line 15: it can
> Okay, This will be modified in the next release.
Done
https://review.coreboot.org/c/coreboot/+/85362/comment/cfe2f5f6_c55f07d6?us… :
PS9, Line 15: it can
: set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register of
: each SBSX node.
> Yes, the default value of the reg por_sbsx_cfg_ctl is 64'b1111111, we must clear bit3 to 0.
Done
File src/soc/mediatek/mt8196/booker.c:
https://review.coreboot.org/c/coreboot/+/85362/comment/5056964e_0f3b047b?us… :
PS9, Line 11: MCUSYS_PAR_WRAP_BASE
> Okay, This will be modified in the next release.
Done
https://review.coreboot.org/c/coreboot/+/85362/comment/6115391e_9574db0d?us… :
PS9, Line 13: 0x00450000 + 0x0A00
> Okay, This will be modified in the next release.
Done
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Change subject: soc/mediatek/mt8196: Add booker driver
......................................................................
soc/mediatek/mt8196: Add booker driver
The MediaTek booker (the customized ARM CI-700) mainly uses CHI
protocol, but doesn't support coherence(which is achieved through ACP
solution). Additionally, the booker also uses other protocols such as
AXI, which translates CHI transactions into EMI's AXI transactions.
Currently, the mt8196 booker only uses the functions of SLC CMO routing.
If downstream SLC needs CMO command propagation from the DSU, it needs
to set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register
of each SBSX node.
TEST=build pass, check boot log with:
[booker_init] AP hash rule: 0xbe00.
BUG=b:317009620
Signed-off-by: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com>
Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/booker.c
M src/soc/mediatek/mt8196/bootblock.c
A src/soc/mediatek/mt8196/include/soc/booker.h
4 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85362/10
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Change subject: soc/mediatek/mt8196: Add booker driver
......................................................................
Patch Set 9:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85362/comment/d03489fc_c5fb3a7d?us… :
PS9, Line 9: The MTK booker
> The MediaTek booker (the customized ARM CI-700)
Okay, This will be modified in the next release.
https://review.coreboot.org/c/coreboot/+/85362/comment/f60919d6_fb3e5145?us… :
PS9, Line 15: it can
> `it needs to` ?
Okay, This will be modified in the next release.
https://review.coreboot.org/c/coreboot/+/85362/comment/ed564ac5_1f42b926?us… :
PS9, Line 15: it can
: set bit[3] (disable_cmo_prop) to 0 in the por_sbsx_cfg_ctl register of
: each SBSX node.
> Does it mean that we need to set the bit 3 (disable_cmo_prop) to `0` in order to propagate the CMO c […]
Yes, the default value of the reg por_sbsx_cfg_ctl is 64'b1111111, we must clear bit3 to 0.
File src/soc/mediatek/mt8196/booker.c:
https://review.coreboot.org/c/coreboot/+/85362/comment/74188f42_a581767a?us… :
PS9, Line 11: MCUSYS_PAR_WRAP_BASE
> just use `MCUCFG_BASE`
Okay, This will be modified in the next release.
https://review.coreboot.org/c/coreboot/+/85362/comment/e6a52a9d_f481870a?us… :
PS9, Line 13: 0x00450000 + 0x0A00
> please define this
Okay, This will be modified in the next release.
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