coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
by Dtrain Hsu (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85447?usp=email ) Change subject: mb/google/brya/var/uldrenite: Generate RAM ID and SPD file ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8003f693e1d8fa049a0e508078ce29b5bb39f2ef Gerrit-Change-Number: 85447 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Dec 2024 01:50:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
by John Su (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85447?usp=email ) Change subject: mb/google/brya/var/uldrenite: Generate RAM ID and SPD file ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85447/comment/0f7e4a5b_f56b4776?us… : PS1, Line 10: Here is the ram part number list: : DRAM Part Name ID to assign : H9JCNNNBK3MLYR-N6E 0 (0000) : K3KL6L60GM-MGCT 1 (0001) : K3KL8L80CM-MGCT 2 (0010) : MT62F1G32D2DS-026 WT:B 2 (0010) : H58G56CK8BX146 3 (0011) > Copying the file content is not needed. Maybe just mention the models with the vendor. Hi Paul Would it be convenient for me to provide the RAM ID for HW reference, since they usually don't open the content? Thank you -- To view, visit https://review.coreboot.org/c/coreboot/+/85447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8003f693e1d8fa049a0e508078ce29b5bb39f2ef Gerrit-Change-Number: 85447 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 04 Dec 2024 01:41:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Yidi Lin (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85126/comment/fbeac548_63ef09c9?us… : PS12, Line 11: fix low : probability boot failure issue > Which part of this patch fix the issue? I thought this patch simply adds PMIF feature support instea […] I suggest reverting the patch to the patchset 8 and submitting an individual path to address the boot failure issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 01:33:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
by Karthik Ramasubramanian (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Naveen M, Paul Menzel, Pranava Y N, Varun Upadhyay. Karthik Ramasubramanian has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85282?usp=email ) Change subject: drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs ...................................................................... Patch Set 8: (2 comments) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/85282/comment/a3cbf0e1_100f5139?us… : PS7, Line 110: config->alc711_address[dev->path.generic.id].version = SOUNDWIRE_VERSION_1_1; : config->alc711_address[dev->path.generic.id].class = MIPI_CLASS_NONE; : } else { : config->alc711_address[dev->path.generic.id].version = SOUNDWIRE_VERSION_1_2; : config->alc711_address[dev->path.generic.id].class = MIPI_CLASS_SDCA; > > hi Karthik, […] After incorporating the suggestions in https://review.coreboot.org/c/coreboot/+/85282/comment/775ae108_1417b21d/ and updating the adlrvp for ALC711, you can remove this code. That way you dont need any conditional code block in the future for any new SOUNDWIRE_VERSION. File src/drivers/soundwire/alc711/chip.h: https://review.coreboot.org/c/coreboot/+/85282/comment/672b4c84_20dee7ed?us… : PS7, Line 13: [MAX_SNDW_LINKS] > hi Karthik, […] Eventhough a platform can support multiple Soundwire links, only one is going to be enabled at any point in time based on the FW config. So you don't need 4 SNDW_LINKS here. One is good enough. Also the concerned chip driver here is Realtek codec specific and not platform specific. So please do not couple the codec driver with platform. You can update the devicetree as follows: ``` device ref hda on chip drivers/intel/soundwire device generic 0 on chip drivers/soundwire/alc711 register "desc" = ""Headset Codec"" register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" register "alc711_address.class" = "MIPI_CLASS_SDCA" register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC722" # SoundWire Link 1 ID 1 device generic 1.1 on probe AUDIO AUDIO_ALC722_SNDW end end chip drivers/soundwire/alc711 register "desc" = ""Headset Codec"" register "alc711_address.version" = "SOUNDWIRE_VERSION_1_2" register "alc711_address.class" = "MIPI_CLASS_SDCA" register "alc711_address.part_id" = "MIPI_DEV_ID_REALTEK_ALC721" # SoundWire Link 3 ID 1 device generic 3.1 on probe AUDIO AUDIO_ALC721_SNDW end end end end ``` Please `#include <mipi/ids.h>` in this chip.h to include all the required preprocessor definitions eg. MIPI_DEV_ID_REALTEK_ALC721 -- To view, visit https://review.coreboot.org/c/coreboot/+/85282?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5953d0fcb7b15368888901f88c5616757ac42877 Gerrit-Change-Number: 85282 Gerrit-PatchSet: 8 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Naveen M <naveen.m(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 23:06:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: soc/amd/common/psp: add RPMC provisioning code
by Felix Held (Code Review) 03 Dec '24

03 Dec '24

Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84707?usp=email ) Change subject: soc/amd/common/psp: add RPMC provisioning code ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84707/comment/d37c94a4_49c8f8bf?us… : PS7, Line 53: [SPEW ] PSP NVRAM isn't healthy the PSP RPMC NVRAM being reported as not healthy was caused by the PSP_RPMC_NVRAM fmap section not being large enough btw. once it had the correct size, it was reported as healthy -- To view, visit https://review.coreboot.org/c/coreboot/+/84707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7760c0bf7618ca60ef160329d0110ac8109032a Gerrit-Change-Number: 84707 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 21:42:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: commonlib/device_tree: Make END token part of struct_size
by Julius Werner (Code Review) 03 Dec '24

03 Dec '24

Julius Werner has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85460?usp=email ) Change subject: commonlib/device_tree: Make END token part of struct_size ...................................................................... Abandoned Weird Jenkins bug... reuploaded as CB:85462 -- To view, visit https://review.coreboot.org/c/coreboot/+/85460?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic756245fbd673d961cb66936e47691e1dbc86836 Gerrit-Change-Number: 85460 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: commonlib/device_tree: Make END token part of struct_size
by Julius Werner (Code Review) 03 Dec '24

03 Dec '24

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85462?usp=email ) Change subject: commonlib/device_tree: Make END token part of struct_size ...................................................................... commonlib/device_tree: Make END token part of struct_size According to the FDT specification the FDT_END token is supposed to be the last token in the structure block, not a free-floating token immediately outside of it. That means we're supposed to count it in struct_size. It seems that the kernel never cared about this, but some FDT parsing utilities like `fdtgrep` do. Change-Id: Icdeadbeefcafed00dbabefeed1337c0debc86836 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/device_tree.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85462/1 diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c index cb7a596..b2daac9 100644 --- a/src/commonlib/device_tree.c +++ b/src/commonlib/device_tree.c @@ -935,12 +935,11 @@ uint8_t *struct_start = dest; header->structure_offset = htobe32(dest - (uint8_t *)start_dest); + be32enc(&dest[struct_size], FDT_TOKEN_END); + struct_size += sizeof(uint32_t); header->structure_size = htobe32(struct_size); dest += struct_size; - *((uint32_t *)dest) = htobe32(FDT_TOKEN_END); - dest += sizeof(uint32_t); - uint8_t *strings_start = dest; header->strings_offset = htobe32(dest - (uint8_t *)start_dest); header->strings_size = htobe32(strings_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/85462?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdeadbeefcafed00dbabefeed1337c0debc86836 Gerrit-Change-Number: 85462 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
by Rob Barnes (Code Review) 03 Dec '24

03 Dec '24

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85461?usp=email ) Change subject: ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant ...................................................................... ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant This change simply replaces 0x80 with a top level constant called ACPI_NOTIFY_CROS_EC_MKBP. There are no functional changes. BUG=b:343288326 TEST=Build Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee --- M src/ec/google/chromeec/acpi/ec.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85461/1 diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 741ad59..f04ce6a 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -12,6 +12,7 @@ #define EC_OEM_VARIABLE_DATA_MASK 0x7 #define INT3400_ODVP_CHANGED 0x88 +#define ACPI_NOTIFY_CROS_EC_MKBP 0x80 #define ACPI_NOTIFY_CROS_EC_PANIC 0xB0 // Mainboard specific throttle handler @@ -437,7 +438,7 @@ Method (_Q1B, 0, NotSerialized) { Printf ("EC: MKBP") - Notify (CREC, 0x80) + Notify (CREC, ACPI_NOTIFY_CROS_EC_MKBP) } #ifdef EC_ENABLE_PD_MCU_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/85461?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee Gerrit-Change-Number: 85461 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com>

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[XS] Change in coreboot[main]: commonlib/device_tree: Make END token part of struct_size
by Julius Werner (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Yu-Ping Wu. Hello Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85460?usp=email to review the following change. Change subject: commonlib/device_tree: Make END token part of struct_size ...................................................................... commonlib/device_tree: Make END token part of struct_size According to the FDT specification the FDT_END token is supposed to be the last token in the structure block, not a free-floating token immediately outside of it. That means we're supposed to count it in struct_size. It seems that the kernel never cared about this, but some FDT parsing utilities like `fdtgrep` do. Change-Id: Ic756245fbd673d961cb66936e47691e1dbc86836 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/device_tree.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/85460/1 diff --git a/src/commonlib/device_tree.c b/src/commonlib/device_tree.c index cb7a596..b2daac9 100644 --- a/src/commonlib/device_tree.c +++ b/src/commonlib/device_tree.c @@ -935,12 +935,11 @@ uint8_t *struct_start = dest; header->structure_offset = htobe32(dest - (uint8_t *)start_dest); + be32enc(&dest[struct_size], FDT_TOKEN_END); + struct_size += sizeof(uint32_t); header->structure_size = htobe32(struct_size); dest += struct_size; - *((uint32_t *)dest) = htobe32(FDT_TOKEN_END); - dest += sizeof(uint32_t); - uint8_t *strings_start = dest; header->strings_offset = htobe32(dest - (uint8_t *)start_dest); header->strings_size = htobe32(strings_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/85460?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic756245fbd673d961cb66936e47691e1dbc86836 Gerrit-Change-Number: 85460 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC
by Christian Walter (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Christian Walter has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85455?usp=email ) Change subject: soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85455?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376 Gerrit-Change-Number: 85455 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 19:18:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024