coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Jarried Lin (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 11: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85362/comment/d0a41f5f_2609382d?us… : PS10, Line 10: e( > Okay, This will be modified in the next release. Done https://review.coreboot.org/c/coreboot/+/85362/comment/4d4faea0_2eb0d8cc?us… : PS10, Line 16: set bit[3] > Okay, This will be modified in the next release. Done File src/soc/mediatek/mt8196/booker.c: https://review.coreboot.org/c/coreboot/+/85362/comment/60072edc_08017bf8?us… : PS10, Line 11: OFF_REG_POR_SBSX_CFG_CTL > Okay, This will be modified in the next release. Done https://review.coreboot.org/c/coreboot/+/85362/comment/aa28e640_b5c82797?us… : PS10, Line 25: 64p > NO. The register por_sbsx_cfg_ctl is 64bits width by checking CI-700 TRM. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 06:49:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Jarried Lin (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Hello Dehui Sun, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85362?usp=email to look at the new patch set (#11). Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... soc/mediatek/mt8196: Add booker driver The MediaTek booker (the customized ARM CI-700) mainly uses CHI protocol, but doesn't support coherence (which is achieved through ACP solution). Additionally, the booker also uses other protocols such as AXI, which translates CHI transactions into EMI's AXI transactions. Currently, the mt8196 booker only uses the functions of SLC CMO routing. If downstream SLC needs CMO command propagation from the DSU, it is needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of each SBSX node in order to propagate the CMO command. TEST=build pass, check boot log with: [booker_init] AP hash rule: 0xbe00. BUG=b:317009620 Signed-off-by: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/booker.c M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/booker.h 4 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85362/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[M] Change in coreboot[main]: driver/sndw/alc1320: add ALC1320 support
by Dolan Liu (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Dolan Liu. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85469?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: driver/sndw/alc1320: add ALC1320 support ...................................................................... driver/sndw/alc1320: add ALC1320 support Test only add ALC1320 support Change-Id: I78bf449a9023d9574c07a4f4cbdcefc378499bc4 --- M src/drivers/soundwire/alc1308/Kconfig M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc711/alc711.c 3 files changed, 61 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/85469/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78bf449a9023d9574c07a4f4cbdcefc378499bc4 Gerrit-Change-Number: 85469 Gerrit-PatchSet: 2 Gerrit-Owner: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove non-thread safe debug print
by Patrick Rudolph (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Paul Menzel, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85288?usp=email ) Change subject: soc/intel/xeon_sp: Remove non-thread safe debug print ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85288/comment/4966d5b5_a093d29b?us… : PS1, Line 7: Fix debug print > Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85288?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cbc9cb11da8397ab6c2e8e56414558a8a0db93b Gerrit-Change-Number: 85288 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 06:39:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Dehui Sun (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Dehui Sun has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 10: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85362/comment/49323077_229f964f?us… : PS10, Line 10: e( > space Okay, This will be modified in the next release. https://review.coreboot.org/c/coreboot/+/85362/comment/07faf1b7_2c76a56b?us… : PS10, Line 16: set bit[3] > it is needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of each SBSX node in ord […] Okay, This will be modified in the next release. File src/soc/mediatek/mt8196/booker.c: https://review.coreboot.org/c/coreboot/+/85362/comment/916f2f95_f4bd157d?us… : PS10, Line 11: OFF_REG_POR_SBSX_CFG_CTL > POR_SBSX_CFG_CTL_OFFSET Okay, This will be modified in the next release. https://review.coreboot.org/c/coreboot/+/85362/comment/7bdc6805_8842f8f4?us… : PS10, Line 25: 64p > I think it is a 32-bit register ? NO. The register por_sbsx_cfg_ctl is 64bits width by checking CI-700 TRM. -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 04 Dec 2024 06:39:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[M] Change in coreboot[main]: driver/sndw/alc1320: add ALC1320 support
by Dolan Liu (Code Review) 04 Dec '24

04 Dec '24

Dolan Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85469?usp=email ) Change subject: driver/sndw/alc1320: add ALC1320 support ...................................................................... driver/sndw/alc1320: add ALC1320 support Test only add ALC1320 support Change-Id: I78bf449a9023d9574c07a4f4cbdcefc378499bc4 --- M src/drivers/soundwire/alc1308/Kconfig M src/drivers/soundwire/alc1308/alc1308.c M src/drivers/soundwire/alc711/alc711.c 3 files changed, 59 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/85469/1 diff --git a/src/drivers/soundwire/alc1308/Kconfig b/src/drivers/soundwire/alc1308/Kconfig index edefe94..14c1a0b 100644 --- a/src/drivers/soundwire/alc1308/Kconfig +++ b/src/drivers/soundwire/alc1308/Kconfig @@ -2,3 +2,8 @@ config DRIVERS_SOUNDWIRE_ALC1308 bool + +config DRIVERS_SOUNDWIRE_ALC1320 + bool + help + SoundWire driver for Realtek ALC722 device diff --git a/src/drivers/soundwire/alc1308/alc1308.c b/src/drivers/soundwire/alc1308/alc1308.c index fc7b2af..c4e2992 100644 --- a/src/drivers/soundwire/alc1308/alc1308.c +++ b/src/drivers/soundwire/alc1308/alc1308.c @@ -31,6 +31,21 @@ .sink_port_list = SOUNDWIRE_PORT(1) }; +static struct soundwire_slave alc1320_slave = { + .wake_up_unavailable = false, + .test_mode_supported = true, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = true, + .bank_delay_supported = false, + .port15_read_behavior = true, + .source_port_list = SOUNDWIRE_PORT(2) | SOUNDWIRE_PORT(4) | + SOUNDWIRE_PORT(6) | SOUNDWIRE_PORT(8) | SOUNDWIRE_PORT(10), + .sink_port_list = SOUNDWIRE_PORT(1) | SOUNDWIRE_PORT(5), +}; + static struct soundwire_audio_mode alc1308_audio_mode = { /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ .bus_frequency_configs_count = 12, @@ -70,9 +85,43 @@ .port_audio_mode_list = { 0 } }; +static struct soundwire_dpn alc1320_dp1 = { + .port_wordlength_configs_count = 3, + .port_wordlength_configs = { 16, 20, 24 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = true, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = 0xf, + .max_async_buffer = 0x08, + .port_audio_mode_count = 2, + .port_audio_mode_list = { 0, 1 } +}; + static const struct soundwire_codec alc1308_codec = { +#if CONFIG(DRIVERS_SOUNDWIRE_ALC1320) + .slave = &alc1320_slave, + .dpn = { + { + /* Data Input for Speaker Path */ + .port = 1, + .sink = &alc1320_dp1 + }, + { + /* Data out for I.V sensing */ + .port = 1, + .source = &alc1320_dp1 + }, + { + /* Data out for I.V sensing */ + .port = 5, + .source = &alc1320_dp1 + } + } +#else .slave = &alc1308_slave, - .audio_mode = { &alc1308_audio_mode }, .dpn = { { /* Data Input for Speaker Path */ @@ -90,7 +139,8 @@ .source = &alc1308_dp1 } } - +#endif + .audio_mode = { &alc1308_audio_mode } }; static void soundwire_alc1308_fill_ssdt(const struct device *dev) diff --git a/src/drivers/soundwire/alc711/alc711.c b/src/drivers/soundwire/alc711/alc711.c index 68c0474..6c20cdf 100644 --- a/src/drivers/soundwire/alc711/alc711.c +++ b/src/drivers/soundwire/alc711/alc711.c @@ -183,9 +183,9 @@ } } #endif - .audio_mode = { &alc711_audio_mode }, if (config->multilane) - .multilane = multilane; + .multilane = multilane, + .audio_mode = { &alc711_audio_mode } }; static void soundwire_alc711_fill_ssdt(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/85469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78bf449a9023d9574c07a4f4cbdcefc378499bc4 Gerrit-Change-Number: 85469 Gerrit-PatchSet: 1 Gerrit-Owner: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: cbfstool: Add hash to more than one region
by Bao Zheng (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85468?usp=email to review the following change. Change subject: cbfstool: Add hash to more than one region ...................................................................... cbfstool: Add hash to more than one region Change-Id: I8f9a5baa2699468380b942b3bdc104cab78adf5f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/cbfstool/cbfstool.c 1 file changed, 11 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85468/1 diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 25f4847..a8650fd 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -162,10 +162,16 @@ } else { struct cbfs_image cbfs; struct cbfs_file *mh_container; + const char *current_region; + if (strcmp(param.region_name, "COREBOOTB") == 0) + current_region = "COREBOOTB"; + else + current_region = SECTION_NAME_PRIMARY_CBFS; + if (!partitioned_file_read_region(&buffer, param.image_file, - SECTION_NAME_PRIMARY_CBFS)) + current_region)) goto no_metadata_hash; - mhc.region = SECTION_NAME_PRIMARY_CBFS; + mhc.region = current_region; if (cbfs_image_from_buffer(&cbfs, &buffer, param.headeroffset)) goto no_metadata_hash; mh_container = cbfs_get_entry(&cbfs, "bootblock"); @@ -245,7 +251,8 @@ will recalculate and update the metadata hash in the bootblock if needed. */ static int maybe_update_metadata_hash(struct cbfs_image *cbfs) { - if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) + if (strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS) && + strcmp(param.region_name, "COREBOOTB")) return 0; /* Metadata hash only embedded in primary CBFS. */ struct mh_cache *mhc = get_mh_cache(); @@ -1601,7 +1608,7 @@ vb2_digest_size(real_hash.algo)); printf("[METADATA HASH]\t%s:%s", vb2_get_hash_algorithm_name(real_hash.algo), hash_str); - if (!strcmp(param.region_name, SECTION_NAME_PRIMARY_CBFS)) { + if (mhc->cbfs_hash.algo != VB2_HASH_INVALID) { if (!memcmp(mhc->cbfs_hash.raw, real_hash.raw, vb2_digest_size(real_hash.algo))) { printf(":valid"); -- To view, visit https://review.coreboot.org/c/coreboot/+/85468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9a5baa2699468380b942b3bdc104cab78adf5f Gerrit-Change-Number: 85468 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

1 0

[M] Change in coreboot[main]: amdfwtool: Split the A/B level 2 with PSP level 1
by Bao Zheng (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85467?usp=email to review the following change. Change subject: amdfwtool: Split the A/B level 2 with PSP level 1 ...................................................................... amdfwtool: Split the A/B level 2 with PSP level 1 Change-Id: Ie9230e333dc5b1eca5beee1d3a57e815764c3cf3 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/handle_file.c M util/amdfwtool/opts.c 4 files changed, 49 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85467/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 24eaaf9..ae5ac14 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1070,11 +1070,15 @@ ctx->pspdir_bak = new_psp_dir(ctx, cb_config->multi_level, cookie); } else if (cookie == PSPL2_COOKIE) { if (ctx->pspdir2 == NULL) { + if (cb_config->ral2_location != 0) + set_current_pointer(ctx, cb_config->ral2_location); if (cb_config->need_ish && ctx->ish_a_dir == NULL) /* Need ISH */ ctx->ish_a_dir = new_ish_dir(ctx); pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); ctx->pspdir2 = pspdir; } else if (ctx->pspdir2_b == NULL) { + if (cb_config->rbl2_location != 0) + set_current_pointer(ctx, cb_config->rbl2_location); if (cb_config->need_ish && ctx->ish_b_dir == NULL) /* Need ISH */ ctx->ish_b_dir = new_ish_dir(ctx); pspdir = new_psp_dir(ctx, cb_config->multi_level, cookie); @@ -1970,6 +1974,8 @@ ctx.current - offset : sizeof(embedded_firmware); uint32_t ret_bytes; + if (cb_config.ral2_location != 0 && cb_config.rbl2_location != 0) + bytes = (void *)ctx.pspdir - (void *)ctx.amd_romsig_ptr + AMDFW_TABLE_SIZE(ctx.pspdir); ret_bytes = write_from_buf_to_file(targetfd, BUFF_OFFSET(ctx, offset), bytes); if (bytes != ret_bytes) { fprintf(stderr, "Error: Writing to file %s failed\n", cb_config.output); @@ -1985,13 +1991,31 @@ ssize_t bytes; bytes = write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.body_location), - ctx.current - cb_config.body_location); + ctx.current - cb_config.body_location, BODY_FILE_SUFFIX); if (bytes != ctx.current - cb_config.body_location) { fprintf(stderr, "Error: Writing body\n"); retval = 1; } } + if (cb_config.recovery_ab && cb_config.ral2_location && cb_config.rbl2_location) { + ssize_t abytes = 0, bbytes = 0; + if (ctx.biosdir2 != NULL) { + abytes = (void *)ctx.biosdir2 - (void *)ctx.pspdir2 + + AMDFW_TABLE_SIZE(ctx.biosdir2); + write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.ral2_location), + abytes, RA_FILE_SUFFIX); + } + if (ctx.biosdir2_b != NULL) { + bbytes = (void *)ctx.biosdir2_b - (void *)ctx.pspdir2_b + + AMDFW_TABLE_SIZE(ctx.biosdir2_b); + write_body(cb_config.output, BUFF_OFFSET(ctx, cb_config.rbl2_location), + bbytes, RB_FILE_SUFFIX); + } + if (abytes != bbytes) + fprintf(stderr, "Warning: The size of A and B tables are not the same\n"); + } + if (cb_config.manifest_file) { dump_blob_version(cb_config.manifest_file, amd_psp_fw_table); } diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index f87fbf5..0328a6e 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -431,7 +431,7 @@ enum platform soc_id; uint8_t efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag; - uint32_t body_location, efs_location; + uint32_t body_location, efs_location, ral2_location, rbl2_location; uint64_t signed_start_addr; char *manifest_file; const char *signed_output_file; @@ -461,6 +461,9 @@ ish_directory_table *ish_a_dir, *ish_b_dir; } context; +#define AMDFW_TABLE_SIZE(tb) (((psp_directory_table *)(tb))-> \ + header.additional_info_fields.dir_size * TABLE_ALIGNMENT) + uint8_t process_config(FILE *config, amd_cb_config *cb_config); void process_signed_psp_firmwares(const char *signed_rom, amd_fw_entry *fw_table, @@ -472,11 +475,13 @@ #define EFS_FILE_SUFFIX ".efs" #define TMP_FILE_SUFFIX ".tmp" #define BODY_FILE_SUFFIX ".body" +#define RA_FILE_SUFFIX ".ra" +#define RB_FILE_SUFFIX ".rb" void write_or_fail(int fd, void *ptr, size_t size); ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size); ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size); -ssize_t write_body(char *output, void *body_offset, ssize_t body_size); +ssize_t write_body(char *output, void *body_offset, ssize_t body_size, char *suffix); ssize_t copy_blob(void *dest, const char *src_file, size_t room); #define OK 0 diff --git a/util/amdfwtool/handle_file.c b/util/amdfwtool/handle_file.c index c37bb2c..bc16ff5 100644 --- a/util/amdfwtool/handle_file.c +++ b/util/amdfwtool/handle_file.c @@ -83,7 +83,7 @@ return buf_size; } -ssize_t write_body(char *output, void *body_offset, ssize_t body_size) +ssize_t write_body(char *output, void *body_offset, ssize_t body_size, char *suffix) { char body_name[PATH_MAX], body_tmp_name[PATH_MAX]; int ret; @@ -93,7 +93,7 @@ /* Create a tmp file and rename it at the end so that make does not get confused if amdfwtool is killed for some unexpected reasons. */ ret = snprintf(body_tmp_name, sizeof(body_tmp_name), "%s%s%s", - output, BODY_FILE_SUFFIX, TMP_FILE_SUFFIX); + output, suffix, TMP_FILE_SUFFIX); if (ret < 0) { fprintf(stderr, "Error %s forming BODY tmp file name: %d\n", strerror(errno), ret); @@ -117,7 +117,7 @@ close(fd); /* Rename the tmp file */ - ret = snprintf(body_name, sizeof(body_name), "%s%s", output, BODY_FILE_SUFFIX); + ret = snprintf(body_name, sizeof(body_name), "%s%s", output, suffix); if (ret < 0) { fprintf(stderr, "Error %s forming BODY file name: %d\n", strerror(errno), ret); return -1; diff --git a/util/amdfwtool/opts.c b/util/amdfwtool/opts.c index 62bbc97..1e460a1 100644 --- a/util/amdfwtool/opts.c +++ b/util/amdfwtool/opts.c @@ -61,6 +61,8 @@ AMDFW_OPT_SIGNED_OUTPUT, AMDFW_OPT_SIGNED_ADDR, AMDFW_OPT_BODY_LOCATION, + AMDFW_OPT_RECOVERY_A_LOCATION, + AMDFW_OPT_RECOVERY_B_LOCATION, /* begin after ASCII characters */ LONGOPT_SPI_READ_MODE = 256, LONGOPT_SPI_SPEED = 257, @@ -120,6 +122,8 @@ {"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED }, {"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG }, {"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION }, + {"recovery-a-location", required_argument, 0, AMDFW_OPT_RECOVERY_A_LOCATION }, + {"recovery-b-location", required_argument, 0, AMDFW_OPT_RECOVERY_B_LOCATION }, /* other */ {"output", required_argument, 0, AMDFW_OPT_OUTPUT }, {"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE }, @@ -611,7 +615,12 @@ retval = 1; } break; - + case AMDFW_OPT_RECOVERY_A_LOCATION: + cb_config->ral2_location = (uint32_t)strtoul(optarg, &tmp, 16); + break; + case AMDFW_OPT_RECOVERY_B_LOCATION: + cb_config->rbl2_location = (uint32_t)strtoul(optarg, &tmp, 16); + break; default: break; } @@ -647,6 +656,10 @@ cb_config->efs_location = cb_config->efs_location - rom_base_address; if (cb_config->body_location & ~MAX_MAPPED_WINDOW_MASK) cb_config->body_location = cb_config->body_location - rom_base_address; + if (cb_config->ral2_location & ~MAX_MAPPED_WINDOW_MASK) + cb_config->ral2_location = cb_config->ral2_location - rom_base_address; + if (cb_config->rbl2_location & ~MAX_MAPPED_WINDOW_MASK) + cb_config->rbl2_location = cb_config->rbl2_location - rom_base_address; } /* If the flash size is larger than 16M, we assume the given -- To view, visit https://review.coreboot.org/c/coreboot/+/85467?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9230e333dc5b1eca5beee1d3a57e815764c3cf3 Gerrit-Change-Number: 85467 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

1 0

[XS] Change in coreboot[main]: amdfwtool: Set address mode of BIOS binary as context defines
by Bao Zheng (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85466?usp=email to review the following change. Change subject: amdfwtool: Set address mode of BIOS binary as context defines ...................................................................... amdfwtool: Set address mode of BIOS binary as context defines TEST=Binary identical test on platforms before mendocino Tested on Skyrim Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85466/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 50589dc..e8740b5 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1534,10 +1534,8 @@ exit(1); } - biosdir->entries[count].source = - RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS); - biosdir->entries[count].address_mode = - SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS); + biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir); + biosdir->entries[count].source = RUN_CURRENT(*ctx); adjust_current_pointer(ctx, bytes, 0x100U); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/85466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62 Gerrit-Change-Number: 85466 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

1 0

[XS] Change in coreboot[main]: DEMO: enable ab recovery
by Bao Zheng (Code Review) 04 Dec '24

04 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85465?usp=email to review the following change. Change subject: DEMO: enable ab recovery ...................................................................... DEMO: enable ab recovery Change-Id: Ib487fb67b8deaa4f9bb85d30db391a859320621f Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85465/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7b97ce7..4f08016 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -410,7 +410,7 @@ config PSP_RECOVERY_AB bool "Use A/B Recovery scheme" - default n + default y help Enable the PSP A/B Recovery mechanism -- To view, visit https://review.coreboot.org/c/coreboot/+/85465?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib487fb67b8deaa4f9bb85d30db391a859320621f Gerrit-Change-Number: 85465 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024