coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limits when battery is missing
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Hello Jamie Ryu, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85146?usp=email to look at the new patch set (#10). Change subject: mb/google/fatcat: Limit Power Limits when battery is missing ...................................................................... mb/google/fatcat: Limit Power Limits when battery is missing Ensure the board can boot by limiting the power limits if the battery is missing. This addresses the factory use case. BUG=b:377798581 TEST=See power limit override log message when the battery is missing on fatcat board Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85146/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 10 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat: Enable Intel DPTF support and configure policies
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Pranava Y N, Subrata Banik, Sukumar Ghorai. Hello Pranava Y N, Subrata Banik, Sukumar Ghorai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85457?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies ...................................................................... mb/google/fatcat: Enable Intel DPTF support and configure policies This commit enables the Dynamic Power, Thermal, and Frequency (DPTF) Framework for the fatcat board. DPTF is a system management Framework that allows the board to dynamically adjust its power and thermal settings based on the system load and thermal conditions. This can help to improve the board's performance and battery life. The following changes were made to enable DPTF: - Added the Intel DPTF driver to the board's Kconfig file. - Overrode the default DPTF settings in the fatcat overridetree.cb file. - Enabled the DPTF policy on the board. Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 130 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85457/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Gerrit-Change-Number: 85457 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Enable DPTF
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Pranava Y N, Subrata Banik, Sukumar Ghorai. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85457?usp=email ) Change subject: mb/google/fatcat: Enable DPTF ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: @sukumar, could you review the default DPTF values? -- To view, visit https://review.coreboot.org/c/coreboot/+/85457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Gerrit-Change-Number: 85457 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 03 Dec 2024 18:41:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/fatcat: Enable DPTF
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Pranava Y N, Subrata Banik. Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85457?usp=email ) Change subject: mb/google/fatcat: Enable DPTF ...................................................................... mb/google/fatcat: Enable DPTF Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 130 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85457/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index a67ea3b..bee6d71 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -5,6 +5,7 @@ select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index fba49fd..10a351a 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -137,11 +137,140 @@ }, }" + # Enable DPTF + register "dptf_enable" = "true" + device domain 0 on device ref igpu on probe DISPLAY DISPLAY_PRESENT end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""wwan"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 95000, + .max_power = 95000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/85457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Gerrit-Change-Number: 85457 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Hello Jamie Ryu, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85146?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... mb/google/fatcat: Limit Power Limit when battery is missing Ensure the board can boot by limiting the power limits if the battery is missing. This addresses the factory use case. BUG=b:377798581 TEST=See power limit override log message when the battery is missing on fatcat board Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85146/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 9 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Reduce PL2/PL4 based on battery status
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Jérémy Compostella has restored this change. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Reduce PL2/PL4 based on battery status ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: restore Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number
by Subrata Banik (Code Review) 03 Dec '24

03 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85456?usp=email ) Change subject: soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number ...................................................................... soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number This commit enhances the SMBIOS Type 4 table by populating the "serial number" field with the unique SoC QDF information retrieved via PMC IPC. This improvement provides more accurate and detailed processor information for Panther Lake SoCs and onwards, aiding in: - System identification - Diagnostics - Asset management Previously, the serial number field was not populated. TEST=Able to build and boot google/fatcat. Example of SMBIOS Type 4 output: Before this commit: Serial Number: Not Specified Asset Tag: Not Specified Part Number: Not Specified After this commit: Serial Number: ABCD (Example SoC QDF information) Asset Tag: Not Specified Part Number: Not Specified Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/cpu.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/85456/1 diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 28fa1d8..4b3c950 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -15,6 +15,8 @@ #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelblocks/msr.h> +#include <intelblocks/pmclib.h> +#include <smbios.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -234,3 +236,14 @@ return 0; } + +/* Override SMBIOS type 4 processor serial numbers */ +const char *smbios_processor_serial_number(void) +{ + char *qdf = retrieve_soc_qdf_info_via_pmc_ipc(); + + if (qdf != NULL) + return qdf; + else + return ""; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85456?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a0bb0e44c619393b8f058ae30fbf2f9719b724 Gerrit-Change-Number: 85456 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC
by Subrata Banik (Code Review) 03 Dec '24

03 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85455?usp=email ) Change subject: soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC ...................................................................... soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC This commit introduces a new function, `retrieve_soc_qdf_info_via_pmc_ipc()`, to retrieve the SoC QDF information string using the PMC IPC mechanism. This function allows for more flexible use of the SoC QDF information, enabling its use in various data structures like the SMBIOS Type 4 table. The existing `pmc_dump_soc_qdf_info()` function is updated to use this new function to retrieve the QDF information before printing it. TEST=Able to build and boot google/fatcat. Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 29 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/85455/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 18d1b4d..5423865 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -287,4 +287,15 @@ */ void pmc_dump_soc_qdf_info(void); +/* + * Retrieve SoC QDF information. + * + * This function retrieves the SoC QDF information string, which can be used to + * populate various data structures, such as the SMBIOS Type 4 table for CPU + * identification. + * + * @return A pointer to the SoC QDF information string. + */ +char *retrieve_soc_qdf_info_via_pmc_ipc(void); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index c51a960..0fadd6e 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -934,20 +934,16 @@ printk(BIOS_ERR, "PMC: Failed sending PCI Enumeration Done Command\n"); } -/* - * This function reads and prints SoC QDF information using PMC interface - * if SOC_QDF_DYNAMIC_READ_PMC config is enabled. - */ -void pmc_dump_soc_qdf_info(void) +char *retrieve_soc_qdf_info_via_pmc_ipc(void) { struct pmc_ipc_buffer req = { 0 }; struct pmc_ipc_buffer rsp; uint32_t cmd_reg; int r; - char qdf_info[5]; + static char qdf_info[5] = { 0 }; if (!CONFIG(SOC_QDF_DYNAMIC_READ_PMC)) - return; + return NULL; req.buf[0] = PMC_IPC_CMD_REGID_SOC_QDF; cmd_reg = pmc_make_ipc_cmd(PMC_IPC_CMD_SOC_REG_ACC, @@ -959,7 +955,7 @@ if (r < 0 || rsp.buf[0] == 0) { printk(BIOS_ERR, "%s: pmc_send_ipc_cmd failed or QDF not available.\n", __func__); - return; + return NULL; } qdf_info[0] = ((rsp.buf[0] >> 24) & 0xFF); @@ -967,5 +963,18 @@ qdf_info[2] = ((rsp.buf[0] >> 8) & 0xFF); qdf_info[3] = (rsp.buf[0] & 0xFF); qdf_info[4] = '\0'; - printk(BIOS_INFO, "SoC QDF: %s\n", qdf_info); + + return qdf_info; +} + +/* + * This function reads and prints SoC QDF information using PMC interface + * if SOC_QDF_DYNAMIC_READ_PMC config is enabled. + */ +void pmc_dump_soc_qdf_info(void) +{ + char *qdf = retrieve_soc_qdf_info_via_pmc_ipc(); + + if (qdf != NULL) + printk(BIOS_INFO, "SoC QDF: %s\n", qdf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85455?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ccf8aae4be9e9bbcad8ef2f422b88edef66376 Gerrit-Change-Number: 85455 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Reduce PL2/PL4 based on battery status
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Reduce PL2/PL4 based on battery status ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Implement declared but missing functions
by Jérémy Compostella (Code Review) 03 Dec '24

03 Dec '24

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85145?usp=email ) Change subject: mb/google/fatcat: Implement declared but missing functions ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/85145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77f Gerrit-Change-Number: 85145 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit December 2024