coreboot-gerrit December 2024

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#6). Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 73 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 6 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#5). Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 75 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 5 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[NoOp] Change in coreboot[main]: mb/starlabs/starlite_adl: Lower the lowest brightness level
by Sean Rhodes (Code Review) 29 Dec '24

29 Dec '24

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84735?usp=email ) Change subject: mb/starlabs/starlite_adl: Lower the lowest brightness level ...................................................................... Abandoned Not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/84735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad575ab15ef97623eec246ffc7a1128880c5fc5d Gerrit-Change-Number: 84735 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant
by Keith Hui (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Keith Hui. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85768?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant ...................................................................... mb/asus/p8x7x-series: Add SABERTOOTH Z77 as a variant Based on p8z77-v, with adjusted overridetree, GPIO, GMA, HDA verbs and USB port config based on boardview and vendor firmware image. It builds, but not hardware tested. Unlike most other variants, this one allows use of MRC raminit, if for testing. It has no serial port, but the code describes a possible hardware hack to get one working to receive console output. A debug port allows access to LPC bus. Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/sabertooth_z77.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/board_info.txt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.default A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/cmos.layout A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/data.vbt A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/early_init.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/gpio.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/sabertooth_z77/overridetree.cb 13 files changed, 708 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85768/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85768?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c26e751a224491c5aa1ce1035c55955ef0ee83c Gerrit-Change-Number: 85768 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/asrock/z77_extreme4: Enable voltage rail adjustments
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Riku Viitanen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85795?usp=email to look at the new patch set (#3). Change subject: mb/asrock/z77_extreme4: Enable voltage rail adjustments ...................................................................... mb/asrock/z77_extreme4: Enable voltage rail adjustments This board has two Nuvoton NCT3933U current DAC chips on SMBus, enabling firmware to adjust several voltage rails. The correct registers and offsets were reverse engineered by adjusting voltages in vendor firmware and observing what it wrote there. Works with commit 38dcb78ede28 ("nb/sandybridge: Implement automatic DRAM voltage setting") to enable firmware to set the DRAM voltage. TEST=With few XMP and non-XMP modules. Monitored DRAM voltage on test point VT10 (located near the SLI logo) with a multimeter. Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asrock/z77_extreme4/Kconfig M src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/romstage.c 3 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85795/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Gerrit-Change-Number: 85795 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 78 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 4 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: mb/asrock/z77_extreme4: Enable voltage rail adjustments
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Riku Viitanen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85795?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/asrock/z77_extreme4: Enable voltage rail adjustments ...................................................................... mb/asrock/z77_extreme4: Enable voltage rail adjustments This board has two Nuvoton NCT3933U current DAC chips on SMBus, enabling firmware to adjust several voltage rails. The correct registers and offsets were reverse engineered by adjusting voltages in vendor firmware and observing what it wrote there. Works with commit 7fa8a3aeeea4 ("nb/sandybridge: Implement automatic DRAM voltage setting") to enable firmware to set the DRAM voltage. TEST=With few XMP and non-XMP modules. Monitored DRAM voltage on test point VT10 (located near the SLI logo) with a multimeter. Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asrock/z77_extreme4/Kconfig M src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/romstage.c 3 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85795/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Gerrit-Change-Number: 85795 Gerrit-PatchSet: 2 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[S] Change in coreboot[main]: util/findusb_debug: Check for lsusb and lspci
by Nicholas Chin (Code Review) 29 Dec '24

29 Dec '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85796?usp=email ) Change subject: util/findusb_debug: Check for lsusb and lspci ...................................................................... util/findusb_debug: Check for lsusb and lspci Add a check to make sure lsusb and lspci are installed, as the script relies on them to function properly. Previously, if lsusb was not installed, the script proceeded as if nothing was wrong, but never found any devices plugged into the debug port. If lspci was not found, the script exited saying that no EHCI debug capable controller was found. The "command not found" messages that normally would have been shown in these situations was not being shown, as stderr is redirected to /dev/null to hide error messages that don't matter as per the comment near the top of the script. Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/find_usbdebug/find_usbdebug.sh 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85796/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Gerrit-Change-Number: 85796 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: util/findusb_debug: Check for lsusb and lspci
by Nicholas Chin (Code Review) 29 Dec '24

29 Dec '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85796?usp=email ) Change subject: util/findusb_debug: Check for lsusb and lspci ...................................................................... util/findusb_debug: Check for lsusb and lspci Add a check to make sure lsusb and lspci are installed, as the script relies on them to function properly. Previously, if lsusb was not installed, the script proceeded as if nothing was wrong, but never found any devices plugged into the debug port. If lspci was not found, the script exited saying that no EHCI debug capable controller was found. The "command not found" messages that normally would have been shown in these situations was not being shown, as stderr is redirected to /dev/null to hide error messages that don't matter as per the comment near the top of the script. Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/find_usbdebug/find_usbdebug.sh 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85796/1 diff --git a/util/find_usbdebug/find_usbdebug.sh b/util/find_usbdebug/find_usbdebug.sh index de370b1..cd269ab 100755 --- a/util/find_usbdebug/find_usbdebug.sh +++ b/util/find_usbdebug/find_usbdebug.sh @@ -27,6 +27,19 @@ echo "Must be run as root. Exiting." exit 1 fi + +if ! command -v lsusb; then + echo "lsusb not found. Please install \"usbutils\" from your +Distribution's package manager. Exiting." + exit 1 +fi + +if ! command -v lspci; then + echo "lspci not found. Please install \"pciutils\" from your +Distribution's package manager. Exiting." + exit 1 +fi + dmesgfile=$1 find_devs_in_tree () { -- To view, visit https://review.coreboot.org/c/coreboot/+/85796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib56a20aab9552aa6321c2fb9ad0d2ca7d6cd00c7 Gerrit-Change-Number: 85796 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

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[S] Change in coreboot[main]: mb/asrock/z77_extreme4: Enable voltage rail adjustments
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85795?usp=email ) Change subject: mb/asrock/z77_extreme4: Enable voltage rail adjustments ...................................................................... mb/asrock/z77_extreme4: Enable voltage rail adjustments This board has two Nuvoton NCT3933U current DAC chips on SMBus, enabling firmware to adjust several voltage rails. The correct registers and offsets were reverse engineered by adjusting voltages in vendor firmware and observing what it wrote there. Works with commit 7fa8a3aeeea4 (nb/sandybridge: Implement automatic DRAM voltage setting) to enable firmware to set the DRAM voltage. TEST=With few XMP and non-XMP modules. Monitored DRAM voltage on test point VT10 (located near the SLI logo) with a multimeter. Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/mainboard/asrock/z77_extreme4/Kconfig M src/mainboard/asrock/z77_extreme4/Makefile.mk A src/mainboard/asrock/z77_extreme4/romstage.c 3 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85795/1 diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig b/src/mainboard/asrock/z77_extreme4/Kconfig index 4b31543..d5092c2 100644 --- a/src/mainboard/asrock/z77_extreme4/Kconfig +++ b/src/mainboard/asrock/z77_extreme4/Kconfig @@ -12,6 +12,7 @@ select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select INTEL_INT15 + select MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE select MAINBOARD_HAS_LIBGFXINIT select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/asrock/z77_extreme4/Makefile.mk b/src/mainboard/asrock/z77_extreme4/Makefile.mk index e4b6fbf..7e36e28 100644 --- a/src/mainboard/asrock/z77_extreme4/Makefile.mk +++ b/src/mainboard/asrock/z77_extreme4/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/asrock/z77_extreme4/romstage.c b/src/mainboard/asrock/z77_extreme4/romstage.c new file mode 100644 index 0000000..e0f0913 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/romstage.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <stdint.h> +#include <console/console.h> +#include <commonlib/bsd/helpers.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <device/smbus_host.h> + +struct nct3933u_ch { + uint8_t address; + uint8_t channel; + int voltage_default; /* in microvolts */ + int voltage_step; /* in microvolts */ +}; + +struct nct3933u_ch cpu_pll = {0x14, 1, 1832000, 8200}; +struct nct3933u_ch vtt = {0x14, 2, 1048000, 9313}; +struct nct3933u_ch pch = {0x14, 3, 1059000, 9313}; +/*struct nct3933u_ch vrefca_a = {0x15, 1, ?, ?};*/ +/*struct nct3933u_ch vrefdq_a = {0x15, 2, ?, ?};*/ +struct nct3933u_ch dram = {0x15, 3, 1600000, 5000}; + + +/* takes millivolts as input */ +static enum cb_err set_voltage(struct nct3933u_ch dac, int voltage) { + voltage *= 1000; /* Convert to microvolts */ + int offset = (voltage - dac.voltage_default)/dac.voltage_step; + + if ((offset > 127) || (offset < -127)) + return CB_ERR; + + /* Convert the offset to sign-magnitude format for NCT3933U */ + offset = (ABS(offset) & 0x7f) | (offset & 0x80); + + smbus_write_byte(dac.address, dac.channel, offset); + + return CB_SUCCESS; +} + +void mainboard_set_dram_voltage(int voltage) { + set_voltage(dram, voltage); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85795?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic59c0c74f070c7d8ebd8e9c1760fe0b491c06a51 Gerrit-Change-Number: 85795 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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coreboot-gerrit December 2024