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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add p8b75-v variant
by Keith Hui (Code Review) 29 Dec '24

29 Dec '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85792?usp=email ) Change subject: mb/asus/p8x7x-series: Add p8b75-v variant ...................................................................... mb/asus/p8x7x-series: Add p8b75-v variant Not hardware tested; copied from p8h77-v and p8z77-m then adjusted USB port config and overridetree based on info seen from vendor firmware update and boardview. VBT extracted manually from vendor firmware update. Currently known facts about this board that aren't already coded into this patch: - 3 PCI slots wired to B75 PCI bridge - DRAM_LED on GP07 of SIO and power LED on GPIO27 of PCH, just like p8z77-m - Has TWO 8MiB SPI flash chips on board, both wired to PCH. It appears to use both to build a 16MiB flash space but that's to be confirmed. Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p8b75-v.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8b75-v/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8b75-v/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8b75-v/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8b75-v/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/overridetree.cb 13 files changed, 645 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85792/1 diff --git a/Documentation/mainboard/asus/p8b75-v.md b/Documentation/mainboard/asus/p8b75-v.md new file mode 100644 index 0000000..60805bf --- /dev/null +++ b/Documentation/mainboard/asus/p8b75-v.md @@ -0,0 +1,74 @@ +# ASUS P8B75-V + +This page describes how to run coreboot on the [ASUS P8B75-V]. + +## Flashing coreboot + +```{eval-rst} ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Model | W25Q64FVA1Q x2 | ++---------------------+----------------+ +| Size | 2*8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Socketed | yes | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | no | ++---------------------+----------------+ +``` + +The flash chips are located next to the SATA ports. There are two of them. Since the +8MiB vendor firmware image does not include IFD and ME firmware, it probably uses both +to produce a 16MiB flash space, but that is to be confirmed. + +To install coreboot for the first time, the flash chip must be removed and +flashed with an external programmer; flashing in-circuit doesn't work. +The flash chip is socketed, so it's easy to remove and reflash. + +## Known issues + +- This port is not hardware tested. + +- The PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for + an x8, and is electrically an x4 only. + +## Extra onboard button and LED + +The board has an `MemOK!` button that OEM firmware uses for memory tuning related to overclocking. +It connects to pin 74 of NCT6779D super I/O chip but currently does nothing under coreboot. + +It also has a `DRAM_LED` that lights up during memory training, and remains on if a memory error +occurred. It is controlled by GP07 signal of super I/O. coreboot supports this feature as well. + +## Technology + +```{eval-rst} ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8B75-V]: https://www.asus.com/supportonly/p8b75-v/helpdesk_knowledge/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1bbacaf..484ba8b 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -47,6 +47,7 @@ P3B-F <asus/p3b-f.md> P5Q <asus/p5q.md> P8C WS <asus/p8c_ws.md> +P8B75-V <asus/p8b75-v.md> P8H61-M LX <asus/p8h61-m_lx.md> P8H61-M Pro <asus/p8h61-m_pro.md> P8H77-V <asus/p8h77-v.md> diff --git a/src/mainboard/asus/p8x7x-series/Kconfig b/src/mainboard/asus/p8x7x-series/Kconfig index e278b56..f1212a6 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig +++ b/src/mainboard/asus/p8x7x-series/Kconfig @@ -56,6 +56,12 @@ select SUPERIO_NUVOTON_NCT6779D select SUPERIO_NUVOTON_COMMON_COM_A +config BOARD_ASUS_P8B75_V + select BOARD_ASUS_P8X7X_SERIES + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_NUVOTON_NCT6779D + select USE_NATIVE_RAMINIT + if BOARD_ASUS_P8X7X_SERIES config MAINBOARD_DIR @@ -68,6 +74,7 @@ default "p8z77-v_lx2" if BOARD_ASUS_P8Z77_V_LX2 default "p8z77-v" if BOARD_ASUS_P8Z77_V default "p8z77-m" if BOARD_ASUS_P8Z77_M + default "p8b75-v" if BOARD_ASUS_P8B75_V config MAINBOARD_PART_NUMBER default "P8C WS" if BOARD_ASUS_P8C_WS @@ -76,6 +83,7 @@ default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2 default "P8Z77-V" if BOARD_ASUS_P8Z77_V default "P8Z77-M" if BOARD_ASUS_P8Z77_M + default "P8B75-V" if BOARD_ASUS_P8B75_V config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/asus/p8x7x-series/Kconfig.name b/src/mainboard/asus/p8x7x-series/Kconfig.name index a5598ca..e65e285 100644 --- a/src/mainboard/asus/p8x7x-series/Kconfig.name +++ b/src/mainboard/asus/p8x7x-series/Kconfig.name @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config BOARD_ASUS_P8B75_V + bool "P8B75-V" + config BOARD_ASUS_P8C_WS bool "P8C_WS" diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/board_info.txt b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/board_info.txt new file mode 100644 index 0000000..6e32765 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/supportonly/p8b75-v/helpdesk_knowledge/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.default new file mode 100644 index 0000000..4501aa4 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout new file mode 100644 index 0000000..6cec2b1 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# audio_panel_type +# HD Audio or AC'97 +# +425 1 e 9 audio_panel_type + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# audio_panel_type +9 0 HDA +9 1 AC97 + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/data.vbt b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/data.vbt new file mode 100644 index 0000000..d17d1e6 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/early_init.c new file mode 100644 index 0000000..35d8f23 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/early_init.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) +#define GPIO0_DEV PNP_DEV(0x2e, NCT6779D_WDT1_GPIO01_V) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1a, 0x02); + /* Pin 37: Reset out + * Pin 95: GP24 (VCCSA overvoltage input) */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x60); + /* Pin 89: TODO: Check value against vendor firmware */ + pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e); + /* Serial port A, GP1x (take GP14 high during reset + * to disable ME and unlock flash chip) */ + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + /* Pin 120: PECI */ + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + + /* Turn on DRAM_LED. If raminit dies, this would remain on and we know + * we have a problem. We turn it off in ramstage. */ + pnp_set_logical_device(GPIO0_DEV); + pnp_write_config(GPIO0_DEV, 0x30, 0x02); + pnp_write_config(GPIO0_DEV, 0xe0, 0x7f); + pnp_write_config(GPIO0_DEV, 0xe1, 0x00); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + /* Enable UART */ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads new file mode 100644 index 0000000..e6b0407 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/gpio.c b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/gpio.c new file mode 100644 index 0000000..be086e05 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/gpio.c @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, /* Test point? */ + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, /* PME# */ + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, /* Power LED */ + .gpio28 = GPIO_DIR_OUTPUT, /* Unused */ + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, /* Unused */ + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_GPIO, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_GPIO, + .gpio63 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, + .gpio62 = GPIO_DIR_INPUT, + .gpio63 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, /* Clock out 3 - 48MHz to SIO */ + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/hda_verb.c new file mode 100644 index 0000000..e2125e3 --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/hda_verb.c @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <option.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ + 0x104384a8, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x104384a8), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_ATAPI, + AZALIA_SPDIF_OUT, + AZALIA_ATAPI_INTERNAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 3, 0)), /* SPDIF out 2 */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_LINE_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + 4, 1, 0)), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + 0xc, 5, 0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_FRONT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_PINK, + 0xc, 6, 0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_REAR_PANEL, + AZALIA_LINE_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLUE, + 4, 5, 15)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_FRONT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_GREEN, + 0xc, 2, 0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* SPDIF out 1 */ + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* SPDIF in */ + + 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + unsigned int ac97 = get_uint_option("audio_panel_type", 0) & 0x1; + + /* + * The verbs above are for a HD Audio front panel. + * With vendor firmware, if audio front panel type is set as AC97, line out 2 + * (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently. + * + * The differences are all in the "Misc" fields of configuration defaults (in byte 2) + * as shown below. ALC887 datasheet did not offer details on what those bits + * (listed as reserved in HDA spec) are, so we'll have to take their word for it. + * + * Pin | 0x19 | 0x1b + * -----+------+----- + * HDA | 1100 | 1100 + * AC97 | 1001 | 0001 + */ + + const u32 verbs[] = { + AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99), + AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41) + }; + + if ((viddid == 0x10ec0887) && ac97) { + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); + } +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8b75-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/overridetree.cb new file mode 100644 index 0000000..485339f --- /dev/null +++ b/src/mainboard/asus/p8x7x-series/variants/p8b75-v/overridetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1043 0x84ca inherit + chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 1, 0 }, /* Port 0: USB3 internal header, #3 */ + { 1, 0x557, 0 }, /* Port 1: USB3 internal header, #4 */ + { 1, 1, 1 }, /* Port 2: USB3 rear, bottom */ + { 1, 1, 1 }, /* Port 3: USB3 rear, top */ + { 1, 1, 2 }, /* Port 4: USB2 rear LAN, top */ + { 1, 9, 2 }, /* Port 5: Above, bottom, double check */ + { 0, 1, -1}, /* Port 6: Not present */ + { 0, 1, -1}, /* Port 7: Not present */ + { 1, 1, 4 }, /* Port 8: USB2 rear USB34, bottom */ + { 1, 1, 4 }, /* Port 9: USB2 rear USB34, top */ + { 1, 1, 5 }, /* Port 10: USB2 internal header USB56 */ + { 1, 1, 5 }, /* Port 11: USB2 internal header USB56 */ + { 1, 1, 6 }, /* Port 12: USB2 internal header USB78 */ + { 1, 1, 6 } /* Port 13: USB2 internal header USB78 */ + }" + register "gen1_dec" = "0x000c0291" + device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) + device ref pcie_rp5 on # RTL8111F GbE NIC + subsystemid 0x1849 0x1e1a #TODO: DOUBLE CHECK + device pci 00.0 on end # make onboard + end + device ref pcie_rp6 on end # PCIEX1_1 + device ref pcie_rp7 on end # PCIEX1_2 + device ref pci_bridge on end + + device ref lpc on + chip superio/nuvoton/nct6779d + device pnp 2e.1 on # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # UART A + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + irq 0x72 = 12 + + # KBC 12Mhz/A20 speed/sw KBRST + drq 0xf0 = 0x82 + drq 0x22 = 0xdf # Power down UART B + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-8 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1 + device pnp 2e.108 on # GPIO0 + drq 0xe0 = 0x7f + drq 0xe1 = 0x80 # DRAM_LED off + end + device pnp 2e.9 off end # GPIO8 + device pnp 2e.109 on end # GPIO1 + device pnp 2e.509 on end # GPIO5 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # H/W Monitor, FP LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # WDT1 + device pnp 2e.e off end # CIR Wake-up + device pnp 2e.f off end # Push-pull/Open-drain + device pnp 2e.14 on end # Port 80 UART + device pnp 2e.16 off end # Deep Sleep + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/85792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Gerrit-Change-Number: 85792 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Mario Scheithauer (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Johannes Hahn, Uwe Poeche, Werner Zeh. Mario Scheithauer has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) The change is no longer submittable: All-Comments-Resolved and Code-Review are unsatisfied now. Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/soc/intel/common/block/power_limit/power_limit.c: https://review.coreboot.org/c/coreboot/+/85606/comment/403e3a63_bef443b9?us… : PS5, Line 97: msr = rdmsr(MSR_PKG_POWER_LIMIT); Maybe one more thing... If you set the whole register to '0', you can skip the previous read. -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 5 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 29 Dec 2024 16:54:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MT6685 Clock IC driver
by Yidi Lin (Code Review) 29 Dec '24

29 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85734?usp=email ) Change subject: soc/mediatek/mt8196: Add MT6685 Clock IC driver ...................................................................... soc/mediatek/mt8196: Add MT6685 Clock IC driver Add MT6685 initial settings and ADC init settings to support Thermal Information Acquisition (TIA). TIA will read thermal info in HW. TEST=Build pass BUG=b:317009620 Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85734 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/common/include/soc/mt6685.h A src/soc/mediatek/common/mt6685.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6685.c M src/soc/mediatek/mt8196/pmif_init.c 5 files changed, 201 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/mt6685.h b/src/soc/mediatek/common/include/soc/mt6685.h new file mode 100644 index 0000000..5590a1b --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6685.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT6685_H__ +#define __SOC_MEDIATEK_MT6685_H__ + +#include <soc/spmi.h> +#include <types.h> + +struct mt6685_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +struct mt6685_key_setting { + unsigned short addr; + unsigned short val; +}; + +void mt6685_init(void); +void mt6685_init_pmif_arb(void); +void mt6685_write_field(u32 reg, u32 val, u32 mask, u32 shift); +u32 mt6685_read_field(u32 reg, u32 mask, u32 shift); +u8 mt6685_read8(u32 reg); +void mt6685_write8(u32 reg, u8 reg_val); +u16 mt6685_read16(u32 reg); +void mt6685_write16(u32 reg, u16 reg_val); +void mt6685_init_setting(void); + +#endif diff --git a/src/soc/mediatek/common/mt6685.c b/src/soc/mediatek/common/mt6685.c new file mode 100644 index 0000000..fa434f4 --- /dev/null +++ b/src/soc/mediatek/common/mt6685.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6685.h> +#include <soc/pmif.h> +#include <timer.h> + +#define MT6685_TOP_RST_MISC 0x127 +#define MT6685_TOP_RST_MISC_SET 0x128 + +static struct pmif *pmif_arb; +u32 mt6685_read_field(u32 reg, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_9, reg, mask, shift); +} + +void mt6685_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + assert(pmif_arb); + pmif_arb->write_field(pmif_arb, SPMI_SLAVE_9, reg, val, mask, shift); +} + +u8 mt6685_read8(u32 reg) +{ + u32 rdata = 0; + + assert(pmif_arb); + pmif_arb->read(pmif_arb, SPMI_SLAVE_9, reg, &rdata); + + return (u8)rdata; +} + +void mt6685_write8(u32 reg, u8 reg_val) +{ + assert(pmif_arb); + pmif_arb->write(pmif_arb, SPMI_SLAVE_9, reg, reg_val); +} + +u16 mt6685_read16(u32 reg) +{ + u16 rdata = 0; + + assert(pmif_arb); + pmif_arb->read16(pmif_arb, SPMI_SLAVE_9, reg, &rdata); + return rdata; +} + +void mt6685_write16(u32 reg, u16 reg_val) +{ + assert(pmif_arb); + pmif_arb->write16(pmif_arb, SPMI_SLAVE_9, reg, reg_val); +} + +static void mt6685_wdt_set(void) +{ + mt6685_write_field(MT6685_TOP_RST_MISC_SET, 0x3, 0xFF, 0); +} + +static const struct mt6685_key_setting key_protect_setting[] = { + {0x39E, 0x7A}, + {0x39F, 0x99}, + {0x3A8, 0x15}, + {0x3A9, 0x63}, + {0x3AA, 0x30}, + {0x3AB, 0x63}, + {0x9A5, 0x29}, + {0x9A6, 0x47}, + {0xF98, 0x85}, + {0xF99, 0x66}, +}; +static void mt6685_unlock(bool unlock) +{ + for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) + mt6685_write16(key_protect_setting[i].addr, + unlock ? key_protect_setting[i].val : 0); +} + +void mt6685_init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1); + assert(pmif_arb); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spi"); + + printk(BIOS_INFO, "[%s]CHIP ID = %#x\n", __func__, mt6685_read_field(0xb, 0xFF, 0)); +} + +void mt6685_init(void) +{ + mt6685_init_pmif_arb(); + mt6685_unlock(true); + mt6685_wdt_set(); + mt6685_init_setting(); + mt6685_unlock(false); + printk(BIOS_INFO, "[%s]TOP_RST_MISC = %#x\n", __func__, + mt6685_read_field(MT6685_TOP_RST_MISC, 0xFF, 0)); +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 7fe0889..73661bd 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -35,6 +35,7 @@ romstage-y += ../common/mt6316.c mt6316.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c +romstage-y += ../common/mt6685.c mt6685.c romstage-y += ../common/mtk_fsp.c romstage-y += mtk_pwrsel.c romstage-y += ../common/pmif_clk.c pmif_clk.c diff --git a/src/soc/mediatek/mt8196/mt6685.c b/src/soc/mediatek/mt8196/mt6685.c new file mode 100644 index 0000000..10ac231 --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6685.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <soc/mt6685.h> + +static const struct mt6685_setting init_setting[] = { + {0x18, 0x2, 0x2, 0}, + {0x1A, 0x1F, 0x1F, 0}, + {0x27, 0x10, 0x10, 0}, + {0x8A, 0x0, 0x1F, 0}, + {0x10B, 0x8, 0x8, 0}, + {0x11E, 0x1, 0x1, 0}, + {0x127, 0x2, 0x2, 0}, + {0x193, 0x1, 0x1, 0}, + {0x19C, 0x3, 0xF, 0}, + {0x389, 0x0, 0xFF, 0}, + {0x38A, 0x0, 0x7, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x418, 0x10, 0xF0, 0}, + {0x789, 0x6, 0x6, 0}, + {0x9B3, 0x0, 0x7F, 0}, + {0x9B4, 0x7E, 0x7E, 0}, + {0xF8C, 0x15, 0x15, 0}, + {0xF8D, 0x5, 0x5, 0}, + {0x1B0D, 0xF, 0xF, 0}, + {0x1B0E, 0x1, 0x1, 0}, + {0x1B0F, 0x0, 0x1, 0}, + {0x1B10, 0x7F, 0x7F, 0}, + {0x1B1A, 0x8, 0x8, 0}, + {0x1B89, 0x0, 0x80, 0}, + {0x1B8E, 0x40, 0x40, 0}, + {0x1B99, 0x0, 0x80, 0}, + {0x1B9E, 0x40, 0x40, 0}, + {0x1BA9, 0x0, 0x80, 0}, + {0x1BAE, 0x40, 0x40, 0}, + {0x1BB9, 0x0, 0x80, 0}, + {0x1BC9, 0x0, 0x80, 0}, + {0x1BD9, 0x0, 0x80, 0}, + {0x1C09, 0x0, 0x80, 0}, + {0x1C0B, 0x1, 0x5, 0}, + {0x1C0E, 0xC0, 0xC0, 0}, + {0x1C8E, 0x1, 0x1, 0}, + + /* Add UVLO 2.0 setting, also need to modify dts setting for main pmic */ + {0x7F1, 0x1, 0xF, 0}, + {0x9a3, 0xD, 0x1F, 0}, + {0x9b2, 0x80, 0x80, 0}, + {0xA8b, 0x4, 0x4, 0}, +}; + +static inline void write_field(const struct mt6685_setting *setting) +{ + mt6685_write_field(setting->addr, setting->val, setting->mask, setting->shift); +} + +void mt6685_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting); i++) + write_field(&init_setting[i]); +} diff --git a/src/soc/mediatek/mt8196/pmif_init.c b/src/soc/mediatek/mt8196/pmif_init.c index 0fda348..0baf720 100644 --- a/src/soc/mediatek/mt8196/pmif_init.c +++ b/src/soc/mediatek/mt8196/pmif_init.c @@ -20,6 +20,8 @@ .pmifid = PMIF_SPMI, .write = pmif_spmi_write, .read = pmif_spmi_read, + .write16 = pmif_spmi_write16, + .read16 = pmif_spmi_read16, .write_field = pmif_spmi_write_field, .read_field = pmif_spmi_read_field, .is_pmif_init_done = pmif_check_init_done, @@ -30,6 +32,8 @@ .pmifid = PMIF_SPMI, .write = pmif_spmi_write, .read = pmif_spmi_read, + .write16 = pmif_spmi_write16, + .read16 = pmif_spmi_read16, .write_field = pmif_spmi_write_field, .read_field = pmif_spmi_read_field, .is_pmif_init_done = pmif_check_init_done, @@ -40,6 +44,8 @@ .pmifid = PMIF_SPMI, .write = pmif_spmi_write, .read = pmif_spmi_read, + .write16 = pmif_spmi_write16, + .read16 = pmif_spmi_read16, .write_field = pmif_spmi_write_field, .read_field = pmif_spmi_read_field, .is_pmif_init_done = pmif_check_init_done, -- To view, visit https://review.coreboot.org/c/coreboot/+/85734?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I26ae4f416202f04a8030259c49e009b19a60712e Gerrit-Change-Number: 85734 Gerrit-PatchSet: 9 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: add in GLK related information
by Jared Mauch (Code Review) 28 Dec '24

28 Dec '24

Attention is currently required from: Jared Mauch, Pratikkumar V Prajapati. Hello Pratikkumar V Prajapati, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85747?usp=email to look at the new patch set (#2). Change subject: add in GLK related information ...................................................................... add in GLK related information Dell Wyse 5070 - Intel(R) Pentium(R) Silver J5005 CPU Change-id: I8086318431f0936cd4c6e1ed590e0fba8f0fbf5b --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85747/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85747?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8086318431f0936cd4c6e1ed590e0fba8f0fbf5b Gerrit-Change-Number: 85747 Gerrit-PatchSet: 2 Gerrit-Owner: Jared Mauch Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jared Mauch Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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[S] Change in coreboot[main]: mb/starlabs/starlite: Add smart battery variant
by Sean Rhodes (Code Review) 28 Dec '24

28 Dec '24

Sean Rhodes has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/85701?usp=email ) Change subject: mb/starlabs/starlite: Add smart battery variant ...................................................................... mb/starlabs/starlite: Add smart battery variant Add Kconfig options for `_SB`, the smart battery variant which is identical apart from a different EC which supports a Smart Battery instead of the CW2015. Change-Id: I1e04ea26ef597ce542a7348982d056fb55de0d22 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starlite_adl/Kconfig M src/mainboard/starlabs/starlite_adl/Kconfig.name 2 files changed, 19 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/85701/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85701?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e04ea26ef597ce542a7348982d056fb55de0d22 Gerrit-Change-Number: 85701 Gerrit-PatchSet: 5 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/inte/{adl,mtl}: Move ASPM helper functions to common
by Sean Rhodes (Code Review) 28 Dec '24

28 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83679?usp=email ) Change subject: soc/inte/{adl,mtl}: Move ASPM helper functions to common ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/block/aspm/aspm.c: https://review.coreboot.org/c/coreboot/+/83679/comment/169d6e74_61645c78?us… : PS3, Line 73: s_cfg->PcieRpEnableCpm[index] = CONFIG(PCIEXP_CLK_PM); : s_cfg->PcieRpAspm[index] = aspm_control_to_upd(rp_cfg->pcie_rp_aspm); : s_cfg->PcieRpL1Substates[index] = l1ss_control_to_upd(rp_cfg->PcieRpL1Substates); > Do you also want to use option API here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Gerrit-Change-Number: 83679 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Sat, 28 Dec 2024 20:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[L] Change in coreboot[main]: soc/inte/{adl,mtl}: Move ASPM helper functions to common
by Sean Rhodes (Code Review) 28 Dec '24

28 Dec '24

Attention is currently required from: Sean Rhodes. Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83679?usp=email ) Change subject: soc/inte/{adl,mtl}: Move ASPM helper functions to common ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Gerrit-Change-Number: 83679 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sat, 28 Dec 2024 20:12:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Add workaround for FSP bug
by Patrick Rudolph (Code Review) 28 Dec '24

28 Dec '24

Attention is currently required from: Jérémy Compostella. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85789?usp=email ) Change subject: cpu/x86/64bit/mode_switch: Add workaround for FSP bug ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I am curious. […] Probably broken since 2018 (not sure which FSPs are using more recent EDK2), but only visible when x86_64 coreboot installs a new IDT by calling `exception_init()` and then calls the x86_32 FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Sat, 28 Dec 2024 19:49:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer
by Jan Philipp Groß (Code Review) 28 Dec '24

28 Dec '24

Attention is currently required from: Nicholas Chin. Jan Philipp Groß has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/85790?usp=email ) Change subject: util/find_usbdebug: Fix lsusb -t parsing for usbutils v016 and newer ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffa1238b995d387d6e51459f85ae96da52a5c0ff Gerrit-Change-Number: 85790 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 28 Dec 2024 16:03:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: cbfstool: Add hash to more than one region
by Bao Zheng (Code Review) 28 Dec '24

28 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/85468?usp=email ) Change subject: cbfstool: Add hash to more than one region ...................................................................... Patch Set 12: (1 comment) Patchset: PS1: > Can you explain what you're trying to do here? What is `COREBOOTB`? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85468?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f9a5baa2699468380b942b3bdc104cab78adf5f Gerrit-Change-Number: 85468 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 28 Dec 2024 14:26:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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