coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if a USB PD charger is attached
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85743?usp=email ) Change subject: ec/google/chromeec: Add API to check if a USB PD charger is attached ...................................................................... ec/google/chromeec: Add API to check if a USB PD charger is attached This change introduces a new API, `google_chromeec_is_usb_pd_attached()` which checks the current status of the USB-C port and returns whether a USB Power Delivery (PD) charger is currently connected. This API is useful for determining if the system is currently being powered by a PD charger. BUG=b:377798581 TEST=Able to read the PD status correctly while booting google/fatcat. Change-Id: I47c934ee8a7563d4ba5124bff5613e61dd66e923 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85743 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index af5c235..4c1bbe7 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -966,6 +966,25 @@ return 0; } +/* + * This API checks the current status of the USB-C port and returns + * whether a USB Power Delivery (PD) charger is currently connected. + */ +bool google_chromeec_is_usb_pd_attached(void) +{ + const struct ec_params_usb_pd_power_info params = { + .port = PD_POWER_CHARGING_PORT, + }; + struct ec_response_usb_pd_power_info resp = {}; + int rv; + + rv = ec_cmd_usb_pd_power_info(PLAT_EC, &params, &resp); + if (rv != 0) + return false; + + return resp.type == USB_CHG_TYPE_PD; +} + int google_chromeec_override_dedicated_charger_limit(uint16_t current_lim, uint16_t voltage_lim) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 31c7671..cdea70f 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -137,6 +137,9 @@ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, uint16_t *current_max, uint16_t *voltage_max); +/* Check if a USB Power Delivery (PD) charger is attached */ +bool google_chromeec_is_usb_pd_attached(void); + /* * Set max current and voltage of a dedicated charger. * -- To view, visit https://review.coreboot.org/c/coreboot/+/85743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47c934ee8a7563d4ba5124bff5613e61dd66e923 Gerrit-Change-Number: 85743 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: device/pci_ids: Rename and add PCI IDs for Intel Touch Controller
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Jérémy Compostella. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85644?usp=email ) Change subject: device/pci_ids: Rename and add PCI IDs for Intel Touch Controller ...................................................................... Patch Set 1: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/85644/comment/60a07708_87a685bf?us… : PS1, Line 4948: #define PCI_DID_INTEL_MTL_THC0_INTEL 0x7e48 : #define PCI_DID_INTEL_MTL_THC0_SPI 0x7e49 : #define PCI_DID_INTEL_MTL_THC1_INTEL 0x7e4a : #define PCI_DID_INTEL_MTL_THC1_SPI 0x7e4b can you please split this CL into two ? 1. for renaming MTL to add `_INTEL` postfix 2. Adding PTL PCI IDs -- To view, visit https://review.coreboot.org/c/coreboot/+/85644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60d9bec60d0578bd5a12a4df25248b7ae58539d6 Gerrit-Change-Number: 85644 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 02:37:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: looking at MTL IOE die I/O registers and PTL SOC die I/O registers for TBT, I don't see any difference in the register definitions to justify the CL. Can you please help me to understand which bit-field inside TBT.LCAP register you are referring here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 02:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Add FSP-I and FSP-O
by Jincheng Li (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Andrey Petrov, Christian Walter, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Subrata Banik. Jincheng Li has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/83113?usp=email ) Change subject: drivers/intel/fsp2_0: Add FSP-I and FSP-O ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53ed1eb45eac89d72ae472fe2b41d64c5eecb182 Gerrit-Change-Number: 83113 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 02:15:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/asus/p8x7x-series: Streamline DT PCIe configs
by Keith Hui (Code Review) 30 Dec '24

30 Dec '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85797?usp=email ) Change subject: mb/asus/p8x7x-series: Streamline DT PCIe configs ...................................................................... mb/asus/p8x7x-series: Streamline DT PCIe configs All variants in this family have PCIe root port 1 enabled. Turn it on in devicetree.cb and remove lines in overridetree.cb for devices that remain off. TEST=Timeless binaries did not change across entire family. Change-Id: I4feb88a78f72952bed049505073aed00d2120df3 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb M src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb 5 files changed, 1 insertion(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/85797/1 diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index e9b97bc..7719344f 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -37,7 +37,7 @@ device ref ehci2 on end device ref hda on end - device ref pcie_rp1 off end + device ref pcie_rp1 on end # PCIe x4 slot, by various names device ref pcie_rp2 off end device ref pcie_rp3 off end device ref pcie_rp4 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 1e8d807..c0d38b6 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -24,13 +24,9 @@ { 1, 0, 6 } }" device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # PCIEX1_1 device ref pcie_rp6 on end # 82574 GbE #1 device ref pcie_rp7 on end # 82574 GbE #2 - device ref pcie_rp8 off end device ref pci_bridge on end device ref lpc on chip superio/nuvoton/nct6776 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index 1389304..f1decba 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -22,9 +22,6 @@ }" register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # AR8161 GbE NIC device ref pcie_rp6 on end # ASM1083 PCI Bridge device ref pcie_rp7 on end # PCIEX1_1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index 50aed1b..c88b260 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -23,16 +23,12 @@ }" device ref pcie_rp1 on end # PCIe x4 slot - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # PCIe x1 slot device ref pcie_rp6 on # RTL8111F GbE NIC subsystemid 0x1849 0x1e1a device pci 00.0 on end # make onboard end device ref pcie_rp7 on end # PCI slot via ASM1083 - device ref pcie_rp8 off end device ref lpc on chip superio/nuvoton/nct6779d device pnp 2e.1 off end # Parallel diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 66bc5bb..4d8124a 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -24,9 +24,6 @@ register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on end # RTL8111 GbE NIC device ref pcie_rp6 on end # ASM1083 PCI Bridge device ref pcie_rp7 on end # PCIEX1_1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85797?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4feb88a78f72952bed049505073aed00d2120df3 Gerrit-Change-Number: 85797 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: Documentation/mb/asus/p8z77-m: Document latest test results
by Keith Hui (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Angel Pons, Kevin Keijzer, Nicholas Chin, Paul Menzel. Hello Angel Pons, Nicholas Chin, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78204?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: Documentation/mb/asus/p8z77-m: Document latest test results ...................................................................... Documentation/mb/asus/p8z77-m: Document latest test results Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M Documentation/mainboard/asus/p8z77-m.md 1 file changed, 63 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/78204/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/78204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f4c9268cd272caa83267be3f71d4a2022c26a1c Gerrit-Change-Number: 78204 Gerrit-PatchSet: 4 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons. Riku Viitanen has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... Patch Set 7: (4 comments) File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/85793/comment/e1f46220_903ca757?us… : PS5, Line 196: #if CONFIG(MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE) > Is it necessary to guard this with preprocessor? Done https://review.coreboot.org/c/coreboot/+/85793/comment/ac600da2_baeea55e?us… : PS5, Line 197: VOLTAGE_MIN > What about DDR3L (1. […] Paranoid me thinks it could cause unstability in the IMC. Also all DDR3(L) DIMMs are supposed to work at 1.5V. Hmm, I was able to find online some datasheets of DDR3L modules that have a 1.35V XMP profile (though they also had the same timings in SPD??). As the code currently stands, we would reject an XMP profile in that case and use SPD instead. Maybe I should change the comparison: dimm->voltage != ctrl->voltage to dimm->voltage > ctrl->voltage in the loop below. Since the first (only voltage checking) round eliminates the possibility of overvolting already. https://review.coreboot.org/c/coreboot/+/85793/comment/e3eff057_84055801?us… : PS5, Line 197: #define VOLTAGE_MIN 1500 : #define VOLTAGE_MAX 1650 : #define VOLTAGE_DEFAULT 1500 > I would suggest adding the units as a suffix to the macro names, e.g. […] Acknowledged https://review.coreboot.org/c/coreboot/+/85793/comment/7535c40e_da1de785?us… : PS5, Line 211: spd_xmp_decode_ddr3(&dimm, spd[spd_slot], : DDR3_XMP_PROFILE_1); : if (dimm.dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { : /* Non-XMP DIMM. Use default voltage since : * every DIMM is supposed to work with it */ : printram("Non-XMP DIMM detected. Defaulting to %imV.\n", : VOLTAGE_DEFAULT); : return VOLTAGE_DEFAULT; : : } else if (dimm.voltage > VOLTAGE_MAX) { : printram("XMP requested voltage too high!\n"); : if (voltage != 0) : voltage = MIN(voltage, VOLTAGE_MAX); : else : voltage = VOLTAGE_MAX; : : } else if (dimm.voltage < VOLTAGE_MIN) { : printram("XMP requested voltage too low!?\n"); : return VOLTAGE_MIN; : : } else { : voltage = MAX(voltage, dimm.voltage); : } > This decodes the XMP SPD a second time, is it necessary? At first I tried to integrate voltage selection into the loop in dram_find_spds_ddr3, but that became messy very quickly. Consider what happens if we have mixed modules, where the first one we read supports faster XMP timings at 1.65V, but some module that's scanned after it doesn't tolerate voltages that high. My code reverts to 1.5V in that case. The XMP DIMM would then be running at speeds to fast for the actual voltage it gets. Maybe there's a method to only parse the voltage quickly. -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 7 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 29 Dec 2024 23:13:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Angel Pons (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Riku Viitanen. Angel Pons has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 3: (7 comments) Commit Message: PS3: Which OSes did you test? File src/mainboard/asrock/z77_extreme4/Kconfig: https://review.coreboot.org/c/coreboot/+/85772/comment/0afe1f37_f47980c6?us… : PS3, Line 19: select SUPERIO_NUVOTON_NCT6776 Try selecting some Kconfig for Nuvoton that ends in `_COM_A`. Might help make serial work. File src/mainboard/asrock/z77_extreme4/cmos.layout: https://review.coreboot.org/c/coreboot/+/85772/comment/42d6acb4_8aded20c?us… : PS3, Line 27: Sandy Bridge MRC Scrambler Seed values : 896 32 r 0 mrc_scrambler_seed : 928 32 r 0 mrc_scrambler_seed_s3 : 960 16 r 0 mrc_scrambler_seed_chk Only used with MRC.bin and this board is native-only. Please remove. File src/mainboard/asrock/z77_extreme4/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85772/comment/98a61117_82590f8f?us… : PS3, Line 16: # bifurcated from peg10 It is, by design. The PCIe lanes can't come from any other place. File src/mainboard/asrock/z77_extreme4/dsdt.asl: https://review.coreboot.org/c/coreboot/+/85772/comment/54f734aa_a3596d43?us… : PS3, Line 10: // OEM revision Looks like autoport copypasta, please remove if so https://review.coreboot.org/c/coreboot/+/85772/comment/cb70678e_cce6de1e?us… : PS3, Line 21: Scope (\_SB) { : Device (PCI0) : { : #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> : #include <southbridge/intel/bd82x6x/acpi/pch.asl> : } : } nit: Old autoport versions used to emit this incoherent use of tabs and brace location. Would be nice to fix. File src/mainboard/asrock/z77_extreme4/mainboard.c: PS3: Was VBIOS tested? -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Sun, 29 Dec 2024 22:47:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Angel Pons (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Riku Viitanen. Angel Pons has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... Patch Set 5: (5 comments) File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/85793/comment/302b0607_a507fb21?us… : PS5, Line 196: #if CONFIG(MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE) Is it necessary to guard this with preprocessor? https://review.coreboot.org/c/coreboot/+/85793/comment/011e1714_b092ceb2?us… : PS5, Line 197: VOLTAGE_MIN What about DDR3L (1.35 V)? https://review.coreboot.org/c/coreboot/+/85793/comment/46aa5189_bbb9c67a?us… : PS5, Line 197: #define VOLTAGE_MIN 1500 : #define VOLTAGE_MAX 1650 : #define VOLTAGE_DEFAULT 1500 I would suggest adding the units as a suffix to the macro names, e.g. `VOLTAGE_MIN_MV` https://review.coreboot.org/c/coreboot/+/85793/comment/07eb6fbb_a932f5c0?us… : PS5, Line 211: spd_xmp_decode_ddr3(&dimm, spd[spd_slot], : DDR3_XMP_PROFILE_1); : if (dimm.dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { : /* Non-XMP DIMM. Use default voltage since : * every DIMM is supposed to work with it */ : printram("Non-XMP DIMM detected. Defaulting to %imV.\n", : VOLTAGE_DEFAULT); : return VOLTAGE_DEFAULT; : : } else if (dimm.voltage > VOLTAGE_MAX) { : printram("XMP requested voltage too high!\n"); : if (voltage != 0) : voltage = MIN(voltage, VOLTAGE_MAX); : else : voltage = VOLTAGE_MAX; : : } else if (dimm.voltage < VOLTAGE_MIN) { : printram("XMP requested voltage too low!?\n"); : return VOLTAGE_MIN; : : } else { : voltage = MAX(voltage, dimm.voltage); : } This decodes the XMP SPD a second time, is it necessary? File src/northbridge/intel/sandybridge/sandybridge.h: https://review.coreboot.org/c/coreboot/+/85793/comment/a065c212_0e834d17?us… : PS5, Line 66: optional Not exactly optional, it has to be implemented if `MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE` is enabled, and is never called otherwise. -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 5 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Sun, 29 Dec 2024 22:40:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#7). Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 72 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 7 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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