coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85802?usp=email ) Change subject: mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger ...................................................................... mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger This change modifies the touchpad interrupt configuration to use edge-triggered interrupts instead of level-triggered interrupts. This is necessary to ensure that the touchpad interrupt is properly detected by the AP w/o seeing interrupt flood. BUG=b:376019577 TEST=Verified that the touchpad works smoothly with this change. Change-Id: Ida0dfe10963a979c5e977133149d97799a76e3b3 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/85802/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 6ac0755..87f9097 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -440,7 +440,7 @@ /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* GPP_A13: TCH_PAD_INT_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_A13, NONE, PWROK, EDGE_SINGLE, INVERT), }; static const struct pad_config touchpad_i2c_disable_pads[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85802?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida0dfe10963a979c5e977133149d97799a76e3b3 Gerrit-Change-Number: 85802 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85774?usp=email ) Change subject: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85774/comment/70ed2d4e_82e300a2?us… : PS3, Line 20: > Please send a separate patch to fix the indent. OK, please check 85801. thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 08:42:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Fix indentation in Makefile.mk
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85801?usp=email ) Change subject: soc/mediatek/mt8196: Fix indentation in Makefile.mk ...................................................................... soc/mediatek/mt8196: Fix indentation in Makefile.mk TEST=Build pass BUG=b:317009620 Change-Id: Id70988da2505ed8940f4c55f3483c6bc2c33ff1c Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/85801/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index a63a22f..d7b0df8 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -17,7 +17,7 @@ bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += mminfra.c bootblock-y += ../common/mmu_operations.c -bootblock-y += mtcmos.c +bootblock-y += mtcmos.c bootblock-y += mtk_cksys.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += tracker.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85801?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id70988da2505ed8940f4c55f3483c6bc2c33ff1c Gerrit-Change-Number: 85801 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/emulation/spike-riscv: Define default DRAM_SIZE to avoid crash whe...
by Joel Bueno (Code Review) 30 Dec '24

30 Dec '24

Joel Bueno has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85800?usp=email ) Change subject: mb/emulation/spike-riscv: Define default DRAM_SIZE to avoid crash when probing memory ...................................................................... mb/emulation/spike-riscv: Define default DRAM_SIZE to avoid crash when probing memory For RISC-V emulated targets (using SOC_UCB_RISCV), the top of memory is calculated in cbmem_top_chipset() by calling probe_ramsize() with a size of CONFIG_DRAM_SIZE_MB. This causes an access fault when the size is set to zero, which is the case for Spike. This does not happen on qemu because, for that target, we parse the FDT instead of manually probing memory. TEST=boot verified on SPIKE-RISCV Fixes: 2fa8caba507a ("lib/ramdetect: Limit probe size to function argument") on SPIKE-RISCV Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Signed-off-by: joel.bueno <joel.bueno(a)openchip.com> --- M src/mainboard/emulation/spike-riscv/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85800/1 diff --git a/src/mainboard/emulation/spike-riscv/Kconfig b/src/mainboard/emulation/spike-riscv/Kconfig index 5160125..7bf7ed0 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig +++ b/src/mainboard/emulation/spike-riscv/Kconfig @@ -25,4 +25,8 @@ int default 1 +config DRAM_SIZE_MB + int + default 1024 + endif # BOARD_EMULATION_SPIKE_RISCV -- To view, visit https://review.coreboot.org/c/coreboot/+/85800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I567103bcd956b10fab64c5e63018315924ec0d2b Gerrit-Change-Number: 85800 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Bueno <joel.bueno(a)openchip.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Configure Acoustic noise mitigation
by Eric Lai (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Rui Zhou. Eric Lai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85798?usp=email ) Change subject: mb/google/nissa/var/rull: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7f60f1248c6b46f4f9bac1731be4f0396766ae2 Gerrit-Change-Number: 85798 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 07:53:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Configure Acoustic noise mitigation
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85798?usp=email ) Change subject: mb/google/nissa/var/rull: Configure Acoustic noise mitigation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7f60f1248c6b46f4f9bac1731be4f0396766ae2 Gerrit-Change-Number: 85798 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 30 Dec 2024 07:26:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
by Hope Wang (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Hope Wang has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85751?usp=email ) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD ...................................................................... Patch Set 8: (1 comment) File src/soc/mediatek/mt8196/pmif_spmi.c: https://review.coreboot.org/c/coreboot/+/85751/comment/72fee0c0_e44d9a38?us… : PS1, Line 177: if (dev->slvid == SPMI_SLAVE_6) { : setbits32p(SPMI_SCL_P_PD_ADDR, : BIT(SPMI_SCL_P_PD_OFFSET) | BIT(SPMI_SDA_P_PD_OFFSET)); : printk(BIOS_INFO, "%s, Set SoC PD for SPMI-P SCL/SDA, [0x%x] = 0x%x\n", : __func__, SPMI_SCL_P_PD_ADDR, read32p(SPMI_SCL_P_PD_ADDR)); : } > If so, we can do that in `pmif_spmi_iocfg`. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 07:07:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add delay in pmif_spmi.c
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85799?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Add delay in pmif_spmi.c ...................................................................... soc/mediatek/mt8196: Add delay in pmif_spmi.c The initialization process of SPMI requires a certain amount of time (0.5ms) to ensure all components are correctly configured and synchronized. Otherwise, if the SPMI calibration fails, it will result in the non-serial firmware failing to boot. TEST=Build pass, non-serial firmware boot ok. BUG=b:341054056 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85799/1 diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c index 326c247..e780d2f 100644 --- a/src/soc/mediatek/mt8196/pmif_spmi.c +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ #include <console/console.h> +#include <delay.h> #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> @@ -285,6 +286,7 @@ { write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN); write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN); + udelay(500); printk(BIOS_INFO, "%s done\n", __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85751?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD ...................................................................... soc/mediatek/mt8196: Set SPMI-P SCL/SDA SoC PD Configure the SCL and SDA of the SPMI-P to Pull-Down mode on MT8196 SoC, it is done only once during the SPMI read check to fix SPMI clock calibration failure. TEST=Build pass BUG=b:361174333 Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/pmif_spmi.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85751/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbf8ed8e31850ca81c823db1b25bde4a83a48c4f Gerrit-Change-Number: 85751 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: Configure Acoustic noise mitigation
by Rui Zhou (Code Review) 30 Dec '24

30 Dec '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85798?usp=email ) Change subject: mb/google/nissa/var/rull: Configure Acoustic noise mitigation ...................................................................... mb/google/nissa/var/rull: Configure Acoustic noise mitigation Follow the power team’s recommendation: - Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:380384127 TEST=built firmware and verified by power team, and noise pass Change-Id: Ib7f60f1248c6b46f4f9bac1731be4f0396766ae2 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85798/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d4b773a..d6262de 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -12,6 +12,13 @@ end chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "sagv" = "SaGv_Enabled" # EMMC Tx CMD Delay -- To view, visit https://review.coreboot.org/c/coreboot/+/85798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7f60f1248c6b46f4f9bac1731be4f0396766ae2 Gerrit-Change-Number: 85798 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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coreboot-gerrit December 2024