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Hello Elyes Haouas, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
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Change subject: soc/mediatek/mt8196: Fix indentation in Makefile.mk
......................................................................
soc/mediatek/mt8196: Fix indentation in Makefile.mk
TEST=Build pass
BUG=b:317009620
Change-Id: Id70988da2505ed8940f4c55f3483c6bc2c33ff1c
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/85801/2
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Change subject: mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:
https://review.coreboot.org/c/coreboot/+/85802/comment/ad99b7b4_6a621b29?us… :
PS1, Line 443: EDGE_SINGLE
> > Does this not contradict with devicetree irq configuration ```ACPI_IRQ_WAKE_LEVEL_LOW```? […]
Acknowledged
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Change subject: mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:
https://review.coreboot.org/c/coreboot/+/85802/comment/d78a64d7_8b2fbb25?us… :
PS1, Line 443: EDGE_SINGLE
> Does this not contradict with devicetree irq configuration ```ACPI_IRQ_WAKE_LEVEL_LOW```?
looks like as per ACPI and I2C HID spec, the ACPI configuration has to be level
https://github.com/coreboot/coreboot/blob/main/src/drivers/i2c/hid/hid.c#L82
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85772?usp=email
to look at the new patch set (#5).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/asrock: Add Z77 Extreme4
......................................................................
mb/asrock: Add Z77 Extreme4
New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".
Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.16.3 booting to Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIe x16 slots, including automatic bifurcation (x8/x8)
- PCI slots
- Suspend and resume (S3)
- Dr. Debug (shows post codes during boot)
Untested:
- Intel VBIOS
- USB headers
- Other fans
- LED headers
- eSATA, SPDIF
- PCIe x1 slots
Not working:
- Serial port
Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com>
---
A src/mainboard/asrock/z77_extreme4/Kconfig
A src/mainboard/asrock/z77_extreme4/Kconfig.name
A src/mainboard/asrock/z77_extreme4/Makefile.mk
A src/mainboard/asrock/z77_extreme4/acpi/ec.asl
A src/mainboard/asrock/z77_extreme4/acpi/platform.asl
A src/mainboard/asrock/z77_extreme4/acpi/superio.asl
A src/mainboard/asrock/z77_extreme4/board_info.txt
A src/mainboard/asrock/z77_extreme4/cmos.default
A src/mainboard/asrock/z77_extreme4/cmos.layout
A src/mainboard/asrock/z77_extreme4/data.vbt
A src/mainboard/asrock/z77_extreme4/devicetree.cb
A src/mainboard/asrock/z77_extreme4/dsdt.asl
A src/mainboard/asrock/z77_extreme4/early_init.c
A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads
A src/mainboard/asrock/z77_extreme4/gpio.c
A src/mainboard/asrock/z77_extreme4/hda_verb.c
A src/mainboard/asrock/z77_extreme4/mainboard.c
17 files changed, 647 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/5
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Change subject: mb/google/fatcat/var/fatcat: Add touchpad wake source
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/asrock: Add Z77 Extreme4
......................................................................
Patch Set 4:
(5 comments)
File src/mainboard/asrock/z77_extreme4/cmos.layout:
https://review.coreboot.org/c/coreboot/+/85772/comment/0360f251_ea4c6067?us… :
PS3, Line 27: Sandy Bridge MRC Scrambler Seed values
: 896 32 r 0 mrc_scrambler_seed
: 928 32 r 0 mrc_scrambler_seed_s3
: 960 16 r 0 mrc_scrambler_seed_chk
> Only used with MRC.bin and this board is native-only. Please remove.
Done
File src/mainboard/asrock/z77_extreme4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/85772/comment/2020bd96_aa6ba64f?us… :
PS3, Line 16: # bifurcated from peg10
> It is, by design. The PCIe lanes can't come from any other place.
Done
File src/mainboard/asrock/z77_extreme4/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/85772/comment/7c8429f0_14fcc52a?us… :
PS3, Line 10: // OEM revision
> Looks like autoport copypasta, please remove if so
Done
https://review.coreboot.org/c/coreboot/+/85772/comment/230d6858_eda2f287?us… :
PS3, Line 21: Scope (\_SB) {
: Device (PCI0)
: {
: #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
: #include <southbridge/intel/bd82x6x/acpi/pch.asl>
: }
: }
> nit: Old autoport versions used to emit this incoherent use of tabs and brace location. […]
Done
File src/mainboard/asrock/z77_extreme4/mainboard.c:
PS3:
> Was VBIOS tested?
no
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Change subject: mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:
https://review.coreboot.org/c/coreboot/+/85802/comment/1942bdd7_0e650a1a?us… :
PS1, Line 443: EDGE_SINGLE
Does this not contradict with devicetree irq configuration ```ACPI_IRQ_WAKE_LEVEL_LOW```?
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85772?usp=email
to look at the new patch set (#4).
Change subject: mb/asrock: Add Z77 Extreme4
......................................................................
mb/asrock: Add Z77 Extreme4
New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".
Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.16.3 booting to Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIe x16 slots, including automatic bifurcation (x8/x8)
- PCI slots
- Suspend and resume (S3)
- Dr. Debug (shows post codes during boot)
Untested:
- Intel VBIOS
- USB headers
- Other fans
- LED headers
- eSATA, SPDIF
- PCIe x1 slots
Not working:
- Serial port
Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com>
---
A src/mainboard/asrock/z77_extreme4/Kconfig
A src/mainboard/asrock/z77_extreme4/Kconfig.name
A src/mainboard/asrock/z77_extreme4/Makefile.mk
A src/mainboard/asrock/z77_extreme4/acpi/ec.asl
A src/mainboard/asrock/z77_extreme4/acpi/platform.asl
A src/mainboard/asrock/z77_extreme4/acpi/superio.asl
A src/mainboard/asrock/z77_extreme4/board_info.txt
A src/mainboard/asrock/z77_extreme4/cmos.default
A src/mainboard/asrock/z77_extreme4/cmos.layout
A src/mainboard/asrock/z77_extreme4/data.vbt
A src/mainboard/asrock/z77_extreme4/devicetree.cb
A src/mainboard/asrock/z77_extreme4/dsdt.asl
A src/mainboard/asrock/z77_extreme4/early_init.c
A src/mainboard/asrock/z77_extreme4/gma-mainboard.ads
A src/mainboard/asrock/z77_extreme4/gpio.c
A src/mainboard/asrock/z77_extreme4/hda_verb.c
A src/mainboard/asrock/z77_extreme4/mainboard.c
17 files changed, 651 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/85772/4
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