coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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3018 discussions

[L] Change in coreboot[main]: mb/asrock: Add Z77 Extreme4
by Angel Pons (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Riku Viitanen. Angel Pons has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85772?usp=email ) Change subject: mb/asrock: Add Z77 Extreme4 ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/mainboard/asrock/z77_extreme4/mainboard.c: PS3: > no Okay, I generally prefer removing this but I think there's no problem in keeping it for now. If I ever get bored I'll move this to devicetree or something. -- To view, visit https://review.coreboot.org/c/coreboot/+/85772?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Gerrit-Change-Number: 85772 Gerrit-PatchSet: 5 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 12:01:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Riku Viitanen <riku.viitanen(a)protonmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add delay in pmif_spmi.c
by Yidi Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email ) Change subject: soc/mediatek/mt8196: Add delay in pmif_spmi.c ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85799/comment/64531c1b_792ad86c?us… : PS1, Line 18: remove the blank line https://review.coreboot.org/c/coreboot/+/85799/comment/69b8801a_b2947190?us… : PS1, Line 19: Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 > `Duplicate signature` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 11:59:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource
by Angel Pons (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Benjamin Doron, Patrick Rudolph, Paul Menzel. Angel Pons has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/79228?usp=email ) Change subject: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I106c1730787a88c03719acfb8a80e7b840b29997 Gerrit-Change-Number: 79228 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 30 Dec 2024 11:59:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Enable x86_64
by Angel Pons (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85805?usp=email ) Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ...................................................................... Patch Set 1: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85805/comment/4ad1bc9b_dcf5b859?us… : PS1, Line 13: Add support for x86_64 coreboot and confirm that all supported boards > `'occurence' may be misspelled - perhaps 'occurrence'?` Also, make it plural: occurrences File src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/85805/comment/c69f6fc0_f5fcb956?us… : PS1, Line 513: VOID *SetupStructPtr; Was this removed because it's undocumented? https://review.coreboot.org/c/coreboot/+/85805/comment/5ae651ee_2f1953c2?us… : PS1, Line 272: UINT32 GpioTablePtr; Silly idea: ``` #define PTR_32B(type) UINT32 ``` ```suggestion PTR_32B(UPD_GPIO_INIT_CONFIG) GpioTablePtr; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Gerrit-Change-Number: 85805 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 11:58:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Fix indentation in Makefile.mk
by Yidi Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85801?usp=email ) Change subject: soc/mediatek/mt8196: Fix indentation in Makefile.mk ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85801?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id70988da2505ed8940f4c55f3483c6bc2c33ff1c Gerrit-Change-Number: 85801 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 11:50:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
by Yidi Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85774?usp=email ) Change subject: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 11:50:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: arch/x86/mmu: Port armv8 MMU to x86_64
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Arthur Heymans, Benjamin Doron, Christian Walter, Felix Held, Julius Werner, Subrata Banik. Patrick Rudolph has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/79161?usp=email ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: Created https://review.coreboot.org/c/coreboot/+/85806 as a simple alternative. -- To view, visit https://review.coreboot.org/c/coreboot/+/79161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 79161 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 30 Dec 2024 11:24:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85806?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... cpu/x86/64bit: Install extended page tables in BSS On Intel 14nm Xeon-SP every processor support 1TiB of DRAM. Since MMIO is mapped above usable DRAM, the default page tables in RODATA are not sufficient to cover the high MMIO space. This prevents the use of coreboot's ramstage drivers as they cannot access the PCI BARs residing in high MMIO. Introduce a simple page table generator that installs extended page tables in BSS to access up to 48bit of the virtual address space. TEST: Booted on ibm/sbp1 and accessed a PCI BAR above 512GiB without crash. Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/mmu.c M src/cpu/x86/Kconfig M src/soc/intel/xeon_sp/Kconfig 4 files changed, 212 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85806/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/ebg/soc_xhci: Check if BAR is reachable
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Make use of PCI driver for xHCI
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85808?usp=email ) Change subject: soc/intel/xeon_sp: Make use of PCI driver for xHCI ...................................................................... soc/intel/xeon_sp: Make use of PCI driver for xHCI Instead of misusing the chip final handler move the EGB specific code into the ebg folder and make use of the existing PCI driver for xHCI by adding the correct PCI ID. This allows to decouple the 10nm Xeon-SP from EBG and use the northbridge code with a LBG PCH. Currently no mainboard uses the code, but it should be used as FSP always applies the default USB configuration for ArcherCity. Change-Id: Ie3968da4c95febbb270e1dbbea8b8b1b8fc1e96d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/xeon_sp/ebg/include/soc/xhci.h M src/soc/intel/xeon_sp/ebg/soc_xhci.c M src/soc/intel/xeon_sp/include/soc/ramstage.h M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/ramstage.c 7 files changed, 17 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/85808/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 60ed807..a7a31b2d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4538,6 +4538,7 @@ #define PCI_DID_INTEL_PTL_U_H_XHCI 0xe37d #define PCI_DID_INTEL_PTL_U_H_TCSS_XHCI 0xe331 #define PCI_DID_INTEL_SNR_XHCI 0x18d0 +#define PCI_DID_INTEL_EBG_XHCI 0x1bcd /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 6d35f39..da6396c 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -153,6 +153,7 @@ PCI_DID_INTEL_ADP_M_XHCI, PCI_DID_INTEL_RPP_S_XHCI, PCI_DID_INTEL_SNR_XHCI, + PCI_DID_INTEL_EBG_XHCI, 0 }; diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h index 005a8e1..c6e9116 100644 --- a/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h +++ b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h @@ -47,7 +47,7 @@ uint32_t port; }; +void mainboard_override_usb_oc(void); void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins); -void lock_oc_cfg(bool lock); #endif /* _XHCI_H_ */ diff --git a/src/soc/intel/xeon_sp/ebg/soc_xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c index f8aa37b..2d3d09c 100644 --- a/src/soc/intel/xeon_sp/ebg/soc_xhci.c +++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <device/pci.h> +#include <intelblocks/xhci.h> #include <soc/pch_pci_devs.h> #include <soc/xhci.h> #include <types.h> @@ -33,7 +34,7 @@ write32(mbar + config[i].pin, config[i].port); } -void lock_oc_cfg(bool lock) +static void lock_oc_cfg(bool lock) { uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2); @@ -43,3 +44,15 @@ cfg &= ~(OCCFGDONE); pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg); } + +__weak void mainboard_override_usb_oc(void) +{ + /* Default weak implementation */ +} + +void soc_xhci_init(struct device *dev) +{ + lock_oc_cfg(false); + mainboard_override_usb_oc(); + lock_oc_cfg(true); +} diff --git a/src/soc/intel/xeon_sp/include/soc/ramstage.h b/src/soc/intel/xeon_sp/include/soc/ramstage.h index 91dd114..9cc4ac2 100644 --- a/src/soc/intel/xeon_sp/include/soc/ramstage.h +++ b/src/soc/intel/xeon_sp/include/soc/ramstage.h @@ -13,7 +13,6 @@ void mainboard_override_fsp_gpio(void); /* lock or unlock community B and D pads after FSP-S */ void lock_gpio(bool lock); -void mainboard_override_usb_oc(void); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 9fd747d..f1e9de2 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -71,10 +71,6 @@ p2sb_hide(); - /* Accessing xHCI CSR needs to be done after PCI enumeration. */ - lock_oc_cfg(false); - mainboard_override_usb_oc(); - lock_oc_cfg(true); /* Disable CPU Crashlog to avoid conflict between CPU Crashlog and BMC ACD. */ disable_cpu_crashlog(); } diff --git a/src/soc/intel/xeon_sp/spr/ramstage.c b/src/soc/intel/xeon_sp/spr/ramstage.c index 6ac3efe..e1ede29 100644 --- a/src/soc/intel/xeon_sp/spr/ramstage.c +++ b/src/soc/intel/xeon_sp/spr/ramstage.c @@ -23,8 +23,3 @@ { /* Default weak implementation */ } - -__weak void mainboard_override_usb_oc(void) -{ - /* Default weak implementation */ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/85808?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie3968da4c95febbb270e1dbbea8b8b1b8fc1e96d Gerrit-Change-Number: 85808 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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coreboot-gerrit December 2024