coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: device: Fix debug print
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85807?usp=email ) Change subject: device: Fix debug print ...................................................................... device: Fix debug print Increase the char buffer size to fit all characters that are printed into it by the snprintf() call below. Change-Id: Ib153e1d02a08b2551dad5b51c4c88bf0bb606af3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/device_util.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/85807/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 8d111b6..fc585a0 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -547,7 +547,7 @@ void report_resource_stored(struct device *dev, const struct resource *resource, const char *comment) { - char buf[10]; + char buf[16]; unsigned long long base, end; if (!(resource->flags & IORESOURCE_STORED)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib153e1d02a08b2551dad5b51c4c88bf0bb606af3 Gerrit-Change-Number: 85807 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[M] Change in coreboot[main]: cpu/x86/64bit: Install extended page tables in BSS
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Shuo Liu, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email ) Change subject: cpu/x86/64bit: Install extended page tables in BSS ...................................................................... cpu/x86/64bit: Install extended page tables in BSS On Intel 14nm Xeon-SP every processor support 1TiB of DRAM. Since MMIO is mapped above usable DRAM, the default page tables in RODATA are not sufficient to cover the high MMIO space. This prevents the use of coreboot's ramstage drivers as they cannot access the PCI BARs residing in high MMIO. Introduce a simple page table generator that installs extended page tables in BSS to access up to 48bit of the virtual address space. TEST: Booted on ibm/sbp1 and accessed a PCI BAR above 512GiB without crash. Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/Makefile.mk A src/cpu/x86/64bit/mmu.c M src/cpu/x86/Kconfig M src/soc/intel/xeon_sp/Kconfig 4 files changed, 212 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85806/1 diff --git a/src/cpu/x86/64bit/Makefile.mk b/src/cpu/x86/64bit/Makefile.mk index 8ce3665..8ce9757 100644 --- a/src/cpu/x86/64bit/Makefile.mk +++ b/src/cpu/x86/64bit/Makefile.mk @@ -11,6 +11,8 @@ all_x86-y += $(PAGETABLE_SRC) +ramstage-$(CONFIG_CPU_USE_EXTENDED_PAGE_TABLES_IN_BSS) += mmu.c + # Add --defsym=_start=0 to suppress a linker warning. $(objcbfs)/pt: $(dir)/$(PAGETABLE_SRC) $(obj)/config.h $(CC_bootblock) $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) -o $@.tmp $< -Wl,--section-start=.rodata=$(CONFIG_ARCH_X86_64_PGTBL_LOC),--defsym=_start=0 -fuse-ld=bfd diff --git a/src/cpu/x86/64bit/mmu.c b/src/cpu/x86/64bit/mmu.c new file mode 100644 index 0000000..1dd89dd --- /dev/null +++ b/src/cpu/x86/64bit/mmu.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootstate.h> +#include <cpu/cpu.h> +#include <cpu/x86/cr.h> +#include <console/console.h> +#include <device/device.h> +#include <device/resource.h> +#include <stdint.h> +#include <stdio.h> + +#define _PRES (1ULL << 0) +#define _RW (1ULL << 1) +#define _US (1ULL << 2) +#define _A (1ULL << 5) +#define _D (1ULL << 6) +#define _PS (1ULL << 7) +#define _GEN_DIR(a) (_PRES + _RW + _US + _A + (uintptr_t)(a)) +#define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A + _D + (uintptr_t)(a)) +#define BITS_PER_VA 48 + +/* Page table to map the whole address space. See Note below. */ +#define PTE_ENTRIES (1 + 1 + 512) +static uint8_t __aligned(4096) page_tables[PTE_ENTRIES * 4096]; + +static inline bool cpu_supports_1gb_hugepage(void) +{ + static bool checked, supports; + if (checked) + return supports; + + /* check if CPU supports 1GB hugepages */ + if (cpu_cpuid_extended_level() >= 0x80000001) + supports = !!(cpuid_edx(0x80000001) & (1 << 26)); + checked = true; + + return supports; +} + +/** + * @brief Identity map more of the address space. + * + * The assumption is that on old platforms (that do not support 1GB + * PT), only mobile and client platforms are supported, and that those platforms + * used DDR3 or older DRAM, thus 512GiB of memory are sufficient for + * coreboot's ramstage. + * + * When 1GB PT are supported it maps 48 bits (the maximum 4-LVL paging supports), + * when 1GB PT aren't supported it maps 40 bits of the address space (512GiB). + * + * Runtime generated to keep ramstage size at minimum. + */ +static void mmu_enable(void) +{ + uint64_t *const p4mle = (uint64_t *const)&page_tables[0]; + uint64_t *const pdpt = (uint64_t *const)&page_tables[4096]; + uint64_t *const pdt = (uint64_t *const)&page_tables[4096 * 2]; + + if (cpu_supports_1gb_hugepage()) { + const uintptr_t max_addr = 1ULL * GiB * 512ULL * 512ULL; + const uint64_t incr = 1ULL * GiB; + + /* Build P4MLE */ + for (int i = 0; i < 512; i++) + p4mle[i] = _GEN_DIR(&pdpt[i * 512]); + + /* Build PDPT */ + uint64_t *page_table_ptr = pdpt; + for (uintptr_t addr = 0; addr < max_addr; addr+=incr, page_table_ptr++) + *page_table_ptr = _GEN_PAGE(addr); + } else { + const uintptr_t max_addr = 2ULL * MiB * 512ULL * 512ULL; + const uint64_t incr = 2ULL * MiB; + + /* Build P4MLE */ + p4mle[0] = _GEN_DIR(&pdpt[0]); + + /* Build PDPT */ + for (int i = 0; i < 512; i++) + pdpt[i] = _GEN_DIR(&pdt[i * 512]); + + /* Build PDT */ + uint64_t *page_table_ptr = pdt; + for (uintptr_t addr = 0; addr < max_addr; addr+=incr, page_table_ptr++) + *page_table_ptr = _GEN_PAGE(addr); + } + + /* Load the new page table address */ + write_cr3((uintptr_t)page_tables); +} + +/* + * Reports resources above the given limit. + */ +static void mmu_report_limit(void *gp, struct device *dev, struct resource *res) +{ + unsigned long long base, end; + char buf[16]; + + if (!res->size) + return; + const uint64_t *max_addr = (uint64_t *)gp; + + assert(((res->base + res->size) < *max_addr) && + (res->base < *max_addr) && + (res->size < *max_addr)); + + if (((res->base + res->size) < *max_addr) && + (res->base < *max_addr) && + (res->size < *max_addr)) + return; + + base = res->base; + end = resource_end(res); + buf[0] = '\0'; + + if (dev->downstream && (res->flags & IORESOURCE_PCI_BRIDGE)) { + snprintf(buf, sizeof(buf), + "seg %02x bus %02x ", dev->downstream->segment_group, + dev->downstream->secondary); + } + + printk(BIOS_ERR, "%s %02lx <- [0x%016llx - 0x%016llx] size 0x%08llx " + "gran 0x%02x %s%s\n", dev_path(dev), res->index, + base, end, res->size, res->gran, buf, + resource_type(res)); +} + +/* + * Find the upper limit of assigned memory resources. + */ +static void mmu_find_limit(void *gp, struct device *dev, struct resource *res) +{ + if (!res->size) + return; + uint64_t *limit = (uint64_t *)gp; + + if (*limit < (res->base + res->size)) + *limit = (res->base + res->size); +} + +/* + * Returns the (virtual) size of the currently mapped address space when using + * page tables in RODATA. + */ +static inline uint64_t mmu_default_map_size(void) +{ + if (CONFIG(NEED_SMALL_2MB_PAGE_TABLES)) + return 4ULL * GiB; + else + return 512ULL * GiB; +} + +/* + * Returns the (virtual) size of the mapped address space when using + * new page tables in BSS. + */ +static inline int mmu_max_virt_address_bits(void) +{ + /* Using 512 4K pages limits the usable address space */ + if (cpu_supports_1gb_hugepage()) + return BITS_PER_VA; + else + return 40; +} + +/* + * Installs new page tables in BSS. + */ +static void mmu_setup_all_resources(void *unused) +{ + uint64_t limit = 0; + + /* Get upper limit of active memory address space (DRAM / MMIO) */ + search_global_resources(IORESOURCE_MEM | IORESOURCE_ASSIGNED, + IORESOURCE_MEM | IORESOURCE_ASSIGNED, + mmu_find_limit, &limit); + limit = ALIGN_UP(limit, GiB); + + printk(BIOS_DEBUG, "MMU: Upper MEM limit is 0x%llx\n", limit); + printk(BIOS_DEBUG, "MMU: New page tables are%s required\n", + (limit > mmu_default_map_size()) ? "" : "n't"); + + uint64_t addr_limit = 1ULL << mmu_max_virt_address_bits(); + + /* Report conflicts when active address space is too big */ + assert(limit <= addr_limit); + if (limit > addr_limit) { + printk(BIOS_ERR, "MMU: New page tables in BSS won't cover active address space!\n"); + printk(BIOS_ERR, "MMU: Conflicting resources:\n"); + search_global_resources(IORESOURCE_MEM | IORESOURCE_ASSIGNED, + IORESOURCE_MEM | IORESOURCE_ASSIGNED, + mmu_report_limit, &addr_limit); + } + + mmu_enable(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, mmu_setup_all_resources, NULL); \ No newline at end of file diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 828c0f9..9c2678b 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -152,6 +152,16 @@ bool default n +config CPU_USE_EXTENDED_PAGE_TABLES_IN_BSS + bool + default n + depends on ARCH_RAMSTAGE_X86_64 + help + Set up extended pages tables in BSS that cover a bigger address space + than the default page tables in RODATA, installed after BS_DEV_RESOURCES + to make all memory resources reachable by the CPU. + Increases BSS by additional 2.1MiB. + config NEED_SMALL_2MB_PAGE_TABLES bool default n diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index f61de56..883015e 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -13,6 +13,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select CPU_USE_EXTENDED_PAGE_TABLES_IN_BSS select FSP_CAR select FSP_M_XIP select FSP_COMPRESS_FSP_S_LZ4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifab50975e0382a1f5c27b55bca1dbbb66b37ba3a Gerrit-Change-Number: 85806 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: cpu/x86/64bit/mode_switch: Add workaround for FSP bug
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Jérémy Compostella. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85789?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: cpu/x86/64bit/mode_switch: Add workaround for FSP bug ...................................................................... cpu/x86/64bit/mode_switch: Add workaround for FSP bug FSP is able to backup and restore the bootloader IDT on entry/exit. Even though it sets up it's own IDT, FSP checks the bootloader IDT size and deadloops without warning if it's too big. On x86_64 coreboot the IDT is naturally bigger than on x86_32 and thus x86_32 FSP might die on entry. To workaround this issue do: * Backup and restore the IDT in protected_mode_call_wrapper * Load zero IDT in protected mode before jumping to function TEST: Can boot on SPR FSP (x86_32) using x86_64 coreboot with exceptions in romstage enabled. Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/mode_switch.S 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/85789/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56367d8153aa10a9b1bcaa5ffde8ebe202e8c00c Gerrit-Change-Number: 85789 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: cpu/x86/64bit: Back up/restore CR3 on mode switch
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Arthur Heymans, Felix Held, Jérémy Compostella, Patrick Rudolph, Paul Menzel. Hello Arthur Heymans, Felix Held, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82164?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Code-Review+2 by Arthur Heymans, Verified-1 by build bot (Jenkins) Change subject: cpu/x86/64bit: Back up/restore CR3 on mode switch ...................................................................... cpu/x86/64bit: Back up/restore CR3 on mode switch Store CR3 on stack and restore it when returning from protected mode call, since the stage might have set up different page tables than the default ones linked into all stages. Tested: intel/archercity still boots to payload in x86_64. Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/mode_switch.S 1 file changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/82164/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82164?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If94a24925994ac9599be24f6454ea28d02ff0c67 Gerrit-Change-Number: 82164 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Paul Menzel. Patrick Rudolph has uploaded a new patch set (#3) to the change originally created by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/79228?usp=email ) Change subject: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource ...................................................................... mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource Select CPU_USE_EXTENDED_PAGE_TABLES_IN_BSS and thus switch to page tables in BSS. With page tables in cbmem it's no longer necessary to reserve parts of the DRAM previously used for page tables. Change-Id: I106c1730787a88c03719acfb8a80e7b840b29997 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-q35/mainboard.c 3 files changed, 2 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/79228/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79228?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I106c1730787a88c03719acfb8a80e7b840b29997 Gerrit-Change-Number: 79228 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Fix indentation in Makefile.mk
by Elyes Haouas (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Elyes Haouas has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85801?usp=email ) Change subject: soc/mediatek/mt8196: Fix indentation in Makefile.mk ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85801?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id70988da2505ed8940f4c55f3483c6bc2c33ff1c Gerrit-Change-Number: 85801 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 10:44:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Enable x86_64
by Patrick Rudolph (Code Review) 30 Dec '24

30 Dec '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85805?usp=email ) Change subject: soc/intel/xeon_sp/skx: Enable x86_64 ...................................................................... soc/intel/xeon_sp/skx: Enable x86_64 On Xeon Skylake-SP with dual sockets the platforms make use of 46bit of the address space. Most of the PCI BARs reside in high MMIO, not reachable by x86_32 coreboot. Add support for x86_64 coreboot and confirm that all supported boards are booting without errors. This is done by converting all occurence of VOID * to UINT32 to make sure that FSP UPDs do not change when pointers are 8byte wide. TEST: Booted on ocp/tiogapass to Linux. No errors were observed. Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/tiogapass/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h 3 files changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85805/1 diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 283d5f1..cae6815 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -17,6 +17,9 @@ static void oem_update_iio(FSPM_UPD *mupd) { + UPD_IIO_BIFURCATION_DATA_ENTRY *entry = + (void *)(uintptr_t)mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr; + /* Read GPIO to decide IIO bifurcation at run-time. */ int slot_config0 = gpio_get(GPP_C15); int slot_config1 = gpio_get(GPP_C16); @@ -25,25 +28,24 @@ reading the GPIO expander PCA9555 via SMBUS, and then configure the bifurcation accordingly is left for future work. */ if (!slot_config0 && slot_config1) - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable[Skt0_Iou0].Bifurcation - = IIO_BIFURCATE_xxx8xxx8; + entry[Skt0_Iou0].Bifurcation = IIO_BIFURCATE_xxx8xxx8; } static void mainboard_config_iio(FSPM_UPD *mupd) { memcpy(iio_table_buf, tp_iio_bifur_table, sizeof(tp_iio_bifur_table)); - mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable = - (UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; + mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTablePtr = + (uintptr_t)(UPD_IIO_BIFURCATION_DATA_ENTRY *)iio_table_buf; mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_bifur_table); - mupd->FspmConfig.IioPciConfig.ConfigurationTable = - (UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; + mupd->FspmConfig.IioPciConfig.ConfigurationTablePtr = + (uintptr_t)(UPD_PCI_PORT_CONFIG *)tp_iio_pci_port_skt0; mupd->FspmConfig.IioPciConfig.NumberOfEntries = ARRAY_SIZE(tp_iio_pci_port_skt0); - mupd->FspmConfig.PchPciConfig.PciPortConfig = - (UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; + mupd->FspmConfig.PchPciConfig.PciPortConfigPtr = + (uintptr_t)(UPD_PCH_PCIE_PORT *)tp_pch_pci_port_skt0; mupd->FspmConfig.PchPciConfig.NumberOfEntries = ARRAY_SIZE(tp_pch_pci_port_skt0); @@ -62,7 +64,7 @@ mainboard_config_iio(mupd); /* do not configure GPIO controller inside FSP-M */ - mupd->FspmConfig.GpioConfig.GpioTable = NULL; + mupd->FspmConfig.GpioConfig.GpioTablePtr = 0; mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; } diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 970dba3..acbc31f 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -6,6 +6,8 @@ select PLATFORM_USES_FSP2_0 select NO_FSP_TEMP_RAM_EXIT select UDK_202005_BINDING + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT help Intel Skylake-SP support diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h index f81e218..8306106 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h @@ -261,7 +261,7 @@ /** GPIOTABLE_CONFIG: GpioTable - Base Address of the Gpio Table declared by the - bootloader. + bootloader. Pointer to UPD_GPIO_INIT_CONFIG. Default: NULL NumberofEntries - Number of Entries in the GPIO Table provided Default: 0 @@ -269,7 +269,7 @@ configuration using default GPIO_INIT_CONFIG tables **/ typedef struct { - UPD_GPIO_INIT_CONFIG *GpioTable; + UINT32 GpioTablePtr; UINT32 NumberOfEntries; } GPIOTABLE_CONFIG; @@ -293,7 +293,7 @@ /** IIOBIFURCATION_CONFIG: IIoBifurcationTable - Base Address of the IIO Bifurcation table - declared by the bootloader + declared by the bootloader. Pointer to UPD_IIO_BIFURCATION_DATA_ENTRY. Default: NULL NumberofEntries - Number of Entries in the IIO Bifurcation Table Default: 0 @@ -301,7 +301,7 @@ bifurcation using default IIO_BIFURCATION_DATA_ENTRY tables **/ typedef struct { - UPD_IIO_BIFURCATION_DATA_ENTRY *IIoBifurcationTable; + UINT32 IIoBifurcationTablePtr; UINT32 NumberOfEntries; } IIOBIFURCATION_CONFIG; @@ -381,12 +381,11 @@ /** PCIEPORT_CONFIG: PciePortConfiguration - Pointer to an array of PCIe port configuration structures - as declared above + as declared above. Pointer to UPD_PCI_PORT_CONFIG. NumberOfEntries - Number of elements in the PciePortConfiguration Array **/ typedef struct { - UPD_PCI_PORT_CONFIG *ConfigurationTable; - + UINT32 ConfigurationTablePtr; UINT16 NumberOfEntries; } IIOPCIPORT_CONFIG; @@ -412,11 +411,12 @@ /** IIORESOURCE_CONFIG: - ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array + ResourceConfigTable - Pointer to an Iio Stack Resource Configuration Structure Array. + Pointer to UPD_IIO_STACK_RESOURCE_CONFIG. NumberOfEntries - Number of Entries in the Iio Stack Resource Configuration Array **/ typedef struct { - UPD_IIO_STACK_RESOURCE_CONFIG *ResourceTable; + UINT32 ResourceTablePtr; UINT16 NumberOfEntries; } IIORESOURCE_CONFIG; @@ -436,6 +436,7 @@ /** PCHPCIPORT_CONFIG: PciPortConfig - Pointer to an array of PCH PCI Ports to be configured + Pointer to UPD_PCH_PCIE_PORT. RootPortFunctionSwapping - Disable root port swapping based on device connection status PciePllSsc - Specifies the Pcie Pll Spread Spectrum Percentage @@ -446,7 +447,7 @@ NumberOfEntries - Number of entries in the PCH PCI Port configuration **/ typedef struct { - UPD_PCH_PCIE_PORT *PciPortConfig; + UINT32 PciPortConfigPtr; UINT8 RootPortFunctionSwapping; UINT8 PciePllSsc; UINT16 NumberOfEntries; @@ -507,12 +508,7 @@ **/ UINT8 BoardId; - UINT8 reserved2[24]; - -/** Offset 0x00C2 **/ - VOID *SetupStructPtr; - - UINT8 reserved3[20]; + UINT8 reserved2[48]; /** Offset 0x00DA - IioPciConfig IIO Pci Port Config Struct. Defaults: All pointers are NULL. All values are set to zero. @@ -529,7 +525,7 @@ **/ IIORESOURCE_CONFIG IioResourceConfig; - UINT8 reserved4[3]; + UINT8 reserved3[3]; /** Offset 0x00F1 - DCI Enable Enable / Disable DCI -- To view, visit https://review.coreboot.org/c/coreboot/+/85805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adac99e7600a708b596fd74b00669f4cb4e041b Gerrit-Change-Number: 85805 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85774?usp=email ) Change subject: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks ...................................................................... Patch Set 5: (3 comments) File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85774/comment/ed214ef0_c9493979?us… : PS3, Line 137: PERI_MASK_IDLE_TO_CKSYS = IO_PHYS + 0x06630270, > I think this file is supposed to have only base registers, not all the registers we need. […] Done File src/soc/mediatek/mt8196/mtk_cksys.c: PS3: > No need to add mtk_ to the file name. We don't use that prefix for other files. […] Done https://review.coreboot.org/c/coreboot/+/85774/comment/81ba9c3e_c406145b?us… : PS3, Line 6: mtk_cksys > Same for the header file name. Can we use cksys. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 10:32:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85774?usp=email to look at the new patch set (#5). Change subject: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks ...................................................................... soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks In MT8196, CKSYS achieves power efficiency by dynamically turning the clocks on or off based on the status provided by PERI. TEST=Build pass, boot log: mtk_cksys_init = 0x1 BUG=b:317009620 Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/cksys.c A src/soc/mediatek/mt8196/include/soc/cksys.h 4 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85774/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
by Jarried Lin (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85774?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks ...................................................................... soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks In MT8196, CKSYS achieves power efficiency by dynamically turning the clocks on or off based on the status provided by PERI. TEST=Build pass, boot log: mtk_cksys_init = 0x1 BUG=b:317009620 Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/85774/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85774?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70f710f068d7d882037691930a90c83adaab15d2 Gerrit-Change-Number: 85774 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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