coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... soc/intel/alderlake: Add function to force disable memory channels Add a function `mem_init_override_channel_mask` to disable memory channels based on given bitmap where each bit represents a memory channel. A set bit will disable corresponding memory channel. Variants can override this bitmap by selecting `ENFORCE_MEM_CHANNEL_DISABLE` and implementing `mb_get_channel_disable_mask` to return the bitmap. BUG=b:379311559 TEST=Make sure that channel mask is applied correctly. Lotso without any channel mask: ``` lotso-rev0 ~ # dmidecode -t 17 | grep -E "(Locator: C|Size)" Size: 2 GB Locator: Channel-0-DIMM-0 Size: 2 GB Locator: Channel-1-DIMM-0 Size: 2 GB Locator: Channel-2-DIMM-0 Size: 2 GB Locator: Channel-3-DIMM-0 Size: 2 GB Locator: Channel-0-DIMM-0 Size: 2 GB Locator: Channel-1-DIMM-0 Size: 2 GB Locator: Channel-2-DIMM-0 Size: 2 GB Locator: Channel-3-DIMM-0 lotso-rev0 ~ # dmidecode -t 17 | grep Size | wc -l 8 ``` Lotso with channel 2 & 3 masked: ``` lotso-rev0 ~ # dmidecode -t 17 | grep -E "(Locator: C|Size)" Size: 2 GB Locator: Channel-0-DIMM-0 Size: 2 GB Locator: Channel-1-DIMM-0 Size: 2 GB Locator: Channel-0-DIMM-0 Size: 2 GB Locator: Channel-1-DIMM-0 lotso-rev0 ~ # dmidecode -t 17 | grep Size | wc -l 4 ``` Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85529 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c 3 files changed, 54 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Subrata Banik: Looks good to me, approved Jayvik Desai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f6e9182..15f347f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -441,6 +441,14 @@ int default 16 +config ENFORCE_MEM_CHANNEL_DISABLE + bool + default n + help + Select this option to disable certain memory channels on demand. If + selected, A function named mb_get_channel_disable_mask() must be + implemented to return the bit map of memory channels to disable. + config ALDERLAKE_ENABLE_SOC_WORKAROUND bool default y diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 1d9eaf9..97fb77c 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -116,4 +116,16 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated); +/* + * This function is expected to return a bitmap of memory channels to + * disable. A set bit will disable corresponding memory channel. + * Variants can override this bitmap by selecting + * `ENFORCE_MEM_CHANNEL_DISABLE` and implementing this function. + */ +#if CONFIG(ENFORCE_MEM_CHANNEL_DISABLE) +uint8_t mb_get_channel_disable_mask(void); +#else +static inline uint8_t mb_get_channel_disable_mask(void) { return 0; } +#endif + #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 35c3252..6b3143e 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -233,6 +233,39 @@ mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); } +/* + * A memory channel will be disabled if corresponding bit in + * ch_disable_mask is set. + */ +static void mem_init_override_channel_mask(FSP_M_CONFIG *mem_cfg) +{ + uint8_t *disable_channel_upds[MRC_CHANNELS] = { + &mem_cfg->DisableMc0Ch0, + &mem_cfg->DisableMc0Ch1, + &mem_cfg->DisableMc0Ch2, + &mem_cfg->DisableMc0Ch3, + &mem_cfg->DisableMc1Ch0, + &mem_cfg->DisableMc1Ch1, + &mem_cfg->DisableMc1Ch2, + &mem_cfg->DisableMc1Ch3, + }; + + uint8_t ch_disable_mask = mb_get_channel_disable_mask(); + if (ch_disable_mask == 0) + return; + + /* Mc0Ch0 cannot be disabled */ + if (ch_disable_mask & BIT(0)) { + printk(BIOS_ERR, "Cannot disable the first memory channel (Mc0Ch0).\n"); + return; + } + + for (size_t ch = 0; ch < MRC_CHANNELS; ch++) { + if (ch_disable_mask & BIT(ch)) + *disable_channel_upds[ch] = 1; + } +} + void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { @@ -283,6 +316,7 @@ mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, &data); mem_init_spd_upds(mem_cfg, &data); + mem_init_override_channel_mask(mem_cfg); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 12 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F
by Eric Lai (Code Review) 30 Dec '24

30 Dec '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85775?usp=email ) Change subject: mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F ...................................................................... mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F Change the ram_id to 2 for MT62F2G32D4DS-020 WT:F based on the hardware schematic MB_SCH_1224A. BUG=b:372395010 TEST=Run part_id_gen tool and check the generated files. Change-Id: Ia486d892fca0ed2a9e3e869b97b43af617ef17ac Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85775 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk M src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt M src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt 3 files changed, 4 insertions(+), 3 deletions(-) Approvals: Dtrain Hsu: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk index 310ef55..b18b9c4 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/francka/memory/Makefile.mk @@ -5,4 +5,5 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 0(0b0000) -SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 1(0b0001) Parts = MT62F2G32D4DS-020 WT:F +SPD_SOURCES += spd/lp5/set-0/spd-empty.hex # ID = 1(0b0001) +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 2(0b0010) Parts = MT62F2G32D4DS-020 WT:F diff --git a/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt index dcb790a..3d31714 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt +++ b/src/mainboard/google/fatcat/variants/francka/memory/dram_id.generated.txt @@ -4,4 +4,4 @@ # util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/francka/memory src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt DRAM Part Name ID to assign -MT62F2G32D4DS-020 WT:F 1 (0001) +MT62F2G32D4DS-020 WT:F 2 (0010) diff --git a/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt index 9b80035..09d6e0b 100644 --- a/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt +++ b/src/mainboard/google/fatcat/variants/francka/memory/mem_parts_used.txt @@ -9,4 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name -MT62F2G32D4DS-020 WT:F,1 +MT62F2G32D4DS-020 WT:F,2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia486d892fca0ed2a9e3e869b97b43af617ef17ac Gerrit-Change-Number: 85775 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F
by Eric Lai (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Amanda Hwang, Pranava Y N. Eric Lai has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/85775?usp=email ) Change subject: mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia486d892fca0ed2a9e3e869b97b43af617ef17ac Gerrit-Change-Number: 85775 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 05:42:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: soc/inte/{adl,mtl}: Move ASPM helper functions to common
by Kapil Porwal (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83679?usp=email ) Change subject: soc/inte/{adl,mtl}: Move ASPM helper functions to common ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/83679/comment/29bc180e_8cd56ca4?us… : PS9, Line 154: SOC_INTEL_CPU_ROOT_PORTS ```suggestion config HAS_INTEL_CPU_ROOT_PORTS ``` WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/83679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Gerrit-Change-Number: 83679 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 05:14:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Add FSP-I and FSP-O
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Andrey Petrov, Christian Walter, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar. Subrata Banik has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/83113?usp=email ) Change subject: drivers/intel/fsp2_0: Add FSP-I and FSP-O ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/83113/comment/970f1e6a_a713cd8e?us… : PS3, Line 13: #define FSP_HDR_ATTRIB_FSPI 4 : #define FSP_HDR_ATTRIB_FSPO 8 not sure if you wish to guard these macros against FSP 2.4 kconfig. Ideally adding new FSP APIs demands the major version change at FSP side but looks like Intel decided to used FSP 2.4 spec to include new APIs. -- To view, visit https://review.coreboot.org/c/coreboot/+/83113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53ed1eb45eac89d72ae472fe2b41d64c5eecb182 Gerrit-Change-Number: 83113 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 30 Dec 2024 04:31:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... mb/google/fatcat: Limit Power Limit when battery is missing Ensure the board can boot by limiting the power limits if the battery is missing. This addresses the factory use case. BUG=b:377798581 TEST=See power limit override log message when the battery is missing on fatcat board Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85146 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index e4c98dd..37ba330 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -32,6 +32,7 @@ select MAINBOARD_HAS_TPM2 select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD select SOC_INTEL_PANTHERLAKE_U_H diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk index be05cd4..47123cd 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only romstage-y += memory.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c new file mode 100644 index 0000000..4b9cfd2 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <ec/google/chromeec/ec.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + */ +const struct cpu_tdp_power_limits power_optimized_limits[] = { + { + .mch_id = PCI_DID_INTEL_PTL_H_ID_1, + .cpu_tdp = 25, + .power_limits_index = PTL_H_1_CORE, + .pl1_min_power = 10000, + .pl1_max_power = 25000, + .pl2_min_power = 50000, + .pl2_max_power = 50000, + .pl4_power = 50000 /* TODO: needs fine tuning */ + }, +}; + +void baseboard_devtree_update(void) +{ + /* Don't optimize the power limit if booting with barrel attached */ + if (google_chromeec_is_barrel_charger_present()) + return; + + if (!google_chromeec_is_battery_present()) + variant_update_cpu_power_limits(power_optimized_limits, + ARRAY_SIZE(power_optimized_limits)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 20 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Dinesh Gehlot (Code Review) 30 Dec '24

30 Dec '24

Attention is currently required from: Jamie Ryu, Jérémy Compostella, Paul Menzel, Subrata Banik. Dinesh Gehlot has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 19 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 30 Dec 2024 04:17:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: ec/google/chromeec: Add function to detect barrel charger
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85765?usp=email ) Change subject: ec/google/chromeec: Add function to detect barrel charger ...................................................................... ec/google/chromeec: Add function to detect barrel charger This commit introduces a new function, google_chromeec_is_barrel_charger_present(), which checks if a barrel charger is present. The function uses the following logic to determine if a barrel charger is present: - If both a barrel charger and USB-C PD are present, then the barrel charger takes precedence over USB-C PD. As a result, google_chromeec_is_usb_pd_attached() will return false. This logic can be used to deterministically say if a barrel charger is present even when both a barrel charger and USB-C PD are attached. - If an AC charger is detected and USB-C PD is not present, then a barrel charger must be present. This change allows the EC to accurately detect the presence of a barrel charger, even when a USB-C PD charger is also attached. BUG=b:377798581 TEST=Able to read the charger status correctly while booting google/fatcat. Experiment #1: - USB-C PD Attached = yes - Barrel Attached = No - Charger Detected = Yes ``` fatcat-rev257 ~ # cbmem -c | grep -5 "ac_charger_present" [INFO ] ac_charger_present: yes [INFO ] usb_pd_present: yes [INFO ] baseboard_devtree_update: Barrel Absent ``` Experiment #2: - USB-C PD Attached = No - Barrel Attached = Yes - Charger Detected = Yes ``` [INFO ] ac_charger_present: yes [INFO ] usb_pd_present: no [INFO ] baseboard_devtree_update: Barrel Present ``` Experiment #3: - USB-C PD Attached = Yes - Barrel Attached = Yes - Charger Detected = Yes ``` [INFO ] ac_charger_present: yes [INFO ] usb_pd_present: no [INFO ] baseboard_devtree_update: Barrel Present ``` Experiment #4: - USB-C PD Attached = No - Barrel Attached = No - Charger Detected = No ``` [INFO ] ac_charger_present: no [INFO ] usb_pd_present: no [INFO ] baseboard_devtree_update: Barrel Absent ``` Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85765 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 1ee242b..2e8961f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1002,6 +1002,30 @@ return false; } +/* + * Using below scenarios to conclude if device has a barrel charger attached. + * +-----------+-----------------+------------------+---------------------------------+ + * | Scenarios | Charger Present | USB-C PD Present | Conclusion: Barrel Present ? | + * +-----------+-----------------+------------------+---------------------------------+ + * | #1 | Yes | Yes | Non Conclusive (comments below) | + * | #2 | No | Yes | Not possible | + * | #3 | Yes | No | Must be barrel charger | + * | #4 | No | No | Barrel not present | + * +-----------+-----------------+------------------+---------------------------------+ + */ +bool google_chromeec_is_barrel_charger_present(void) +{ + /* + * If both the barrel charger and USB-C PD are connected, the barrel charger takes + * precedence over USB-C PD. This means google_chromeec_is_usb_pd_attached() + * will return false in such a scenario. + * + * This behavior allows us to reliably detect the presence of a barrel + * charger, even when a USB-C PD charger is also connected. + */ + return google_chromeec_is_charger_present() && !google_chromeec_is_usb_pd_attached(); +} + int google_chromeec_override_dedicated_charger_limit(uint16_t current_lim, uint16_t voltage_lim) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index a50c311..b11b7a8 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -148,6 +148,14 @@ */ bool google_chromeec_is_charger_present(void); +/** + * Check if barrel charger is present. + * + * @return true: if the barrel charger is present + * false: if the barrel charger is not present + */ +bool google_chromeec_is_barrel_charger_present(void); + /* * Set max current and voltage of a dedicated charger. * -- To view, visit https://review.coreboot.org/c/coreboot/+/85765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9644f0dec057f95bb0a22cdc18edc1a0234ee3a9 Gerrit-Change-Number: 85765 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if battery is critically low
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85759?usp=email ) Change subject: ec/google/chromeec: Add API to check if battery is critically low ...................................................................... ec/google/chromeec: Add API to check if battery is critically low This patch adds a new API `google_chromeec_is_below_critical_threshold() ` to check if the battery level is below the critical threshold. The API uses the existing `ec_cmd_battery_get_dynamic()` command to retrieve the battery flags and checks the `EC_BATT_FLAG_LEVEL_CRITICAL` flag to determine if the battery level is critical. This API can be used by other components to query the battery critical status and take necessary actions, for example, while the system is booting with low battery fuel with and/or without an AC charger attached. This addresses the need to implement a low battery charger icon and detect when the system is booting with low battery fuel. The existing `google_chromeec_is_battery_present_and_above_critical_threshold()` API is not suitable for this purpose because any negative decision (like battery not present and/or battery is critically low) implemented around this existing API will also render the lower battery indicator when the system is booting into battery cut-off mode. Ideally, we do not wish to render any icon and simply allow boot to the OS during system battery cut-off boot. BUG=b:377798581 TEST=Able to read the battery status correctly while booting google/fatcat. Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85759 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Kapil Porwal: Looks good to me, but someone else must approve diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 8c80a3f..1ee242b 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1614,6 +1614,22 @@ return false; } +bool google_chromeec_is_below_critical_threshold(void) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) == 0) { + /* Check if battery LEVEL_CRITICAL is set */ + if (resp.flags & EC_BATT_FLAG_LEVEL_CRITICAL) + return true; + } + + return false; +} + bool google_chromeec_is_battery_present(void) { struct ec_params_battery_dynamic_info params = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index afb1485..a50c311 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -448,6 +448,14 @@ bool google_chromeec_is_battery_present_and_above_critical_threshold(void); /** + * Check if battery level is below critical threshold. + * + * @return true: if the battery level is below critical threshold + * false: any the above conditions is not true + */ +bool google_chromeec_is_below_critical_threshold(void); + +/** * Check if battery is present. * * @return true: if the battery is present -- To view, visit https://review.coreboot.org/c/coreboot/+/85759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1fc1df374fb4c663becc371c69b285d8b9957ff Gerrit-Change-Number: 85759 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: ec/google/chromeec: Add API to check if charger is present
by Subrata Banik (Code Review) 30 Dec '24

30 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85758?usp=email ) Change subject: ec/google/chromeec: Add API to check if charger is present ...................................................................... ec/google/chromeec: Add API to check if charger is present This patch introduces a new API, `google_chromeec_is_charger_present()`, to determine if a charger is connected. The API leverages the existing `ec_cmd_battery_get_dynamic()` command to retrieve battery flags and checks the `EC_BATT_FLAG_AC_PRESENT` flag to ascertain charger presence. Other components can leverage this API to query the charger status, which is particularly useful for distinguishing between barrel chargers and USB-C chargers after relying on the `google_chromeec_is_usb_pd_attached()` API. BUG=b:377798581 TEST=Able to read the charger status (w/ barrel and/or w/ USB-PD) correctly while booting google/fatcat. Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85758 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 25 insertions(+), 0 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, but someone else must approve diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 4c1bbe7..8c80a3f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -985,6 +985,23 @@ return resp.type == USB_CHG_TYPE_PD; } +/* This API checks if charger is present. */ +bool google_chromeec_is_charger_present(void) +{ + struct ec_params_battery_dynamic_info params = { + .index = 0, + }; + struct ec_response_battery_dynamic_info resp; + + if (ec_cmd_battery_get_dynamic(PLAT_EC, &params, &resp) == 0) { + /* Check if AC charger is present */ + if (resp.flags & EC_BATT_FLAG_AC_PRESENT) + return true; + } + + return false; +} + int google_chromeec_override_dedicated_charger_limit(uint16_t current_lim, uint16_t voltage_lim) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index cdea70f..afb1485 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -140,6 +140,14 @@ /* Check if a USB Power Delivery (PD) charger is attached */ bool google_chromeec_is_usb_pd_attached(void); +/** + * Check if charger is present. + * + * @return true: if the charger is present + * false: if the charger is not present + */ +bool google_chromeec_is_charger_present(void); + /* * Set max current and voltage of a dedicated charger. * -- To view, visit https://review.coreboot.org/c/coreboot/+/85758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iadf81400f71a51c093f71fe995cacc107c50c7af Gerrit-Change-Number: 85758 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024