coreboot-gerrit December 2024

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#3). Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 78 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 3 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85793?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 78 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 2 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 29 Dec '24

29 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76582?usp=email to look at the new patch set (#11). Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... ec/starlabs/merlin: Adjust the EC code to read values from CMOS This is in preparation to store options in EFI variable store, rather that option. However, some still need to stay in CMOS. Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c 2 files changed, 141 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76582/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 11 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: ec/starlabs/merlin/nuvoton: Remove the call to initialise the keyboard
by Sean Rhodes (Code Review) 29 Dec '24

29 Dec '24

Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85794?usp=email ) Change subject: ec/starlabs/merlin/nuvoton: Remove the call to initialise the keyboard ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I947d5d2f7512cc910963054dfbe6b5dc0f00462a Gerrit-Change-Number: 85794 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Sun, 29 Dec 2024 20:58:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/asrock: Add Z87 Extreme4 (Haswell)
by Jan Philipp Groß (Code Review) 29 Dec '24

29 Dec '24

Attention is currently required from: Angel Pons, Nicholas Chin. Hello Angel Pons, Nicholas Chin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84672?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add Z87 Extreme4 (Haswell) ...................................................................... mb/asrock: Add Z87 Extreme4 (Haswell) This port was done via autoport and subsequent manual tweaking. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection via jumper and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - HDMI-Out Port - DVI-D Port - RJ-45 Gigabit LAN Port - Both USB 2.0 Ports - All four USB 3.1 Gen1 Ports - Both USB 3.1 Gen1 headers - Vertical Type A USB 3.1 Gen1 (located next to RAM slots and PCH) - All six SATA3 6.0 Gb/s connectors by Intel - All three PCI Express 3.0 x16 slots (tested with NV 1080 Ti dGPU) - Both PCI Express 2.0 x1 slots (tested with TL-WDN4800 WiFi adapter) - HD Audio Jack (Audio output tested only) - Front Audio Jack (Audio output tested only) Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection via jumper not working: - both SATA3 6.0 Gb/s connectors by ASMedia ASM1061 not (yet) tested: - IR header - COM Port header - DisplayPort - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - PCI slots not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z87_extreme4/Kconfig A src/mainboard/asrock/z87_extreme4/Kconfig.name A src/mainboard/asrock/z87_extreme4/Makefile.mk A src/mainboard/asrock/z87_extreme4/acpi/ec.asl A src/mainboard/asrock/z87_extreme4/acpi/platform.asl A src/mainboard/asrock/z87_extreme4/acpi/superio.asl A src/mainboard/asrock/z87_extreme4/board_info.txt A src/mainboard/asrock/z87_extreme4/bootblock.c A src/mainboard/asrock/z87_extreme4/data.vbt A src/mainboard/asrock/z87_extreme4/devicetree.cb A src/mainboard/asrock/z87_extreme4/dsdt.asl A src/mainboard/asrock/z87_extreme4/gma-mainboard.ads A src/mainboard/asrock/z87_extreme4/gpio.c A src/mainboard/asrock/z87_extreme4/hda_verb.c A src/mainboard/asrock/z87_extreme4/romstage.c 15 files changed, 535 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/84672/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78791aa9877a3ad79bf8b896c583fedf37e96d9a Gerrit-Change-Number: 84672 Gerrit-PatchSet: 6 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 29 Dec '24

29 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76582?usp=email to look at the new patch set (#10). Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... ec/starlabs/merlin: Adjust the EC code to read values from CMOS This is in preparation to store options in EFI variable store, rather that option. However, some still need to stay in CMOS. Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c 2 files changed, 141 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76582/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 29 Dec '24

29 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76582?usp=email to look at the new patch set (#9). Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... ec/starlabs/merlin: Adjust the EC code to read values from CMOS This is in preparation to store options in EFI variable store, rather that option. However, some still need to stay in CMOS. Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c 2 files changed, 141 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76582/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 9 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Riku Viitanen (Code Review) 29 Dec '24

29 Dec '24

Riku Viitanen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... nb/sandybridge: Implement automatic DRAM voltage setting This change enables using higher performance XMP profiles that request more than the standard 1.5V on boards that can adjust their DRAM voltage from firmware. Precautions are taken to not run any modules outside their specifications. Furthermore, voltages higher than 1.65V are not enabled by default for safety. TEST=ASRock Z77 Extreme4. Tested various combinations of XMP and non-XMP modules. Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Signed-off-by: Riku Viitanen <riku.viitanen(a)protonmail.com> --- M src/device/Kconfig M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_native.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 78 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85793/1 diff --git a/src/device/Kconfig b/src/device/Kconfig index bcff6fd..516e840 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -1035,6 +1035,12 @@ Please note that enabling D3Cold support may break system suspend-to-RAM (S3) functionality. +config MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE + def_bool n + help + Selected by mainboards that can adjust their RAM operating + voltage from firmware. + source "src/device/dram/Kconfig" endmenu diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 9ec8fb6f..a230429 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -193,6 +193,55 @@ } /* CONFIG(HAVE_SPD_IN_CBFS) */ } +#ifdef CONFIG_MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE +#define VOLTAGE_MIN 1500 +#define VOLTAGE_MAX 1650 +#define VOLTAGE_DEFAULT 1500 +static int dram_find_highest_common_voltage(spd_ddr3_raw_data *spd) +{ + printram("Begin DRAM voltage search.\n"); + int channel, spd_slot, voltage = 0; + struct dimm_attr_ddr3_st dimm; + + FOR_ALL_CHANNELS { + for (int slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + printram("channel=%i, slot=%i\n", channel, slot); + + if (spd[spd_slot][SPD_MEMORY_TYPE] == SPD_MEMORY_TYPE_SDRAM_DDR3) { + spd_xmp_decode_ddr3(&dimm, spd[spd_slot], + DDR3_XMP_PROFILE_1); + if (dimm.dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { + /* Non-XMP DIMM. Use default voltage since + * every DIMM is supposed to work with it */ + printram("Non-XMP DIMM detected. Defaulting to %imV.", + VOLTAGE_DEFAULT); + return VOLTAGE_DEFAULT; + + } else if (dimm.voltage > VOLTAGE_MAX) { + printram("XMP requested voltage too high!\n"); + if (voltage != 0) + voltage = MIN(voltage, VOLTAGE_MAX); + else + voltage = VOLTAGE_MAX; + + } else if (dimm.voltage < VOLTAGE_MIN) { + printram("XMP requested voltage too low!?\n"); + return VOLTAGE_MIN; + + } else { + printram("Set temporary voltage to %imV\n", dimm.voltage); + voltage = MAX(voltage, dimm.voltage); + } + } + printram("voltage is %imV\n", voltage); + } + } + + return voltage; +} +#endif + static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; @@ -204,6 +253,16 @@ ctrl->extended_temperature_range = 1; ctrl->auto_self_refresh = 1; + if (CONFIG(MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE)) { + printk(BIOS_DEBUG, "Mainboard has adjustable DRAM voltage. " + "Searching for a suitable voltage.\n"); + ctrl->voltage = dram_find_highest_common_voltage(spd); + printk(BIOS_DEBUG, "Setting DRAM voltage to %imV\n", ctrl->voltage); + mainboard_set_dram_voltage(ctrl->voltage); + } else { + ctrl->voltage = 1500; + } + FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; @@ -241,8 +300,7 @@ else spd_decode_ddr3(dimm, spd[spd_slot]); - } else if (dimm->voltage != 1500) { - /* TODO: Support DDR3 voltages other than 1500mV */ + } else if (dimm->voltage != ctrl->voltage) { printram("XMP profile's requested %u mV is unsupported.\n", dimm->voltage); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ee7c525..4aeacc5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -305,7 +305,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 enum power_down_mode { PDM_NONE = 0, @@ -417,6 +417,8 @@ struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; + u16 voltage; /* operating voltage in millivolts */ + dimm_info info; } ramctr_timing; diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index ed11945..555cf5f 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -645,6 +645,12 @@ dram_dimm_mapping(ctrl); } + if (CONFIG(MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE)) { + printk(BIOS_DEBUG, "Setting DRAM voltage to %imV\n", + ctrl->voltage); + mainboard_set_dram_voltage(ctrl->voltage); + } + /* Set MPLL frequency */ dram_freq(ctrl); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 0eaa4ec..1d6214b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -63,6 +63,9 @@ void northbridge_romstage_finalize(void); void early_init_dmi(void); +/* optional callback for setting the DRAM voltage */ +void mainboard_set_dram_voltage(int voltage); + /* mainboard_early_init: Optional callback, run after console init but before raminit. */ void mainboard_early_init(int s3resume); void perform_raminit(int s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 1 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com>

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[M] Change in coreboot[main]: ec/starlabs/merlin: Adjust the EC code to read values from CMOS
by Sean Rhodes (Code Review) 29 Dec '24

29 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76582?usp=email to look at the new patch set (#8). Change subject: ec/starlabs/merlin: Adjust the EC code to read values from CMOS ...................................................................... ec/starlabs/merlin: Adjust the EC code to read values from CMOS This is in preparation to store options in EFI variable store, rather that option. However, some still need to stay in CMOS. Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/ec/starlabs/merlin/ite.c M src/ec/starlabs/merlin/nuvoton.c 2 files changed, 93 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/76582/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/76582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb094456543c75b59a8ddd80b58eb4fa1e10144f Gerrit-Change-Number: 76582 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asus/p8x7x-series: Add p8b75-v variant
by Keith Hui (Code Review) 29 Dec '24

29 Dec '24

Keith Hui has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85792?usp=email ) Change subject: mb/asus/p8x7x-series: Add p8b75-v variant ...................................................................... mb/asus/p8x7x-series: Add p8b75-v variant Not hardware tested; copied from p8h77-v and p8z77-m then adjusted USB port config and overridetree based on info seen from vendor firmware update and boardview. VBT extracted manually from vendor firmware update. Currently known facts about this board that aren't already coded into this patch: - 3 PCI slots wired to B75 PCI bridge - DRAM_LED on GP07 of SIO and power LED on GPIO27 of PCH, just like p8z77-m - Has TWO 8MiB SPI flash chips on board, both wired to PCH. It appears to use both to build a 16MiB flash space but that's to be confirmed. Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A Documentation/mainboard/asus/p8b75-v.md M Documentation/mainboard/index.md M src/mainboard/asus/p8x7x-series/Kconfig M src/mainboard/asus/p8x7x-series/Kconfig.name A src/mainboard/asus/p8x7x-series/variants/p8b75-v/board_info.txt A src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.default A src/mainboard/asus/p8x7x-series/variants/p8b75-v/cmos.layout A src/mainboard/asus/p8x7x-series/variants/p8b75-v/data.vbt A src/mainboard/asus/p8x7x-series/variants/p8b75-v/early_init.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/gma-mainboard.ads A src/mainboard/asus/p8x7x-series/variants/p8b75-v/gpio.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/hda_verb.c A src/mainboard/asus/p8x7x-series/variants/p8b75-v/overridetree.cb 13 files changed, 656 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85792/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb14c9efd1fb5b8826a646aae5f3fab9d9c08187 Gerrit-Change-Number: 85792 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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coreboot-gerrit December 2024