coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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3018 discussions

[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by David Wu (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > we might need to include the header file inside chip.h to avoid the compilation issue […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 04:14:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: we might need to include the header file inside chip.h to avoid the compilation issue https://qa.coreboot.org/job/coreboot-gerrit/269275/testReport/junit/(root)/… -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:53:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85520/comment/b445c5bb_c638a19b?us… : PS3, Line 10: > The issue does not occur on Karis due to different WIFI module type with current projects, Karis is using M.2 (none solder down version),The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis result in #102, We appreciate your understanding and kindly request your assistance in reviewing this. Thank you! do you mind adding such details into commit msg for better code readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:52:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85526?usp=email ) Change subject: soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl ...................................................................... soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl This patch corrects the conditional inclusion of the `ufs.asl` file in the southbridge ACPI configuration. Previously, the inclusion of `ufs.asl` was incorrectly dependent on the `MAINBOARD_USES_IFD_GBE_REGION` Kconfig option. This prevented the UFS ACPI entry from being included in the DSDT when `MAINBOARD_USES_IFD_GBE_REGION` was disabled, causing issues with booting from UFS media. This commit fixes the issue by ensuring that `ufs.asl` is included based on the `SOC_INTEL_PANTHERLAKE_U_H` Kconfig option, which correctly reflects the presence of UFS hardware. This change ensures that the UFS ACPI device is correctly enumerated and available to the operating system. BUG=b:382243957 TEST=Able to verify UFS ACPI device is available inside DSDT table. Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/acpi/southbridge.asl 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85526/1 diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl index c047a71..a6cdda3 100644 --- a/src/soc/intel/pantherlake/acpi/southbridge.asl +++ b/src/soc/intel/pantherlake/acpi/southbridge.asl @@ -47,10 +47,9 @@ /* GbE 0:1f.6 */ #if CONFIG(MAINBOARD_USES_IFD_GBE_REGION) #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> +#endif /* UFS 0:17:0 */ #if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) #include <soc/intel/common/block/acpi/acpi/ufs.asl> #endif - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85526?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a Gerrit-Change-Number: 85526 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by David Wu (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85520/comment/224bba64_87c867ed?us… : PS3, Line 10: > can you please capture the motivation as well. […] The issue does not occur on Karis due to different WIFI module type with current projects, Karis is using M.2 (none solder down version),The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis result in #102, We appreciate your understanding and kindly request your assistance in reviewing this. Thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85520/comment/ca1a9d15_ea610fa8?us… : PS3, Line 10: can you please capture the motivation as well. We have wifi-7 for Karis as well but we don't have to limit the speed there -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:11:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email ) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:11:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by David Wu (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/riven/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85520/comment/6f02b87d_12f136a8?us… : PS1, Line 490: .pcie_rp_pcie_speed = 2, > why we need to set wifi7 as Gen2 ? As concluded in the 12/7 meeting, based on the current test results for #137, #138, all relevant parties have reached a consensus that the current solution to the issue is to set PCIe root port 4 speed to Gen2, apply the pcie_recovery_patch in #103, and implement the core90_fix in #85 from Intel. Debugging will continue to identify the root cause and develop a comprehensive solution to resolve the issue. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 03:01:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by David Wu (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email ) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/85519/comment/079a14ad_c34e6173?us… : PS3, Line 85: Pcie_Speed_control > i would request to avoid camel casing if possible Done. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 02:53:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit December 2024