coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[XS] Change in coreboot[main]: soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
by Kapil Porwal (Code Review) 08 Dec '24

08 Dec '24

Attention is currently required from: Divagar Mohandass, Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85526?usp=email ) Change subject: soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85526?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a Gerrit-Change-Number: 85526 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sun, 08 Dec 2024 04:52:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/pci_ids: Add Pantherlake-H GT2 (DID2)
by Felix Singer (Code Review) 08 Dec '24

08 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85525?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device/pci_ids: Add Pantherlake-H GT2 (DID2) ...................................................................... device/pci_ids: Add Pantherlake-H GT2 (DID2) This patch adds new DID2 PCI device ID for Intel PTL. Reference: Bspec 72574 BUG=b:380362184 TEST=Able to build google/fatcat. Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85525 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/pantherlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 6386891..60ed807 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4306,6 +4306,7 @@ #define PCI_DID_INTEL_PTL_U_GT2_1 0xb090 #define PCI_DID_INTEL_PTL_H_GT2_1 0xb080 #define PCI_DID_INTEL_PTL_H_GT2_2 0xb0a0 +#define PCI_DID_INTEL_PTL_H_GT2_3 0xb0b0 /* Intel Northbridge Ids */ #define PCI_DID_INTEL_APL_NB 0x5af0 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 50d3c51..144e8c3 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -345,6 +345,7 @@ PCI_DID_INTEL_PTL_U_GT2_1, PCI_DID_INTEL_PTL_H_GT2_1, PCI_DID_INTEL_PTL_H_GT2_2, + PCI_DID_INTEL_PTL_H_GT2_3, PCI_DID_INTEL_LNL_M_GT2, PCI_DID_INTEL_RPL_U_GT1, PCI_DID_INTEL_RPL_U_GT2, diff --git a/src/soc/intel/pantherlake/bootblock/report_platform.c b/src/soc/intel/pantherlake/bootblock/report_platform.c index 55afc49..aa8b030 100644 --- a/src/soc/intel/pantherlake/bootblock/report_platform.c +++ b/src/soc/intel/pantherlake/bootblock/report_platform.c @@ -112,6 +112,7 @@ { PCI_DID_INTEL_PTL_U_GT2_1, "Pantherlake-U GT2" }, { PCI_DID_INTEL_PTL_H_GT2_1, "Pantherlake-H GT2" }, { PCI_DID_INTEL_PTL_H_GT2_2, "Pantherlake-H GT2" }, + { PCI_DID_INTEL_PTL_H_GT2_3, "Pantherlake-H GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/85525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Gerrit-Change-Number: 85525 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: device/pci_ids: Add Pantherlake-H GT2 (DID2)
by Bora Guvendik (Code Review) 08 Dec '24

08 Dec '24

Attention is currently required from: Kapil Porwal, Paul Menzel, Pranava Y N. Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/85525?usp=email ) Change subject: device/pci_ids: Add Pantherlake-H GT2 (DID2) ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85525/comment/db8413d9_9b2147ab?us… : PS1, Line 7: IDs > Singular, as you only add one? Done https://review.coreboot.org/c/coreboot/+/85525/comment/f2194a6e_d73003fe?us… : PS1, Line 7: Add new Intel PTL device IDs for DID2 > As the prefix says `pci_ids` maybe just: […] Done https://review.coreboot.org/c/coreboot/+/85525/comment/236f3285_35c4a4b7?us… : PS1, Line 9: This patch adds new DID2 PCI device ID for Intel PTL. > Where did you get the id from? https://patchwork.freedesktop.org/patch/624615/?series=141372&rev=1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Gerrit-Change-Number: 85525 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 07 Dec 2024 23:40:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: device/pci_ids: Add Pantherlake-H GT2 (DID2)
by Bora Guvendik (Code Review) 08 Dec '24

08 Dec '24

Attention is currently required from: Bora Guvendik, Kapil Porwal, Pranava Y N. Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85525?usp=email to look at the new patch set (#2). Change subject: device/pci_ids: Add Pantherlake-H GT2 (DID2) ...................................................................... device/pci_ids: Add Pantherlake-H GT2 (DID2) This patch adds new DID2 PCI device ID for Intel PTL. Reference: Bspec 72574 BUG=b:380362184 TEST=Able to build google/fatcat. Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/pantherlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85525/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Gerrit-Change-Number: 85525 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yidi Lin (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 8 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 07 Dec 2024 11:54:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/meidatek/mt8196/blobs: Add SPM firmware v1.0
by Yidi Lin (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Wenzhen Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Wenzhen Yu. ( https://review.coreboot.org/c/blobs/+/85285?usp=email ) Change subject: soc/meidatek/mt8196/blobs: Add SPM firmware v1.0 ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Please correct the file name to `spm_firmware.bin`. -- To view, visit https://review.coreboot.org/c/blobs/+/85285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic5b5417b9b746fcca225209d9b17108a2499ac71 Gerrit-Change-Number: 85285 Gerrit-PatchSet: 4 Gerrit-Owner: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 07 Dec 2024 11:47:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by Ren Kuo (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Ren Kuo has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email ) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 09:23:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/hp: Add HP Compaq 8300 Elite SFF
by Paul Menzel (Code Review) 07 Dec '24

07 Dec '24

Paul Menzel has posted comments on this change by Michał Zieliński. ( https://review.coreboot.org/c/coreboot/+/67666?usp=email ) Change subject: mb/hp: Add HP Compaq 8300 Elite SFF ...................................................................... Patch Set 12: (1 comment) Patchset: PS12: Thank you again for making the port, and congratulations for getting in submitted. It’d be great if you could upload the logs to the board status repository (`util/board_status/`). Thank you in advance. -- To view, visit https://review.coreboot.org/c/coreboot/+/67666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5322acc0210f000b53954e2925549358f86d5c8 Gerrit-Change-Number: 67666 Gerrit-PatchSet: 12 Gerrit-Owner: Michał Zieliński Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 09:21:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by David Wu (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email ) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... Patch Set 5: (2 comments) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/85519/comment/d523b743_6a448420?us… : PS4, Line 61: PCIE > PCIe Done https://review.coreboot.org/c/coreboot/+/85519/comment/82386668_a0d02a39?us… : PS4, Line 84: Pcie > PCIe as above. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 08:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by David Wu (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85520/comment/ccb92bcc_09695633?us… : PS3, Line 10: > I don’t see the updated commit message yet. It’d be great if you could do this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 5 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 07 Dec 2024 08:30:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Wu <david_wu(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit December 2024