coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by Ren Kuo (Code Review) 09 Dec '24

09 Dec '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 The decision to set PCIe root port 5 speed to Gen2 is based on experiment setup for b/376156567 and analysis results in comment #86. The setting will fix the issue of Wifi 7 M.2 module doesn't work. BUG=b:376156567 TEST=Boot to OS and then check link speed. Use command: lspci -vv | grep 'LnkSta' Before LnkSta: Speed 8GT/s (downgraded), Width x1 After LnkSta: Speed 5GT/s (downgraded), Width x1 Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85533/1 diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 880b3dd..4e554ab 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -294,6 +294,7 @@ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_pcie_speed = SPEED_GEN2, }" chip drivers/wifi/generic register "wake" = "GPE0_DW0_03" -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

1 0

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC mt6373 driver
by Jarried Lin (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85129?usp=email to look at the new patch set (#22). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add PMIC mt6373 driver ...................................................................... soc/mediatek/mt8196: Add PMIC mt6373 driver 1. add mt6373 driver in soc folder 2. add regulator api for SD power 3. add implement interface for vcn33_3 4. enable vcn33_3 & set vcn33_3 3.3v 5. add MT6373 LDO enable api TEST=build pass BUG=b:317009620 Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6373.h A src/soc/mediatek/common/mt6373.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6373.c 4 files changed, 718 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85129/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 22 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

1 0

[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Mark Chang (Code Review) 09 Dec '24

09 Dec '24

Mark Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Add support for MiTAC Computing Whitestone-2 mainboard Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Signed-off-by: Mark Chang <mark.chang(a)mitaccomputing.com> --- A configs/config.mitaccomputing_ws_2 A src/mainboard/mitaccomputing/Kconfig A src/mainboard/mitaccomputing/Kconfig.name A src/mainboard/mitaccomputing/whitestone-2/Kconfig A src/mainboard/mitaccomputing/whitestone-2/Kconfig.name A src/mainboard/mitaccomputing/whitestone-2/Makefile.mk A src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl A src/mainboard/mitaccomputing/whitestone-2/board.fmd A src/mainboard/mitaccomputing/whitestone-2/board_info.txt A src/mainboard/mitaccomputing/whitestone-2/bootblock.c A src/mainboard/mitaccomputing/whitestone-2/devicetree.cb A src/mainboard/mitaccomputing/whitestone-2/dsdt.asl A src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h A src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h A src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h A src/mainboard/mitaccomputing/whitestone-2/mainboard.c A src/mainboard/mitaccomputing/whitestone-2/ramstage.c A src/mainboard/mitaccomputing/whitestone-2/romstage.c 18 files changed, 780 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85532/1 diff --git a/configs/config.mitaccomputing_ws_2 b/configs/config.mitaccomputing_ws_2 new file mode 100644 index 0000000..29a6c81 --- /dev/null +++ b/configs/config.mitaccomputing_ws_2 @@ -0,0 +1,28 @@ +# MiTAC Computing Whitestone-2 coreboot is modified from Intel ArcherCity CRB +# MiTAC Computing Whitestone-2 is a one socket CRB based on Intel. +# Sapphire Rapids Scalable Processor (SPR-SP) chipset. +# +# Type this in coreboot root directory to get a working .config: +# make defconfig KBUILD_DEFCONFIG=configs/config.config.mitaccomputing_ws_2 + +CONFIG_VENDOR_MITAC_COMPUTING=y +CONFIG_MAINBOARD_FAMILY="MiTAC Computing whitestone_2" +CONFIG_MAINBOARD_PART_NUMBER="MiTAC Computing WHITESTONE-2" +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_MAINBOARD_VENDOR="MiTAC Computing Technology Corp." +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="MiTAC Computing Technology Corp." +CONFIG_BOARD_MITAC_COMPUTING_WHITESTONE_2=y +CONFIG_X2APIC_LATE_WORKAROUND=y +CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200" +CONFIG_PAYLOAD_LINUX=y +CONFIG_PAYLOAD_FILE="site-local/whitestone-2/bzImage" +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_T_FILE="site-local/whitestone-2/Fsp_T.fd" +CONFIG_FSP_M_FILE="site-local/whitestone-2/Fsp_M.fd" +CONFIG_FSP_S_FILE="site-local/whitestone-2/Fsp_S.fd" +CONFIG_HAVE_IFD_BIN=y +CONFIG_IFD_BIN_PATH="site-local/whitestone-2/descriptor.bin" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_BIN_PATH="site-local/whitestone-2/me.bin" +CONFIG_HAVE_GBE_BIN=y +CONFIG_GBE_BIN_PATH="site-local/whitestone-2/gbe.bin" diff --git a/src/mainboard/mitaccomputing/Kconfig b/src/mainboard/mitaccomputing/Kconfig new file mode 100644 index 0000000..c6a91e0 --- /dev/null +++ b/src/mainboard/mitaccomputing/Kconfig @@ -0,0 +1,15 @@ +if VENDOR_MITAC_COMPUTING + +choice + prompt "Mainboard model" + +source "src/mainboard/mitaccomputing/*/Kconfig.name" + +endchoice + +source "src/mainboard/mitaccomputing/*/Kconfig" + +config MAINBOARD_VENDOR + default "MiTAC Computing" + +endif # VENDOR_MITAC_COMPUTING diff --git a/src/mainboard/mitaccomputing/Kconfig.name b/src/mainboard/mitaccomputing/Kconfig.name new file mode 100644 index 0000000..743b2db --- /dev/null +++ b/src/mainboard/mitaccomputing/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_MITAC_COMPUTING + bool "MiTAC Computing" diff --git a/src/mainboard/mitaccomputing/whitestone-2/Kconfig b/src/mainboard/mitaccomputing/whitestone-2/Kconfig new file mode 100644 index 0000000..03c4765 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/Kconfig @@ -0,0 +1,54 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_MITAC_COMPUTING_WHITESTONE_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select CPU_INTEL_SOCKET_LGA4677 + select CONSOLE_OVERRIDE_LOGLEVEL + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select IPMI_OCP + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + select DRIVERS_ASPEED_AST2050 + select SOC_INTEL_SAPPHIRERAPIDS_SP + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select MAINBOARD_USES_IFD_GBE_REGION + select VPD + select OCP_EWL + select OCP_VPD + +config MAINBOARD_DIR + string + default "mitaccomputing/whitestone-2" + +config MAINBOARD_PART_NUMBER + string + default "Whitestone 2" + +config MAINBOARD_FAMILY + default "Intel Eagle Stream Server" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config MAX_SOCKET + int + default 1 + +config DIMM_MAX + int + default 16 + +config UART_FOR_CONSOLE + int + default 0 + +config TTYS0_BAUD + default 115200 + +endif diff --git a/src/mainboard/mitaccomputing/whitestone-2/Kconfig.name b/src/mainboard/mitaccomputing/whitestone-2/Kconfig.name new file mode 100644 index 0000000..57d4133 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_MITAC_COMPUTING_WHITESTONE_2 + bool "Whitestone 2" diff --git a/src/mainboard/mitaccomputing/whitestone-2/Makefile.mk b/src/mainboard/mitaccomputing/whitestone-2/Makefile.mk new file mode 100644 index 0000000..4c7a7be --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +ramstage-y += ramstage.c +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl b/src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl new file mode 100644 index 0000000..4853874 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <southbridge/intel/common/acpi/sleepstates.asl> + +/* Port 80 POST */ +OperationRegion (DBG0, SystemIO, 0x80, 0x02) +Field (DBG0, ByteAcc, Lock, Preserve) +{ + IO80, 8, + IO81, 8 +} + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method (_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method (_WAK, 1) +{ + Return (Package (){ 0, 0 }) +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/board.fmd b/src/mainboard/mitaccomputing/whitestone-2/board.fmd new file mode 100644 index 0000000..57ffccb --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/board.fmd @@ -0,0 +1,13 @@ +FLASH 64M { + SI_ALL@0x0 0x03000000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x7ed000 + SI_PT@0x7f0000 0x2810000 + } + RW_MRC_CACHE@0x3000000 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/board_info.txt b/src/mainboard/mitaccomputing/whitestone-2/board_info.txt new file mode 100644 index 0000000..0e759a4 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: MiTAC Computing +Board name: Whitestone 2 +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/mitaccomputing/whitestone-2/bootblock.c b/src/mainboard/mitaccomputing/whitestone-2/bootblock.c new file mode 100644 index 0000000..641643e --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/bootblock.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE); + uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN); + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); + pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, + com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/devicetree.cb b/src/mainboard/mitaccomputing/whitestone-2/devicetree.cb new file mode 100644 index 0000000..3238207 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/devicetree.cb @@ -0,0 +1,35 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/spr + # configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs + register "turbo_ratio_limit" = "0x181819191e242424" + register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18" + + device domain 0 on + device pci 1f.0 on # Intel device 1b81: PCH eSPI controller + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end + end + end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 on end + end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/mitaccomputing/whitestone-2/dsdt.asl b/src/mainboard/mitaccomputing/whitestone-2/dsdt.asl new file mode 100644 index 0000000..2204748 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <acpi/dsdt_top.asl> + // platform ACPI tables + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + // SPR-SP ACPI tables + #include <soc/intel/xeon_sp/spr/acpi/uncore.asl> + + // LPC related entries + Scope (\_SB.PC00) + { + #include <soc/intel/xeon_sp/spr/acpi/pch.asl> + } +} diff --git a/src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h b/src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h new file mode 100644 index 0000000..c68740d --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef WS_2_ONBOARD_H +#define WS_2_ONBOARD_H + +#define E810_CAM_NUMBER 2 +#define E810_CAM1_PORT_NUMBER 4 +#define E810_CAM2_PORT_NUMBER 8 +#define E810_CAM_PORT_NUMBER (E810_CAM1_PORT_NUMBER + E810_CAM2_PORT_NUMBER) +#define E810_CAM_PORT_NAME_LENGTH 15 +#define E810_CAM1_BUS_NUMBER 0x43 +#define E810_CAM2_BUS_NUMBER 0x44 + +#endif /* End of WS_2_ONBOARD_H */ diff --git a/src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h b/src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h new file mode 100644 index 0000000..b823f01 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPPC_A ------- */ + /* PCH default for ESPI inter GPPC_A0-A9 */ + PAD_CFG_NF_OWNERSHIP(GPPC_A0, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A1, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A2, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A3, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A4, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A5, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A6, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A7, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A8, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A9, DN_20K, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_A10, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPPC_A11, UP_20K, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_A12, DN_20K, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_A13, 1, DEEP), + PAD_CFG_GPO(GPPC_A14, 1, DEEP), + PAD_CFG_GPO(GPPC_A15, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_A16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_A18, 1, DEEP), + PAD_CFG_GPO(GPPC_A19, 1, DEEP), + + /* ------- GPIO Group GPPC_B ------- */ + PAD_CFG_NF_OWNERSHIP(GPPC_B0, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B1, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B2, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B3, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B4, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B5, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B9, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B10, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B12, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B13, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B14, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B15, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B16, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B17, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B18, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B19, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B20, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B21, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B22, NONE, DEEP, NF4, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_B23, NONE, DEEP, NF4, ACPI), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPPC_C ------- */ + PAD_CFG_NF_OWNERSHIP(GPPC_C0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C1, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C2, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C4, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C5, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C6, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C7, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C9, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C10, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_C11, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_C12, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPPC_C13, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_C14, 1, DEEP), + PAD_CFG_GPO(GPPC_C15, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPPC_C16, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPPC_C17, 1, PLTRST), + PAD_CFG_GPO(GPPC_C18, 1, PLTRST), + PAD_CFG_NF_OWNERSHIP(GPPC_C19, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C20, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPPC_C21, NONE, DEEP, NF1, ACPI), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_NF_OWNERSHIP(GPP_D0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D1, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D2, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D9, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D12, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D13, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D14, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D15, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D16, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D17, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D20, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPP_D21, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_D22, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E8, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E9, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E10, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E11, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E12, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E13, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E14, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E15, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_E16, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_E18, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_I ------- */ + PAD_CFG_GPO(GPP_I12, 1, DEEP), + PAD_CFG_GPO(GPP_I13, 1, DEEP), + PAD_CFG_GPO(GPP_I14, 1, DEEP), + PAD_CFG_GPO(GPP_I15, 1, DEEP), + PAD_CFG_GPO(GPP_I16, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_I17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_GPO(GPP_J2, 1, DEEP), + PAD_CFG_NF_OWNERSHIP(GPP_J3, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_J4, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_J8, NONE, DEEP, NF1, ACPI), + + /* ------- GPIO Group GPP_L ------- */ + PAD_CFG_NF_OWNERSHIP(GPP_L0, NONE, DEEP, NF1, ACPI), + PAD_CFG_NF_OWNERSHIP(GPP_L1, NONE, DEEP, NF1, ACPI), + PAD_CFG_GPO(GPP_L2, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_L7, 1, DEEP), + PAD_CFG_GPO(GPP_L8, 1, DEEP), + + /* ------- GPIO Group GPP_M ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_N ------- */ + /* GPP_N1 - GPIO */ + PAD_NC(GPP_N1, NONE), + /* GPP_N4 - GPIO */ + PAD_NC(GPP_N4, NONE), + + /* ------- GPIO Group GPP_O ------- */ + /* GPP_O0 - GPIO */ + PAD_NC(GPP_O0, NONE), + /* GPP_O7 - GPIO */ + PAD_NC(GPP_O7, NONE), + + /* ------- GPIO Group GPPC_H ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H1, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_H15, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H18, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPPC_S ------- */ + PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_S1, 1, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S6, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPPC_S7, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPPC_S8, 1, DEEP), + PAD_CFG_GPO(GPPC_S9, 1, DEEP), + PAD_CFG_GPO(GPPC_S10, 1, DEEP), + PAD_CFG_GPO(GPPC_S11, 1, DEEP), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h b/src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h new file mode 100644 index 0000000..ac39292 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SPRSP_WS2_IIO_H_ +#define _SPRSP_WS2_IIO_H_ + +#include <defs_iio.h> +#include <soc/soc_util.h> + +/* For now only set 3 fields and hard-coded others, should be extended in the future */ +#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ + { \ + .SLOTEIP = 0, \ + .SLOTHPCAP = 0, \ + .SLOTHPSUP = 0, \ + .SLOTPIP = 0, \ + .SLOTAIP = 0, \ + .SLOTMRLSP = 0, \ + .SLOTPCP = 0, \ + .SLOTABP = 0, \ + .SLOTIMP = slotimp, \ + .SLOTSPLS = 0, \ + .SLOTSPLV = 0, \ + .SLOTPSP = slotpsp, \ + .VppEnabled = 0, \ + .VppPort = 0, \ + .VppAddress = 0, \ + .MuxAddress = 0, \ + .ChannelID = 0, \ + .PciePortEnable = 1, \ + .PEXPHIDE = pexphide, \ + .HidePEXPMenu = 0, \ + .PciePortOwnership = 0, \ + .RetimerConnectCount = 0, \ + .PcieMaxPayload = 0x7, \ + .PciePortLinkSpeed = 0, \ + .DfxDnTxPresetGen3 = 0xFF \ + } + +/* + * Whitestone 2 IIO PCIe Port Table + */ +static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY ws2_iio_pci_port[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { + { + /* DMI port: array index 0 */ + CFG_UPD_PCIE_PORT(0, 0, 0), + /* IOU0 (PE0): array index 1 ~ 8 */ + CFG_UPD_PCIE_PORT(0, 1, 1), /* 15:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU1 (PE1): array index 9 ~ 16 */ + CFG_UPD_PCIE_PORT(0, 1, 9), /* 26:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(0, 1, 13), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU2 (PE2): array index 17 ~ 24 */ + CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU3 (PE3): array index 25 ~ 32 */ + CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), /* 48:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), /* 48:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), /* 48:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + /* IOU4 (PE4): array index 33 ~ 40 */ + CFG_UPD_PCIE_PORT(0, 1, 33), /* 59:01.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), /* 59:03.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), /* 59:05.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + CFG_UPD_PCIE_PORT(1, 0, 0), /* 59:07.0 */ + CFG_UPD_PCIE_PORT(1, 0, 0), + }, +}; + +static const UINT8 ws2_iio_bifur[CONFIG_MAX_SOCKET][5] = { + { + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxx8xxx8, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + IIO_BIFURCATE_xxxxxx16, + }, +}; +#endif /* _SPRSP_WS2_IIO_H_ */ diff --git a/src/mainboard/mitaccomputing/whitestone-2/mainboard.c b/src/mainboard/mitaccomputing/whitestone-2/mainboard.c new file mode 100644 index 0000000..76cd238 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/mainboard.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <device/device.h> +#include "smbios_onboard.h" +#include <smbios.h> + +const char *e810_cam1_port_name[E810_CAM1_PORT_NUMBER] = { + "E810 CAM1 Port1", + "E810 CAM1 Port2", + "E810 CAM1 Port3", + "E810 CAM1 Port4", +}; + +const char *e810_cam2_port_name[E810_CAM2_PORT_NUMBER] = { + "E810 CAM2 Port1", + "E810 CAM2 Port2", + "E810 CAM2 Port3", + "E810 CAM2 Port4", + "E810 CAM2 Port5", + "E810 CAM2 Port6", + "E810 CAM2 Port7", + "E810 CAM2 Port8", +}; + +static int e810_smbios_type41(int *handle, unsigned long *current, + const char *name, u8 type_instance, u8 bus_number, u8 function_number) +{ + struct smbios_type41 *t = smbios_carve_table(*current, + SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION, + sizeof(*t), *handle); + + t->reference_designation = smbios_add_string(t->eos, name); + t->device_type = SMBIOS_DEVICE_TYPE_ETHERNET; + t->device_status = 1; + t->device_type_instance = type_instance; + t->segment_group_number = 0; + t->bus_number = bus_number; + t->function_number = function_number; + t->device_number = 0; + + const int data_length = smbios_full_table_len(&t->header, t->eos); + *current += data_length; + *handle += 1; + return data_length; +} + + +static int ws_2_onboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int data_length = 0; + int type_instance = 0; + + for (int i = 0; i < E810_CAM1_PORT_NUMBER; i++) { + data_length += e810_smbios_type41(handle, current, + e810_cam1_port_name[i], + ++type_instance, + E810_CAM1_BUS_NUMBER, + i); + } + + for (int i = 0; i < E810_CAM2_PORT_NUMBER; i++) { + data_length += e810_smbios_type41(handle, current, + e810_cam2_port_name[i], + ++type_instance, + E810_CAM2_BUS_NUMBER, + i); + } + return data_length; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->get_smbios_data = ws_2_onboard_smbios_data; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/mitaccomputing/whitestone-2/ramstage.c b/src/mainboard/mitaccomputing/whitestone-2/ramstage.c new file mode 100644 index 0000000..3372724 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/ramstage.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> +#include "include/spr_ws_2_gpio.h" +#include <bootstate.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + /* configure Emmitsburg PCH GPIO controller after FSP-M */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void finalize_boot(void *unused) +{ + printk(BIOS_DEBUG, "FM_BIOS_POST_CMPLT_N cleared.\n"); + /* Clear FM_BIOS_POST_CMPLT_N */ + gpio_output(GPPC_C17, 0); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/mitaccomputing/whitestone-2/romstage.c b/src/mainboard/mitaccomputing/whitestone-2/romstage.c new file mode 100644 index 0000000..d1d8985 --- /dev/null +++ b/src/mainboard/mitaccomputing/whitestone-2/romstage.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/vpd/vpd.h> +#include <drivers/ocp/include/vpd.h> +#include <soc/romstage.h> +#include <defs_cxl.h> +#include <defs_iio.h> +#include <sprsp_ws_2_iio.h> + +static void mainboard_config_iio(FSPM_UPD *mupd) +{ + /* If CONFIG(OCP_VPD) is not enabled or CXL is explicitly disabled, don't enable CXL */ + if (!CONFIG(OCP_VPD) || get_cxl_mode_from_vpd() == CXL_DISABLED) { + printk(BIOS_DEBUG, "Don't enable CXL via VPD %s\n", CXL_MODE); + } else { + /* Set socket 0 IIO PCIe PE1 to CXL mode */ + /* eg. Protocl Auto Negotiation */ + mupd->FspmConfig.IioPcieSubSystemMode1[0] = IIO_MODE_CXL; + + mupd->FspmConfig.DfxCxlHeaderBypass = 0; + mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED; + + mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000; /* ms */ + } +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + uint8_t val; + + /* Send FSP log message to SOL */ + if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) + mupd->FspmConfig.SerialIoUartDebugEnable = val; + else { + printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", + FSP_LOG, FSP_LOG_DEFAULT); + mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + } + + /* Set Rank Margin Tool to disable. */ + mupd->FspmConfig.EnableRMT = 0x0; + /* Enable - Portions of memory reference code will be skipped + * when possible to increase boot speed on warm boots. + * Disable - Disables this feature. + * Auto - Sets it to the MRC default setting. + */ + mupd->FspmConfig.AttemptFastBoot = 0x1; + mupd->FspmConfig.AttemptFastBootCold = 0x1; + + /* Set Adv MemTest Option to 0. */ + mupd->FspmConfig.AdvMemTestOptions = 0x0; + /* Set MRC Promote Warnings to disable. + Determines if MRC warnings are promoted to system level. */ + mupd->FspmConfig.promoteMrcWarnings = 0x0; + /* Set Promote Warnings to disable. + Determines if warnings are promoted to system level. */ + mupd->FspmConfig.promoteWarnings = 0x0; + soc_config_iio(mupd, ws2_iio_pci_port, ws2_iio_bifur); + mainboard_config_iio(mupd); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com>

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Enable ARM Trusted Firmware integration
by Yu-Ping Wu (Code Review) 09 Dec '24

09 Dec '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85503?usp=email ) Change subject: soc/mediatek/mt8196: Enable ARM Trusted Firmware integration ...................................................................... soc/mediatek/mt8196: Enable ARM Trusted Firmware integration Enable configuration to build with MT8196 arm-trusted-firmware drivers. TEST=build pass BUG=b:317009620 Change-Id: I516e648f78b74cc5ea82f52084d5b9dbaeb6f7f0 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85503 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index c934761..984e379 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -7,6 +7,7 @@ select ARCH_VERSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select HAVE_UART_SPECIAL select CACHE_MRC_SETTINGS select MEDIATEK_DRAM_BLOB_FAST_INIT diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 9d00a2e..3f76811 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -29,6 +29,7 @@ romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dpm_v2.c ramstage-y += dramc_info.c ramstage-y += ../common/early_init.c @@ -40,6 +41,8 @@ ramstage-y += soc.c ramstage-y += ../common/usb.c usb.c +BL31_MAKEARGS += PLAT=mt8196 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/85503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I516e648f78b74cc5ea82f52084d5b9dbaeb6f7f0 Gerrit-Change-Number: 85503 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: Update arm-trusted-firmware submodule to upstream master
by Yu-Ping Wu (Code Review) 09 Dec '24

09 Dec '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85517?usp=email ) Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 8fb91783ffa9: 2024-08-23 14:45:12 +0200 - (Merge "fix(intel): add in missing ECC register" into integration) to commit id 15e5c6c91d48: 2024-12-05 16:00:37 +0100 - (Merge changes I00d2de7b,I5ec82646 into integration) This brings in 512 new commits. Change-Id: I18b5bae0f48b2794a40d8c9e9cba8c69639669f6 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85517 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Elyes Haouas: Looks good to me, approved build bot (Jenkins): Verified diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 8fb9178..15e5c6c 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 8fb91783ffa96343dd8ebad9773d7c2055ea4496 +Subproject commit 15e5c6c91d483aa52908154cc80e48956e234232 -- To view, visit https://review.coreboot.org/c/coreboot/+/85517?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18b5bae0f48b2794a40d8c9e9cba8c69639669f6 Gerrit-Change-Number: 85517 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Enable ARM Trusted Firmware integration
by Yu-Ping Wu (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85503?usp=email ) Change subject: soc/mediatek/mt8196: Enable ARM Trusted Firmware integration ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I516e648f78b74cc5ea82f52084d5b9dbaeb6f7f0 Gerrit-Change-Number: 85503 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 03:46:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: soc/intel/alderlake: Add a function to force disable memory channels
by Kapil Porwal (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Subrata Banik. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add a function to force disable memory channels ...................................................................... Patch Set 1: (1 comment) This change is ready for review. File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/0df8554d_92b82275?us… : PS1, Line 236: mem_init_override_channel_mask suggestion: `mem_init_enforce_ch_disable_mask()` -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 03:05:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
by Daniel Peng (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Daniel Peng has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/85363?usp=email ) Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Patchset: PS4: Ready for review. Please kindly help to review if no concern. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/85363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Gerrit-Change-Number: 85363 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Dec 2024 01:46:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/intel/common/block: Add const qualifier for input of pirq ops
by Shuo Liu (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85283?usp=email ) Change subject: soc/intel/common/block: Add const qualifier for input of pirq ops ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/include/intelblocks/itss.h: https://review.coreboot.org/c/coreboot/+/85283/comment/334c3bf2_7dccbf90?us… : PS5, Line 51: uint32_t itss_soc_get_on_chip_dev_pir(const struct device *dev); > Snow Ridge is also using this function, I'm wondering why compiler doesn't complain about this incon […] I add changes for snowridge, could you please check if this is working on it? P.S. a function by const struct *device can accept a non-const input, but cannot vice versa. -- To view, visit https://review.coreboot.org/c/coreboot/+/85283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0 Gerrit-Change-Number: 85283 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 01:26:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com

1 0

[XS] Change in coreboot[main]: soc/intel/common/block: Add const qualifier for input of pirq ops
by Shuo Liu (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, Shuo Liu. Hello Angel Pons, Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85283?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+2 by Lean Sheng Tan, Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block: Add const qualifier for input of pirq ops ...................................................................... soc/intel/common/block: Add const qualifier for input of pirq ops Add const qualifer for itss_get_on_chip_dev_pirq and itss_soc_get_on_chip_dev_pir so that these ops could be used for both struct device * input and const struct device * input. Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/itss/itss.c M src/soc/intel/snowridge/itss.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85283/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0 Gerrit-Change-Number: 85283 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024