coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[XS] Change in coreboot[main]: soc/mediatek/mt8196: Rename SCP to SPM base variables
by Yu-Ping Wu (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85521?usp=email ) Change subject: soc/mediatek/mt8196: Rename SCP to SPM base variables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85521?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I044bdb5a02c7fef4cf7be1f6aa759a33d9cc0c8c Gerrit-Change-Number: 85521 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 07:09:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: arch/x86: Add breakpoint to stack canary
by Subrata Banik (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Alicja Michalska, Andrey Petrov, Benjamin Doron, Jeremy Compostella, Jérémy Compostella, Patrick Rudolph, Ronak Kanabar. Subrata Banik has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84833?usp=email ) Change subject: arch/x86: Add breakpoint to stack canary ...................................................................... Patch Set 18: (2 comments) File src/arch/x86/Makefile.mk: https://review.coreboot.org/c/coreboot/+/84833/comment/5d088a72_474ecb4e?us… : PS12, Line 72: bootblock > I don't see any problem here. The newly-added functions must be defined when the following is true: […] Acknowledged https://review.coreboot.org/c/coreboot/+/84833/comment/e500f905_1ddf186a?us… : PS12, Line 120: verstage > Same as above Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Gerrit-Change-Number: 84833 Gerrit-PatchSet: 18 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 06:58:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common: Drop locking function fast_spi_set_vcl
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85437?usp=email ) Change subject: soc/intel/common: Drop locking function fast_spi_set_vcl ...................................................................... soc/intel/common: Drop locking function fast_spi_set_vcl Drop function fast_spi_set_vcl as the same code already exists as fast_spi_vscc0_lock() and is already run on xeon_sp. Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85437 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h M src/soc/intel/xeon_sp/ebg/lockdown.c M src/soc/intel/xeon_sp/ibl/lockdown.c 4 files changed, 0 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 0a23e08..4551961 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -464,17 +464,6 @@ pci_or_config32(dev, SPI_BIOS_DECODE_EN, SPI_BIOS_DECODE_LOCK); } -/* Set FAST_SPIBAR + SPIBAR_SFDP0_VSCC0 (0xc4) Vendor Control Lock */ -void fast_spi_set_vcl(void) -{ - void *spibar = fast_spi_get_bar(); - uint32_t vcss; - - vcss = read32(spibar + SPIBAR_SFDP0_VSCC0); - vcss |= SPIBAR_SFDP0_VSCC0_VCL; - write32(spibar + SPIBAR_SFDP0_VSCC0, vcss); -} - void fast_spi_clear_outstanding_status(void) { void *spibar = fast_spi_get_bar(); diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 46b4f48..716f16a 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -107,9 +107,5 @@ * Set FAST_SPIBAR BIOS Decode Lock bit */ void fast_spi_set_bde(void); -/* - * Set FAST_SPIBAR Vendor Component Lock bit. - */ -void fast_spi_set_vcl(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ diff --git a/src/soc/intel/xeon_sp/ebg/lockdown.c b/src/soc/intel/xeon_sp/ebg/lockdown.c index 694e4a2..4ced721 100644 --- a/src/soc/intel/xeon_sp/ebg/lockdown.c +++ b/src/soc/intel/xeon_sp/ebg/lockdown.c @@ -13,6 +13,5 @@ { if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { fast_spi_set_bde(); - fast_spi_set_vcl(); } } diff --git a/src/soc/intel/xeon_sp/ibl/lockdown.c b/src/soc/intel/xeon_sp/ibl/lockdown.c index 694e4a2..4ced721 100644 --- a/src/soc/intel/xeon_sp/ibl/lockdown.c +++ b/src/soc/intel/xeon_sp/ibl/lockdown.c @@ -13,6 +13,5 @@ { if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { fast_spi_set_bde(); - fast_spi_set_vcl(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86180c209e2d550c2bac3ace9cc344eabf950af0 Gerrit-Change-Number: 85437 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Support _PRT reporting for domain
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85151?usp=email ) Change subject: soc/intel/xeon_sp: Support _PRT reporting for domain ...................................................................... soc/intel/xeon_sp: Support _PRT reporting for domain acpigen_write_PRT_pre_routed should support _PRT reporting for both domains and PCI root ports. TESTED=Build and boot on intel/avenuecity CRB _PRT will be correctly reported and IRQ routing missing error in dmesg will disappear [ 40.406496] pcieport 0000:14:08.0: can't derive routing for PCI INT A [ 40.413799] pci 0000:17:00.0: PCI INT A: no GSI [ 40.418965] pcieport 0000:14:08.0: can't derive routing for PCI INT A [ 40.426272] ast 0000:18:00.0: PCI INT A: no GSI Change-Id: I07b9ce7b698a0bad30f0a20998a6543101d12542 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85151 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: <yuchi.chen(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved yuchi.chen(a)intel.com: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 0a4587c..9a3c462 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -202,7 +202,7 @@ uint32_t routed_dev_bitmap = 0; char *entry_count; - if (!is_pci_bridge(br)) + if (!dev_is_active_bridge(br)) return; const char *acpi_scope = acpi_device_path(br); -- To view, visit https://review.coreboot.org/c/coreboot/+/85151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07b9ce7b698a0bad30f0a20998a6543101d12542 Gerrit-Change-Number: 85151 Gerrit-PatchSet: 8 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85152?usp=email ) Change subject: soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting ...................................................................... soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting PCI devices not pre-routed will have their interrupt line left as 0. Skip these devices in _PRT reporting. TESTED=Build and boot on intel/avenuecity CRB Change-Id: I3d51b75eb0fd1c4ca877f6ac884de2742e7f9630 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85152 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: <yuchi.chen(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved yuchi.chen(a)intel.com: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 916e2df..0a4587c 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -225,6 +225,8 @@ uint8_t int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); if ((int_pin > PCI_INT_MAX) || (int_pin < PCI_INT_A)) continue; + if (!int_line) + continue; acpigen_write_PRT_GSI_entry(dev_num, int_pin - PCI_INT_A, int_line); -- To view, visit https://review.coreboot.org/c/coreboot/+/85152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d51b75eb0fd1c4ca877f6ac884de2742e7f9630 Gerrit-Change-Number: 85152 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[M] Change in coreboot[main]: soc/intel/alderlake: Add a function to force disable memory channels
by Eric Lai (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford. Eric Lai has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add a function to force disable memory channels ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/9166abbc_80078807?us… : PS1, Line 252: if (ch_disable_mask == 0) { Do we have any invalid combination here? Like we must have Mc0Ch0 at least? Or you cann't disable DisableMc0Ch0 and DisableMc0Ch3 etc.. -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 06:46:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
by Eric Lai (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/85363?usp=email ) Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Gerrit-Change-Number: 85363 Gerrit-PatchSet: 4 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 06:40:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Support _PRT reporting for domain
by Eric Lai (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Eric Lai has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85151?usp=email ) Change subject: soc/intel/xeon_sp: Support _PRT reporting for domain ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85151?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07b9ce7b698a0bad30f0a20998a6543101d12542 Gerrit-Change-Number: 85151 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 06:38:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/common/block: Add const qualifier for input of pirq ops
by Shuo Liu (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Lean Sheng Tan, Patrick Rudolph, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85283?usp=email ) Change subject: soc/intel/common/block: Add const qualifier for input of pirq ops ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/common/block/include/intelblocks/itss.h: https://review.coreboot.org/c/coreboot/+/85283/comment/507ae6bf_74e4fd0b?us… : PS5, Line 51: uint32_t itss_soc_get_on_chip_dev_pir(const struct device *dev); > In my local environment, without coressponding change in SNR, compiler reports the following conflic […] Not sure if this could be filed with a coreboot issue? (and then we ACK this open to move ahead for merging). -- To view, visit https://review.coreboot.org/c/coreboot/+/85283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0 Gerrit-Change-Number: 85283 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 06:35:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Shuo Liu (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 1: Code-Review+1 (7 comments) File src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/85532/comment/4a5d61b2_c87c4083?us… : PS1, Line 4: #include <soc/intel/common/acpi/acpi_wake_source.asl> Not needed for this? https://review.coreboot.org/c/coreboot/+/85532/comment/9684fb42_c587d3d2?us… : PS1, Line 13: } #include <arch/x86/post.asl>? https://review.coreboot.org/c/coreboot/+/85532/comment/b53416eb_ba8f4767?us… : PS1, Line 30: Suppose the sleep/wake is not supported so no needed? File src/mainboard/mitaccomputing/whitestone-2/bootblock.c: https://review.coreboot.org/c/coreboot/+/85532/comment/9beb5462_32207b30?us… : PS1, Line 23: * For that end it is wired into BMC virtual port. Is SUART2 has s port IO map as SUART1? File src/mainboard/mitaccomputing/whitestone-2/mainboard.c: https://review.coreboot.org/c/coreboot/+/85532/comment/be92fc9f_888fe9c9?us… : PS1, Line 46: } Can the common codes be used? smbios_write_type41 https://review.coreboot.org/c/coreboot/+/85532/comment/42c8d4d1_28a000a0?us… : PS1, Line 71: } Will this duplicate with smbios_generate_type41_from_devtree? https://review.coreboot.org/c/coreboot/+/85532/comment/f6ea0711_40d707af?us… : PS1, Line 80: }; How this be invoked? -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 06:24:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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