coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Xiwen Shao, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=build pass, When we encounter a bus hang and hw watchdog causes the platform to restart, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 6 files changed, 177 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 12 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 09 Dec '24

09 Dec '24

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence Uldrenite support WWAN 5G device, use variant.c to handle the power on sequence for WWAN RW350R-GL. BUG=b:381393809 BRANCH=None TEST=emerge-nissa coreboot Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/Makefile.mk A src/mainboard/google/brya/variants/uldrenite/variant.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85537/1 diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index 91f031e..b8b2532 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -3,3 +3,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/uldrenite/variant.c b/src/mainboard/google/brya/variants/uldrenite/variant.c new file mode 100644 index 0000000..25e0076 --- /dev/null +++ b/src/mainboard/google/brya/variants/uldrenite/variant.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <delay.h> + +#define RW350R_RST_DELAY_MS 20 +#define RW350R_PERST_DELAY_MS 30 + +static const struct pad_config rw350r_en_pad[] = { + /* H23 : LTE_PWR_OFF_EN */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), +}; +static const struct pad_config rw350r_rst_pad[] = { + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), +}; +static const struct pad_config rw350r_perst_pad[] = { + /* F13 : PLTRST_WWAN# */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), +}; + +void variant_init(void) +{ + /* + * RW350R power on seuqence: + * De-assert WWAN_EN -> 20ms -> de-assert WWAN_RST -> 30ms -> + * de-assert WWAN_PERST + */ + gpio_configure_pads(rw350r_en_pad, ARRAY_SIZE(rw350r_en_pad)); + mdelay(RW350R_RST_DELAY_MS); + gpio_configure_pads(rw350r_rst_pad, ARRAY_SIZE(rw350r_rst_pad)); + mdelay(RW350R_PERST_DELAY_MS); + gpio_configure_pads(rw350r_perst_pad, ARRAY_SIZE(rw350r_perst_pad)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#11). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=build pass, When we encounter a bus hang and hw watchdog causes the platform to restart, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 6 files changed, 176 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xiwen Shao, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=build pass, When we encounter a bus hang and hw watchdog causes the platform to restart, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/common/include/soc/tracker_common.h M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 7 files changed, 177 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 10 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
by Divagar Mohandass (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Divagar Mohandass has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85536?usp=email ) Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85536?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065 Gerrit-Change-Number: 85536 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 08:50:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Lei Cao (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Lei Cao has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85535?usp=email ) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Dec 2024 08:40:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Angel Pons (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph. Angel Pons has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 1: Code-Review+1 (12 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85532/comment/7f2a0013_aa001d5a?us… : PS1, Line 8: Could you please add a body to the commit message? I would suggest describing the board (looks like it's a single-socket SPR-SP evaluation board) as well as what has been tested. You can use CB:68188 as an example of this structure. File configs/config.mitaccomputing_ws_2: PS1: I see references to site-local here. This config file will get build-tested by Jenkins, so this won't work. But if Jenkins passed, I guess it didn't pick up the file (IIRC, if the beginning of the filename doesn't match the mainboard vendor/name in the way Jenkins expects it, then the file is ignored). Ironically enough, files in `configs/builder/` do *not* get build-tested (unless this has changed). So you can move this config file into `configs/builder/`. https://review.coreboot.org/c/coreboot/+/85532/comment/bee674c2_4920f20a?us… : PS1, Line 15: CONFIG_X2APIC_LATE_WORKAROUND=y Is this needed for all SPR-SP mainboards? File src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/85532/comment/22b8ce6b_aa1fc738?us… : PS1, Line 30: > Suppose the sleep/wake is not supported so no needed? I think these methods might be needed for ASL to compile, but I would prefer removing them if possible. File src/mainboard/mitaccomputing/whitestone-2/board_info.txt: PS1: nit: Missing `ROM package` File src/mainboard/mitaccomputing/whitestone-2/bootblock.c: https://review.coreboot.org/c/coreboot/+/85532/comment/75eb449d_38a09f35?us… : PS1, Line 18: static void enable_espi_lpc_io_windows(void) > Is is possible to use the lpc functions in `src/soc/intel/common/block/lpc/lpc_lib. […] I think that library is for ramstage. Also, other Xeon-SP boards do this. Still, I agree it would be nice to tidy this up, but I feel it would be best to do so in a follow-up. File src/mainboard/mitaccomputing/whitestone-2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85532/comment/2e1a2b8c_038438ee?us… : PS1, Line 5: register "turbo_ratio_limit" = "0x181819191e242424" : register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18" Is this hardcoded for a specific CPU model? File src/mainboard/mitaccomputing/whitestone-2/dsdt.asl: https://review.coreboot.org/c/coreboot/+/85532/comment/f9ae236c_fc002295?us… : PS1, Line 10: 0x20110725 // OEM revision The "OEM revision" comment means this number was chosen to match that of vendor firmware (BIOS/UEFI) for a particular board (on a retrofitted coreboot port). Unfortunately, this got copy-pasted verbatim to other boards without checking if the comment is true. It would be great if you can check this value. But if you can't check it, please remove the comment: ```suggestion 0x20110725 ``` File src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h: https://review.coreboot.org/c/coreboot/+/85532/comment/0c5c82e2_2653ccc0?us… : PS1, Line 48: CFG_UPD_PCIE_PORT(1, 0, 0) Idea: you could add this macro ``` #define CFG_UPD_PCIE_PORT_DISABLED CFG_UPD_PCIE_PORT(1, 0, 0) ``` and then do ```suggestion CFG_UPD_PCIE_PORT_DISABLED, ``` so that it's easier to see which ports are enabled/disabled. File src/mainboard/mitaccomputing/whitestone-2/mainboard.c: https://review.coreboot.org/c/coreboot/+/85532/comment/b6406a31_2932baa5?us… : PS1, Line 46: } > Can the common codes be used? smbios_write_type41 These E810 devices are Ethernet NICs. I think they are on-board and you want them to have consistent numbering in the OS, is this correct? The simplest thing you can do is declare them in the devicetree, so that coreboot autogenerates SMBIOS Type41 entries for them. If you need to assign specific numbers to specific devices, you can do something like CB:58628 to be able to manually specify numbers. https://review.coreboot.org/c/coreboot/+/85532/comment/c2993165_227d047e?us… : PS1, Line 80: }; > How this be invoked? It's invoked automatically File src/mainboard/mitaccomputing/whitestone-2/romstage.c: https://review.coreboot.org/c/coreboot/+/85532/comment/aed8bda5_ce1fcfd8?us… : PS1, Line 18: Protocl typo ```suggestion /* eg. Protocol Auto Negotiation */ ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 1 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 08:14:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
by Subrata Banik (Code Review) 09 Dec '24

09 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85536?usp=email ) Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming ...................................................................... soc/intel/ptl: Enable UFS functionality by adding IRQ programming This commit adds the necessary IRQ programming for the UFS controller, addressing an issue where the device was not operational after booting to the OS. BUG=b:382243957 TEST=Built and booted google/fatcat successfully, verifying UFS functionality. Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/fsp_params.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85536/1 diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index e0b0adf..dfc47c6 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -199,6 +199,14 @@ ANY_PIRQ(PCI_DEVFN_CSE_4), }, }, +#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) + { + .slot = PCI_DEV_SLOT_UFS, + .fns = { + ANY_PIRQ(PCI_DEVFN_UFS), + }, + }, +#endif { .slot = PCI_DEV_SLOT_SIO1, .fns = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85536?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065 Gerrit-Change-Number: 85536 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85535?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters The DPTF parameters were defined by the thermal team. Based on thermal table in b:383032918#comment1 BUG=b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 125 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85535/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Rui Zhou (Code Review) 09 Dec '24

09 Dec '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85535?usp=email ) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters The DPTF parameters were defined by the thermal team. Based on thermal table in b:383032918#comment1 BUG=b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 125 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85535/1 diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d51fe0b..43ce61b 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -157,23 +157,23 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 15000, + .max_power = 6000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -195,9 +195,125 @@ [3] = { 8, 500 } }" - device generic 0 on end + device generic 0 on + probe THERMAL THERMAL_6W + end + end + + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU_VR"" + register "options.tsr[1].desc" = ""CPU"" + register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(54, 64), + TEMP_PCT(52, 52), + TEMP_PCT(50, 44), + TEMP_PCT(48, 38), + TEMP_PCT(45, 34), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(90, 90), + TEMP_PCT(85, 80), + TEMP_PCT(75, 70), + TEMP_PCT(70, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(75, 80), + TEMP_PCT(70, 70), + TEMP_PCT(65, 50), + } + } + }" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 6000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2000 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 4000, 220, 1640, }, + [1] = { 90, 3700, 220, 1640, }, + [2] = { 80, 3500, 180, 1310, }, + [3] = { 70, 3300, 145, 1030, }, + [4] = { 60, 3100, 115, 765, }, + [5] = { 50, 2800, 90, 545, }, + [6] = { 40, 2500, 55, 365, }, + [7] = { 30, 2100, 30, 220, }, + [8] = { 20, 1500, 15, 120, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + device generic 1 on + probe THERMAL THERMAL_15W + end end end + device ref igpu on chip drivers/gfx/generic register "device_count" = "4" -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

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