Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85528?usp=email )
Change subject: soc/intel/pantherlake: Fix UFS ACPI _ADR calculation
......................................................................
soc/intel/pantherlake: Fix UFS ACPI _ADR calculation
This patch corrects the calculation of the _ADR value for the Intel UFS
controller in the `soc/ufs.h` header file.
The previous calculation incorrectly included a hardcoded value (0x0007)
in the lower bits of the _ADR. This is not in line with the Panther Lake
EDS specification (doc: 815002)
BUG=b:382243957
TEST=Able to build and boot google/fatcat.
> iasl -d /sys/firmware/acpi/tables/DSDT
Device (UFS)
{
Name (_ADR, 0x00170000) // _ADR: Address
Name (_DDN, "UFS Controller") // _DDN: DOS Device Name
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/pantherlake/include/soc/ufs.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85528/1
diff --git a/src/soc/intel/pantherlake/include/soc/ufs.h b/src/soc/intel/pantherlake/include/soc/ufs.h
index ffd9b1f..e5a87e6 100644
--- a/src/soc/intel/pantherlake/include/soc/ufs.h
+++ b/src/soc/intel/pantherlake/include/soc/ufs.h
@@ -11,7 +11,7 @@
#include <soc/pci_devs.h>
/* Calculate _ADR for Intel UFS Controller */
-#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16 | 0x0007)
+#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16)
#define R_SCS_CFG_PCS 0x84
#define R_SCS_CFG_PG_CONFIG 0xA2
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85526?usp=email )
Change subject: soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
......................................................................
soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
This patch corrects the conditional inclusion of the `ufs.asl` file in
the southbridge ACPI configuration.
Previously, the inclusion of `ufs.asl` was incorrectly dependent on the
`MAINBOARD_USES_IFD_GBE_REGION` Kconfig option. This prevented the UFS
ACPI entry from being included in the DSDT when
`MAINBOARD_USES_IFD_GBE_REGION` was disabled, causing issues with
booting from UFS media.
This commit fixes the issue by ensuring that `ufs.asl` is included
based on the `SOC_INTEL_PANTHERLAKE_U_H` Kconfig option, which correctly
reflects the presence of UFS hardware.
This change ensures that the UFS ACPI device is correctly enumerated and
available to the operating system.
BUG=b:382243957
TEST=Able to verify UFS ACPI device is available inside DSDT table.
Change-Id: Ic8e87c57dd2db30f0ba13ac0a9f7fd2db877039a
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85526
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
---
M src/soc/intel/pantherlake/acpi/southbridge.asl
1 file changed, 1 insertion(+), 2 deletions(-)
Approvals:
Kapil Porwal: Looks good to me, approved
Elyes Haouas: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/intel/pantherlake/acpi/southbridge.asl b/src/soc/intel/pantherlake/acpi/southbridge.asl
index c047a71..a6cdda3 100644
--- a/src/soc/intel/pantherlake/acpi/southbridge.asl
+++ b/src/soc/intel/pantherlake/acpi/southbridge.asl
@@ -47,10 +47,9 @@
/* GbE 0:1f.6 */
#if CONFIG(MAINBOARD_USES_IFD_GBE_REGION)
#include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
+#endif
/* UFS 0:17:0 */
#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H)
#include <soc/intel/common/block/acpi/acpi/ufs.asl>
#endif
-
-#endif
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
File src/soc/intel/xeon_sp/lpc_gen1.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/f00ae877_81259da5?us… :
PS9, Line 15: }
Will ioapic0 be created in device tree in another patch later?
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/91826f26_a145a69a?us… :
PS4, Line 47: }
> It cannot be assigned, can it? […]
I guess other GSI assignment rules should be possible, but for _PRT alignment, the revised formula looks clearer. Maybe to assert (dn.stack <= 5) as well?
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Change subject: soc/intel/xeon_sp: Add PCU PCI drivers
......................................................................
Patch Set 9: Code-Review+2
(1 comment)
Patchset:
PS7:
> Depends on https://review.coreboot. […]
Acknowledged
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Change subject: mb/ocp/tiogapass: Wait for BMC
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/mainboard/ocp/tiogapass/romstage.c:
https://review.coreboot.org/c/coreboot/+/85492/comment/8986361b_86a931a6?us… :
PS2, Line 60: static const long timeout = 180 * 1000;
> I would suggest making this a Kconfig just in case
Is GPP_F4 is purposed as a 'BMC ready' signal or a generic purpose signal in tiogapass? Is the usage of GPP_F4 as 'BMC ready' sign depends on specific version of BMC firmware in tiogapass?
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Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
Should this one merged with https://review.coreboot.org/c/coreboot/+/85505?
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Change subject: soc/intel/xeon_sp: Introduce early_pch_init
......................................................................
Patch Set 3: Code-Review+2
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