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Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
......................................................................
mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
The issue does not occur on Karis due to different WIFI module type
with current projects, Karis is using M.2 (none solder down version).
The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102.
BUG=b:374205496
TEST=Boot to OS and then check link speed.
Use command: lspci -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85520/5
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Change subject: drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84990/comment/059f258b_6191eded?us… :
PS3, Line 11:
Did Linux log an error before?
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Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85520/comment/2d6a22b4_d616affe?us… :
PS3, Line 10:
> > The issue does not occur on Karis due to different WIFI module type with current projects, Karis i […]
I don’t see the updated commit message yet. It’d be great if you could do this.
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Change subject: soc/intel/alderlake: Add support for PCIe speed setting
......................................................................
Patch Set 4:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/85519/comment/45263e93_ad3e8ac3?us… :
PS4, Line 61: PCIE
PCIe
https://review.coreboot.org/c/coreboot/+/85519/comment/aaf44106_2bb6564d?us… :
PS4, Line 84: Pcie
PCIe as above.
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Change subject: device/pci_ids: Add new Intel PTL device IDs for DID2
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85525/comment/3c00b9a4_f0d7fc67?us… :
PS1, Line 7: IDs
Singular, as you only add one?
https://review.coreboot.org/c/coreboot/+/85525/comment/9daa6785_f9c9b26f?us… :
PS1, Line 7: Add new Intel PTL device IDs for DID2
As the prefix says `pci_ids` maybe just:
> Add Pantherlake-H GT2 (DID2)
https://review.coreboot.org/c/coreboot/+/85525/comment/7488cac0_ef6e1604?us… :
PS1, Line 9: This patch adds new DID2 PCI device ID for Intel PTL.
Where did you get the id from?
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Change subject: Documentation: Remove out-of-date or obsolete text
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
Patchset:
PS4:
Two patches would make the commit message summary easier to write. ;-)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84778/comment/bbdfca9f_098ea7ce?us… :
PS4, Line 7: Remove out-of-date or obsolete text
… from ideas and GSoC pages
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Change subject: drivers/usb/intel_bluetooth: Change the Power Resource to S0
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84988/comment/be57ad35_43e7384a?us… :
PS4, Line 9: is
"is" => "to"
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Change subject: drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0
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Patch Set 3: Code-Review+2
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