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Change subject: soc/intel/xeon_sp: Improve IRQ routing for Gen6
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Patch Set 10: Code-Review+1
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Change subject: soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq
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Patch Set 5: Code-Review+2
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Change subject: soc/intel/common/block: Add const qualifier for input of pirq ops
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Patch Set 5: Code-Review+2
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Change subject: soc/intel/xeon_sp: Support _PRT reporting for domain
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Patch Set 7: Code-Review+2
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Change subject: soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting
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Patch Set 6: Code-Review+2
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Change subject: soc/intel/xeon_sp: Use pre-processor to define ASL handler names
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Patch Set 8: Code-Review+2
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Change subject: Documentation: Remove out-of-date or obsolete text
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Patch Set 4:
(6 comments)
This change is ready for review.
Commit Message:
https://review.coreboot.org/c/coreboot/+/84778/comment/f76d89dc_cd0e9b62?us… :
PS1, Line 7: /
> Remove?
Done
https://review.coreboot.org/c/coreboot/+/84778/comment/b488c1b0_4b3e7209?us… :
PS1, Line 7: from docs
> Redundant as in prefix.
Done
https://review.coreboot.org/c/coreboot/+/84778/comment/dd3cb1d5_a4b4736d?us… :
PS1, Line 7: text
> Please be more specific. Maybe: […]
Done
https://review.coreboot.org/c/coreboot/+/84778/comment/58871464_ad0c152f?us… :
PS1, Line 8:
> Please elaborate, why it’s obsolete.
Done
File Documentation/developer/contributing/documentation_ideas.md:
https://review.coreboot.org/c/coreboot/+/84778/comment/cccee05d_ecf6792b?us… :
PS1, Line 16: ## Restructure Existing Documentation
> Why is that obsolete?
Sorry, I hadn't explained in the previous patchset commit message - this patch will come after a patch to restructure the documentation dirs.
File Documentation/developer/contributing/gsoc.md:
https://review.coreboot.org/c/coreboot/+/84778/comment/73e2cffe_eb7f0f5c?us… :
PS1, Line 264: Tim Wawrzynczak
: * Raul Rangel
: * Ron Minnich
> Instead of removing the whole thing, rather just add a place holder.
Done
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Change subject: soc/intel/alderlake: Add support for PCIe speed setting
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Patch Set 3: Code-Review+1
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/85519/comment/54969c4b_a60acc9f?us… :
PS3, Line 85: Pcie_Speed_control
i would request to avoid camel casing if possible
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