coreboot-gerrit December 2024

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[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by David Wu (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. David Wu has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email ) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/85519/comment/5ec38c88_6a07af65?us… : PS1, Line 74: /* PCIE RP Pcie Speed. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 */ > can you please define these as ENUM ? so, we could use the same into device tree Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Dec 2024 16:11:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by David Wu (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85519?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... soc/intel/alderlake: Add support for PCIe speed setting This change provides config for devicetree to control PCIe speed BUG=b:374205496 TEST=build pass Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85519/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by David Wu (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85520?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 Set PCIe root port 4 speed to Gen2 for WIFI 7 BUG=b:374205496 TEST=Boot to OS and then check link speed. Use command: lspci -vv | grep 'LnkSta' Before LnkSta: Speed 8GT/s (downgraded), Width x1 After LnkSta: Speed 5GT/s (downgraded), Width x1 Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/riven/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85520/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[M] Change in coreboot[main]: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
by Felix Singer (Code Review) 06 Dec '24

06 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82898?usp=email ) Change subject: soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU ...................................................................... soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU The CSE MKHI_BUP_COMMON_GET_BOOT_PERF_DATA command is also implemented in non-Lite CSE SKUs. Original CL [1] adding this feature also says that, but at that point the feature was validated for CSE Lite only. Move cse_get_boot_performance_data() to shared blk/cse/telemetry.c to have it compile for mainboards without CSE Lite. TEST=Boot NovaCustom V540TU (MTL-P / ME Consumer) with SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 selected and check `cbmem -t`: 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 34,000 945:CSE started to handle ICC configuration 172,000 (138,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 172,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 314,000 (142,000) 991:Die Management Unit (DMU) load completed 360,000 (46,000) 0:1st timestamp 385,844 (25,844) 11:start of bootblock 398,796 (12,952) 12:end of bootblock 402,099 (3,302) [...] [1]: https://review.coreboot.org/c/coreboot/+/59507 Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82898 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/cse/telemetry.c 3 files changed, 31 insertions(+), 30 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Krystian Hebel: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 0b518c3..657494a 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -294,7 +294,7 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY def_bool n - depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD + depends on !SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data. diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 09281ab..76e0853 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -60,35 +60,6 @@ printk(BIOS_ERR, "ME: Write protection for CSE RO is not enabled\n"); } -enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) -{ - struct cse_boot_perf_req { - struct mkhi_hdr hdr; - uint32_t reserved; - } __packed; - - struct cse_boot_perf_req req = { - .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, - .hdr.command = MKHI_BUP_COMMON_GET_BOOT_PERF_DATA, - .reserved = 0, - }; - - size_t resp_size = sizeof(struct cse_boot_perf_rsp); - - if (heci_send_receive(&req, sizeof(req), boot_perf_rsp, &resp_size, - HECI_MKHI_ADDR)) { - printk(BIOS_ERR, "cse_lite: Could not get boot performance data\n"); - return CB_ERR; - } - - if (boot_perf_rsp->hdr.result) { - printk(BIOS_ERR, "cse_lite: Get boot performance data resp failed: %d\n", - boot_perf_rsp->hdr.result); - return CB_ERR; - } - - return CB_SUCCESS; -} static const struct cse_bp_info *cse_get_bp_info_from_rsp(void) { diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index c1c70e5..2c9fb54 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -6,6 +6,36 @@ #define MSEC_TO_USEC(x) (x * 1000) +enum cb_err cse_get_boot_performance_data(struct cse_boot_perf_rsp *boot_perf_rsp) +{ + struct cse_boot_perf_req { + struct mkhi_hdr hdr; + uint32_t reserved; + } __packed; + + struct cse_boot_perf_req req = { + .hdr.group_id = MKHI_GROUP_ID_BUP_COMMON, + .hdr.command = MKHI_BUP_COMMON_GET_BOOT_PERF_DATA, + .reserved = 0, + }; + + size_t resp_size = sizeof(struct cse_boot_perf_rsp); + + if (heci_send_receive(&req, sizeof(req), boot_perf_rsp, &resp_size, + HECI_MKHI_ADDR)) { + printk(BIOS_ERR, "cse: Could not get boot performance data\n"); + return CB_ERR; + } + + if (boot_perf_rsp->hdr.result) { + printk(BIOS_ERR, "cse: Get boot performance data resp failed: %d\n", + boot_perf_rsp->hdr.result); + return CB_ERR; + } + + return CB_SUCCESS; +} + static void process_cse_telemetry_data(void) { struct cse_boot_perf_rsp cse_perf_data; -- To view, visit https://review.coreboot.org/c/coreboot/+/82898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a5b1abd282af9af33cef2371719df4133684a2e Gerrit-Change-Number: 82898 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include
by Felix Singer (Code Review) 06 Dec '24

06 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82674?usp=email ) Change subject: soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include ...................................................................... soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include This change fixes building NovaCustom V540TU, which previously errored out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition. Replace soc/gpio_defs.h with gpio.h which includes everything we need, same as it was done for ADL in change 71266, and other SoCs. TEST=Build and boot NovaCustom V540TU Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82674 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/soc/intel/meteorlake/acpi/gpio.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Kapil Porwal: Looks good to me, approved Michał Żygowski: Looks good to me, approved Krystian Hebel: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/acpi/gpio.asl b/src/soc/intel/meteorlake/acpi/gpio.asl index 440ee75..effc4d2 100644 --- a/src/soc/intel/meteorlake/acpi/gpio.asl +++ b/src/soc/intel/meteorlake/acpi/gpio.asl @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio_defs.h> +#include <gpio.h> #include <soc/intel/common/acpi/gpio.asl> #include <soc/intel/common/block/acpi/acpi/gpio_op.asl> #include <soc/irq.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e Gerrit-Change-Number: 82674 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: ec/dasharo/ec: add Dasharo features
by Felix Singer (Code Review) 06 Dec '24

06 Dec '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82672?usp=email ) Change subject: ec/dasharo/ec: add Dasharo features ...................................................................... ec/dasharo/ec: add Dasharo features - Setting battery thresholds - PEP hooks for S0ix - Remove unused keyboard backlight, OLED, FCMD, ACPI power button device Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82672 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/ec/dasharo/ec/Kconfig M src/ec/dasharo/ec/Makefile.mk A src/ec/dasharo/ec/acpi.h M src/ec/dasharo/ec/acpi/buttons.asl A src/ec/dasharo/ec/acpi/dasharo.asl M src/ec/dasharo/ec/acpi/ec.asl M src/ec/dasharo/ec/acpi/ec_ram.asl M src/ec/dasharo/ec/acpi/lid.asl D src/ec/dasharo/ec/acpi/s76.asl A src/ec/dasharo/ec/buttons.c A src/ec/dasharo/ec/commands.h M src/ec/dasharo/ec/dasharo_ec.c D src/ec/dasharo/ec/dasharo_ec.h D src/ec/dasharo/ec/smbios.c 14 files changed, 302 insertions(+), 332 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve diff --git a/src/ec/dasharo/ec/Kconfig b/src/ec/dasharo/ec/Kconfig index 1a007fa..901d3ce 100644 --- a/src/ec/dasharo/ec/Kconfig +++ b/src/ec/dasharo/ec/Kconfig @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only config EC_DASHARO_EC + select EC_ACPI bool help Dasharo EC @@ -15,7 +16,16 @@ bool default n -config EC_DASHARO_EC_OLED +config EC_DASHARO_EC_UPDATE depends on EC_DASHARO_EC - bool + bool "Update the embedded controller firmware" default n + +config EC_DASHARO_EC_UPDATE_FILE + depends on EC_DASHARO_EC_UPDATE + string "Path to the EC update file" + default "ec.rom" + +config EC_DASHARO_EC_FLASH_SIZE + hex + default 0x20000 diff --git a/src/ec/dasharo/ec/Makefile.mk b/src/ec/dasharo/ec/Makefile.mk index 247bcd4..d71a2fd 100644 --- a/src/ec/dasharo/ec/Makefile.mk +++ b/src/ec/dasharo/ec/Makefile.mk @@ -1,10 +1,9 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only + ifeq ($(CONFIG_EC_DASHARO_EC),y) all-y += dasharo_ec.c - -ramstage-y += smbios.c - +all-y += buttons.c smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c endif diff --git a/src/ec/dasharo/ec/acpi.h b/src/ec/dasharo/ec/acpi.h new file mode 100644 index 0000000..35d7279 --- /dev/null +++ b/src/ec/dasharo/ec/acpi.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EC_DASHARO_EC_ACPI_H +#define EC_DASHARO_EC_ACPI_H + +#include <ec/acpi/ec.h> + +#define DASHARO_EC_REG_LSTE 0x03 +#define DASHARO_EC_REG_LSTE_LID_STATE 0x01 + +#define DASHARO_EC_REG_BATTERY_START_THRESHOLD 0xBC +#define DASHARO_EC_REG_BATTERY_STOP_THRESHOLD 0xBD + +int dasharo_ec_get_lid_state(void); + +enum bat_threshold_type { + BAT_THRESHOLD_START, + BAT_THRESHOLD_STOP +}; + +int dasharo_ec_get_bat_threshold(enum bat_threshold_type type); +void dasharo_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value); + +#endif /* EC_DASHARO_EC_ACPI_H */ diff --git a/src/ec/dasharo/ec/acpi/buttons.asl b/src/ec/dasharo/ec/acpi/buttons.asl index ae85c67..d69f4bb 100644 --- a/src/ec/dasharo/ec/acpi/buttons.asl +++ b/src/ec/dasharo/ec/acpi/buttons.asl @@ -1,11 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Device (PWRB) -{ - Name (_HID, EisaId ("PNP0C0C")) - Name (_PRW, Package () { EC_GPE_SWI, 3 }) -} - Device (SLPB) { Name (_HID, EisaId ("PNP0C0E")) diff --git a/src/ec/dasharo/ec/acpi/dasharo.asl b/src/ec/dasharo/ec/acpi/dasharo.asl new file mode 100644 index 0000000..a94da6a --- /dev/null +++ b/src/ec/dasharo/ec/acpi/dasharo.asl @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (DASH) { + Name (_HID, "DSHR4543") + Name (_UID, 0) + // Hide the device so that Windows does not warn about a missing driver. + Name (_STA, 0xB) + + Method (INIT, 0, Serialized) { + Printf ("DASH: INIT") + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use software control + ^^PCI0.LPCB.EC0.ECOS = 2 + Return (0) + } Else { + Return (1) + } + } + + Method (FINI, 0, Serialized) { + Printf ("DASH: FINI") + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use hardware control + ^^PCI0.LPCB.EC0.ECOS = 1 + Return (0) + } Else { + Return (1) + } + } + + // Fan names + Method (NFAN, 0, Serialized) { + Return (Package() { + "CPU fan", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU fan", +#endif + }) + } + + // Get fan duty cycle and RPM as a single value + Method (GFAN, 1, Serialized) { + Local0 = 0 + Local1 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.DUT1 + Local1 = ^^PCI0.LPCB.EC0.RPM1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.DUT2 + Local1 = ^^PCI0.LPCB.EC0.RPM2 + } + } + If (Local1 != 0) { + // 60 * (EC frequency / 120) / 2 + Local1 = 2156250 / Local1 + } + Return ((Local1 << 8) | Local0) + } + + // Temperature names + Method (NTMP, 0, Serialized) { + Return (Package() { + "CPU temp", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU temp", +#endif + }) + } + + // Get temperature + Method (GTMP, 1, Serialized) { + Local0 = 0; + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.TMP1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.TMP2 + } + } + Return (Local0) + } +} diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl index e4fcdeb..e13c52d 100644 --- a/src/ec/dasharo/ec/acpi/ec.asl +++ b/src/ec/dasharo/ec/acpi/ec.asl @@ -6,7 +6,7 @@ #include "buttons.asl" #include "hid.asl" #include "lid.asl" - #include "s76.asl" + #include "dasharo.asl" } Device (\_SB.PCI0.LPCB.EC0) @@ -36,7 +36,7 @@ { Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1)) If ((Arg0 == 0x03) && (Arg1 == 1)) { - // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys + // Enable hardware touchpad lock and airplane mode keys ECOS = 1 // Enable software display brightness keys @@ -56,9 +56,6 @@ // EC is now available ECOK = Arg1 - - // Reset Dasharo Device - ^^^^S76D.RSET() } } @@ -93,6 +90,20 @@ } } + Method (S0IX, 1, Serialized) { + Printf ("EC: S0ix hook") + If (ECOK) { + S0XH = Arg0 + } + } + + Method (EDSX, 1, Serialized) { + Printf ("EC: Display hook") + If (ECOK) { + DSPH = Arg0 + } + } + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle { Printf ("EC: Touchpad Toggle") @@ -101,9 +112,6 @@ Method (_Q0B, 0, NotSerialized) // Screen Toggle { Printf ("EC: Screen Toggle") -#if CONFIG(EC_DASHARO_EC_OLED) - Notify (^^^^S76D, 0x85) -#endif // CONFIG(EC_DASHARO_EC_OLED) } Method (_Q0C, 0, NotSerialized) // Mute @@ -111,11 +119,6 @@ Printf ("EC: Mute") } - Method (_Q0D, 0, NotSerialized) // Keyboard Backlight - { - Printf ("EC: Keyboard Backlight") - } - Method (_Q0E, 0, NotSerialized) // Volume Down { Printf ("EC: Volume Down") @@ -209,30 +212,12 @@ Method (_Q1D, 0, NotSerialized) // Power Button { Printf ("EC: Power Button") - Notify (PWRB, 0x80) } Method (_Q50, 0, NotSerialized) // Other Events { Local0 = OEM4 - If (Local0 == 0x8A) { - Printf ("EC: White Keyboard Backlight") - Notify (^^^^S76D, 0x80) - } ElseIf (Local0 == 0x9F) { - Printf ("EC: Color Keyboard Toggle") - Notify (^^^^S76D, 0x81) - } ElseIf (Local0 == 0x81) { - Printf ("EC: Color Keyboard Down") - Notify (^^^^S76D, 0x82) - } ElseIf (Local0 == 0x82) { - Printf ("EC: Color Keyboard Up") - Notify (^^^^S76D, 0x83) - } ElseIf (Local0 == 0x80) { - Printf ("EC: Color Keyboard Color Change") - Notify (^^^^S76D, 0x84) - } Else { - Printf ("EC: Other: %o", ToHexString(Local0)) - } + Printf ("EC: Other: %o", ToHexString(Local0)) } #if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS) diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl index cb5bcf1..0087377 100644 --- a/src/ec/dasharo/ec/acpi/ec_ram.asl +++ b/src/ec/dasharo/ec/acpi/ec_ram.asl @@ -45,11 +45,7 @@ Offset (0xD9), AIRP, 8, // Airplane mode LED WINF, 8, // Enable ACPI brightness controls - Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, - FBF3, 8, + Offset (0xE0), + S0XH, 1, // S0ix hook + DSPH, 1, // Display hook } diff --git a/src/ec/dasharo/ec/acpi/lid.asl b/src/ec/dasharo/ec/acpi/lid.asl index 0a64341..45e646a 100644 --- a/src/ec/dasharo/ec/acpi/lid.asl +++ b/src/ec/dasharo/ec/acpi/lid.asl @@ -6,16 +6,16 @@ Name (_PRW, Package () { EC_GPE_SWI, 3 }) Method (_LID, 0, NotSerialized) { - Printf ("LID: _LID") + DEBUG = "LID: _LID" If (^^PCI0.LPCB.EC0.ECOK) { Return (^^PCI0.LPCB.EC0.LSTE) } Else { - Return (1) + Return (One) } } Method (_PSW, 1, NotSerialized) { - Printf ("LID: _PSW: %o", ToHexString(Arg0)) + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) If (^^PCI0.LPCB.EC0.ECOK) { ^^PCI0.LPCB.EC0.LWKE = Arg0 } diff --git a/src/ec/dasharo/ec/acpi/s76.asl b/src/ec/dasharo/ec/acpi/s76.asl deleted file mode 100644 index f23f857..0000000 --- a/src/ec/dasharo/ec/acpi/s76.asl +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Notifications: -// 0x80 - hardware backlight toggle -// 0x81 - backlight toggle -// 0x82 - backlight down -// 0x83 - backlight up -// 0x84 - backlight color change -// 0x85 - OLED screen toggle -Device (S76D) { - Name (_HID, "17761776") - Name (_UID, 0) - // Hide the device so that Windows does not warn about a missing driver. - Name (_STA, 0xB) - - Method (RSET, 0, Serialized) { - Printf ("S76D: RSET") - SAPL(0) - SKBB(0) - SKBC(0xFFFFFF) - } - - Method (INIT, 0, Serialized) { - Printf ("S76D: INIT") - RSET() - If (^^PCI0.LPCB.EC0.ECOK) { - // Set flags to use software control - ^^PCI0.LPCB.EC0.ECOS = 2 - Return (0) - } Else { - Return (1) - } - } - - Method (FINI, 0, Serialized) { - Printf ("S76D: FINI") - RSET() - If (^^PCI0.LPCB.EC0.ECOK) { - // Set flags to use hardware control - ^^PCI0.LPCB.EC0.ECOS = 1 - Return (0) - } Else { - Return (1) - } - } - - // Get Airplane LED - Method (GAPL, 0, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - If (^^PCI0.LPCB.EC0.AIRP & 0x40) { - Return (1) - } - } - Return (0) - } - - // Set Airplane LED - Method (SAPL, 1, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0) { - ^^PCI0.LPCB.EC0.AIRP |= 0x40 - } Else { - ^^PCI0.LPCB.EC0.AIRP &= 0xBF - } - } - } - - // Get Keyboard Backlight Kind - // 0 - No backlight - // 1 - White backlight - // 2 - RGB backlight - Method (GKBK, 0, Serialized) { - Local0 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 2 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - Local0 = ^^PCI0.LPCB.EC0.FBUF - } - Return (Local0) - } - - // Get Keyboard Brightness - Method (GKBB, 0, Serialized) { - Local0 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 1 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - Local0 = ^^PCI0.LPCB.EC0.FBUF - } - Return (Local0) - } - - // Set Keyboard Brightness - Method (SKBB, 1, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 0 - ^^PCI0.LPCB.EC0.FBUF = Arg0 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - } - } - - // Get Keyboard Color - Method (GKBC, 0, Serialized) { - Local0 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 4 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - Local0 = ^^PCI0.LPCB.EC0.FBUF - Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16 - Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8 - } - Return (Local0) - } - - // Set Keyboard Color - Method (SKBC, 1, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 3 - ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) - ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) - ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) - ^^PCI0.LPCB.EC0.FCMD = 0xCA - } - } - - // Fan names - Method (NFAN, 0, Serialized) { - Return (Package() { - "CPU fan", -#if CONFIG(EC_DASHARO_EC_DGPU) - "GPU fan", -#endif - }) - } - - // Get fan duty cycle and RPM as a single value - Method (GFAN, 1, Serialized) { - Local0 = 0 - Local1 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0 == 0) { - Local0 = ^^PCI0.LPCB.EC0.DUT1 - Local1 = ^^PCI0.LPCB.EC0.RPM1 - } ElseIf (Arg0 == 1) { - Local0 = ^^PCI0.LPCB.EC0.DUT2 - Local1 = ^^PCI0.LPCB.EC0.RPM2 - } - } - If (Local1 != 0) { - // 60 * (EC frequency / 120) / 2 - Local1 = 2156250 / Local1 - } - Return ((Local1 << 8) | Local0) - } - - // Temperature names - Method (NTMP, 0, Serialized) { - Return (Package() { - "CPU temp", -#if CONFIG(EC_DASHARO_EC_DGPU) - "GPU temp", -#endif - }) - } - - // Get temperature - Method (GTMP, 1, Serialized) { - Local0 = 0; - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0 == 0) { - Local0 = ^^PCI0.LPCB.EC0.TMP1 - } ElseIf (Arg0 == 1) { - Local0 = ^^PCI0.LPCB.EC0.TMP2 - } - } - Return (Local0) - } -} diff --git a/src/ec/dasharo/ec/buttons.c b/src/ec/dasharo/ec/buttons.c new file mode 100644 index 0000000..d5a5ef4 --- /dev/null +++ b/src/ec/dasharo/ec/buttons.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/acpi/ec.h> + +#include "acpi.h" + +/** + * Return the state of lid switch. + * + * @return 1 if the lid is open. + */ +int dasharo_ec_get_lid_state(void) +{ + return ec_read(DASHARO_EC_REG_LSTE) & DASHARO_EC_REG_LSTE_LID_STATE; +} diff --git a/src/ec/dasharo/ec/commands.h b/src/ec/dasharo/ec/commands.h new file mode 100644 index 0000000..0fe7db4 --- /dev/null +++ b/src/ec/dasharo/ec/commands.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> + +// SMFI commands + +// Indicates that EC is ready to accept commands +#define CMD_NONE 0 +// Probe for Dasharo EC protocol +#define CMD_PROBE 1 +// Read board string +#define CMD_BOARD 2 +// Read version string +#define CMD_VERSION 3 +// Write bytes to console +#define CMD_PRINT 4 +// Access SPI chip +#define CMD_SPI 5 +// Reset EC +#define CMD_RESET 6 +// Get fan speeds +#define CMD_FAN_GET 7 +// Set fan speeds +#define CMD_FAN_SET 8 +// Get keyboard map index +#define CMD_KEYMAP_GET 9 +// Set keyboard map index +#define CMD_KEYMAP_SET 10 +// Get LED value by index +#define CMD_LED_GET_VALUE 11 +// Set LED value by index +#define CMD_LED_SET_VALUE 12 +// Get LED color by index +#define CMD_LED_GET_COLOR 13 +// Set LED color by index +#define CMD_LED_SET_COLOR 14 +// Get LED matrix mode and speed +#define CMD_LED_GET_MODE 15 +// Set LED matrix mode and speed +#define CMD_LED_SET_MODE 16 +// Get key matrix state +#define CMD_MATRIX_GET 17 +// Save LED settings to ROM +#define CMD_LED_SAVE 18 +// Enable/disable no input mode +#define CMD_SET_NO_INPUT 19 +// Set fan curve +#define CMD_FAN_CURVE_SET 20 +// Get security state +#define CMD_SECURITY_GET 21, +// Set security state +#define CMD_SECURITY_SET 22, +// Set camera enablement +#define CMD_CAMERA_ENABLEMENT_SET 23 +// Set WiFi + Bluetooth card enablement +#define CMD_WIFI_BT_ENABLEMENT_SET 24 +// Get a persistent option by index +#define CMD_OPTION_GET 25 +// Set a persistent option by index +#define CMD_OPTION_SET 26 + +// Print command. Registers are unique for each command +#define CMD_PRINT_REG_FLAGS 2 +#define CMD_PRINT_REG_LEN 3 +#define CMD_PRINT_REG_DATA 4 + +// SPI command +// Read from SPI chip if set, write otherwise +#define CMD_SPI_FLAG_READ BIT(0) +// Disable SPI chip after executing command +#define CMD_SPI_FLAG_DISABLE BIT(1) +// Run firmware from scratch RAM if necessary +#define CMD_SPI_FLAG_SCRATCH BIT(2) +// Write to backup ROM instead +#define CMD_SPI_FLAG_BACKUP BIT(3) + +#define CMD_LED_INDEX_ALL 0xFF + +// Persistent option definitions +enum { + OPT_POWER_ON_AC = 0, + NUM_OPTIONS +}; + +uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data); +uint8_t dasharo_ec_read_version(uint8_t *data); +uint8_t dasharo_ec_read_board(uint8_t *data); diff --git a/src/ec/dasharo/ec/dasharo_ec.c b/src/ec/dasharo/ec/dasharo_ec.c index 97c9613..571c6a0 100644 --- a/src/ec/dasharo/ec/dasharo_ec.c +++ b/src/ec/dasharo/ec/dasharo_ec.c @@ -1,31 +1,30 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "dasharo_ec.h" +#include <bootstate.h> #include <arch/io.h> -#include <console/dasharo_ec.h> -#include <console/console.h> +#include <cbfs.h> +#include <console/system76_ec.h> +#include <pc80/mc146818rtc.h> +#include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> #include <timer.h> +#include "acpi.h" +#include "commands.h" // This is the command region for Dasharo EC firmware. It must be // enabled for LPC in the mainboard. #define DASHARO_EC_BASE 0x0E00 #define DASHARO_EC_SIZE 256 -#define REG_CMD 0 +#define SPI_SECTOR_SIZE 1024 + +#define REG_CMD 0 #define REG_RESULT 1 -#define REG_DATA 2 // Start of command data +#define REG_DATA 2 // Start of command data // When command register is 0, command is complete #define CMD_FINISHED 0 -#define RESULT_OK 0 - -// Print command. Registers are unique for each command -#define CMD_PRINT 4 -#define CMD_PRINT_REG_FLAGS 2 -#define CMD_PRINT_REG_LEN 3 -#define CMD_PRINT_REG_DATA 4 - static inline uint8_t dasharo_ec_read(uint8_t addr) { return inb(DASHARO_EC_BASE + (uint16_t)addr); @@ -36,77 +35,59 @@ outb(data, DASHARO_EC_BASE + (uint16_t)addr); } -void dasharo_ec_init(void) +uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data) { - // Clear entire command region - for (int i = 0; i < DASHARO_EC_SIZE; i++) - dasharo_ec_write((uint8_t)i, 0); -} + int i; -void dasharo_ec_flush(void) -{ - dasharo_ec_write(REG_CMD, CMD_PRINT); + if (len > DASHARO_EC_SIZE - REG_DATA) + return -1; - // Wait for command completion, for up to 10 milliseconds, with a + // Wait for previous command completion, for up to 10 milliseconds, with a // test period of 1 microsecond wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); - dasharo_ec_write(CMD_PRINT_REG_LEN, 0); -} + // Write data first + for (i = 0; i < len; ++i) + dasharo_ec_write(REG_DATA + i, data[i]); -void dasharo_ec_print(uint8_t byte) -{ - uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN); - dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte); - dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1); - - // If we hit the end of the buffer, or were given a newline, flush - if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA)) - dasharo_ec_flush(); -} - -bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, - uint8_t request_size, uint8_t *reply_data, uint8_t reply_size) -{ - if (request_size > DASHARO_EC_SIZE - REG_DATA || - reply_size > DASHARO_EC_SIZE - REG_DATA) { - printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n", - cmd, request_size, reply_size); - return false; - } - - /* If any data were buffered by dasharo_ec_print(), flush it first */ - uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN); - if (buffered_len > 0) - dasharo_ec_flush(); - - /* Write the data */ - uint8_t i; - for (i = 0; i < request_size; ++i) - dasharo_ec_write(REG_DATA + i, request_data[i]); - - /* Write the command */ + // Write command register, which starts command dasharo_ec_write(REG_CMD, cmd); - /* Wait for the command to complete */ - bool ret = true; - int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); - if (elapsed == 0) { - /* Timed out: fail the command, don't attempt to read a reply. */ - printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n", - cmd, request_size, reply_size); - ret = false; - } else { - /* Read the reply */ - for (i = 0; i < reply_size; ++i) - reply_data[i] = dasharo_ec_read(REG_DATA+i); - /* Check the reply status */ - ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK); + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + return dasharo_ec_read(REG_RESULT); +} + +int dasharo_ec_get_bat_threshold(enum bat_threshold_type type) +{ + int ret = -1; + + switch (type) { + case BAT_THRESHOLD_START: + ret = ec_read(DASHARO_EC_REG_BATTERY_START_THRESHOLD); + break; + case BAT_THRESHOLD_STOP: + ret = ec_read(DASHARO_EC_REG_BATTERY_STOP_THRESHOLD); + break; + default: + break; } - /* Reset the flags and length so we can buffer console prints again */ - dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0); - dasharo_ec_write(CMD_PRINT_REG_LEN, 0); - return ret; } + +void dasharo_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value) +{ + switch (type) { + case BAT_THRESHOLD_START: + ec_write(DASHARO_EC_REG_BATTERY_START_THRESHOLD, value); + break; + case BAT_THRESHOLD_STOP: + ec_write(DASHARO_EC_REG_BATTERY_STOP_THRESHOLD, value); + break; + default: + break; + } +} diff --git a/src/ec/dasharo/ec/dasharo_ec.h b/src/ec/dasharo/ec/dasharo_ec.h deleted file mode 100644 index f313b0d..0000000 --- a/src/ec/dasharo/ec/dasharo_ec.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DASHARO_EC_H -#define DASHARO_EC_H - -#include <stdbool.h> -#include <stdint.h> - -/* - * Send a command to the EC. request_data/request_size are the request payload, - * request_data can be NULL if request_size is 0. reply_data/reply_size are - * the reply payload, reply_data can be NULL if reply_size is 0. - */ -bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, - uint8_t request_size, uint8_t *reply_data, uint8_t reply_size); - -#endif diff --git a/src/ec/dasharo/ec/smbios.c b/src/ec/dasharo/ec/smbios.c deleted file mode 100644 index e55d5f0..0000000 --- a/src/ec/dasharo/ec/smbios.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - // TODO: Read wake source from EC. - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/82672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Gerrit-Change-Number: 82672 Gerrit-PatchSet: 16 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: ec/dasharo/ec: add Dasharo features
by Felix Singer (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: Maciej Pijanowski, Michał Kopeć, Michał Żygowski. Felix Singer has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82672?usp=email ) Change subject: ec/dasharo/ec: add Dasharo features ...................................................................... Patch Set 15: Code-Review+1 (1 comment) Patchset: PS15: Please split up additions / changes more in the future, so that it's visible what does what. -- To view, visit https://review.coreboot.org/c/coreboot/+/82672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Gerrit-Change-Number: 82672 Gerrit-PatchSet: 15 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 06 Dec 2024 14:37:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85520?usp=email ) Change subject: mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/riven/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85520/comment/efb3b387_2be8a939?us… : PS1, Line 490: .pcie_rp_pcie_speed = 2, why we need to set wifi7 as Gen2 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85520?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Gerrit-Change-Number: 85520 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Dec 2024 11:53:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: Add support for PCIe speed setting
by Subrata Banik (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/85519?usp=email ) Change subject: soc/intel/alderlake: Add support for PCIe speed setting ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/85519/comment/5a631dae_0173f5fe?us… : PS1, Line 74: /* PCIE RP Pcie Speed. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 */ can you please define these as ENUM ? so, we could use the same into device tree -- To view, visit https://review.coreboot.org/c/coreboot/+/85519?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32a9918a51faa903927a9646605a618744b527c0 Gerrit-Change-Number: 85519 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Dec 2024 11:53:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 driver
by Yidi Lin (Code Review) 06 Dec '24

06 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85127?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver ...................................................................... Patch Set 19: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Gerrit-Change-Number: 85127 Gerrit-PatchSet: 19 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 06 Dec 2024 11:49:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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