coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for DID2
by Subrata Banik (Code Review) 07 Dec '24

07 Dec '24

Attention is currently required from: Bora Guvendik, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/85525?usp=email ) Change subject: device/pci_ids: Add new Intel PTL device IDs for DID2 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Gerrit-Change-Number: 85525 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 07 Dec 2024 02:45:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/pci_ids: Add new Intel PTL device IDs for DID2
by Bora Guvendik (Code Review) 07 Dec '24

07 Dec '24

Bora Guvendik has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/85525?usp=email ) Change subject: device/pci_ids: Add new Intel PTL device IDs for DID2 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/85525?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4209236ca48f449c22a830c2e44ea8b5909774b Gerrit-Change-Number: 85525 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Comment-Date: Sat, 07 Dec 2024 00:50:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mainboard/ocp/tiogapass: Enable TPM
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85510?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mainboard/ocp/tiogapass: Enable TPM ...................................................................... mainboard/ocp/tiogapass: Enable TPM Add support for the optional TPM. When GPP_A22 is low a TPM is installed. TEST: Found a working TPM 2.0 SLB9670 on ocp/tiogapass. Change-Id: I970033981a265eb0094bc91fc070487b34972a5a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85510 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/ocp/tiogapass/ramstage.c 3 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 8bf7e79..a1ff82f 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -14,6 +14,8 @@ select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 select UART_OVERRIDE_BAUDRATE + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_USES_IFD_10GBE_0_REGION select VPD diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 37e740a..427694a 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -82,6 +82,9 @@ chip drivers/ipmi/ocp # OCP specific IPMI porting device pnp ca2.1 on end end + chip drivers/pc80/tpm # TPM + device pnp 0c31.0 alias tpm on end + end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.1 hidden end # p2sb device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c index a07edb8..fbc5e92 100644 --- a/src/mainboard/ocp/tiogapass/ramstage.c +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -3,8 +3,10 @@ #include <cpu/x86/smm.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <gpio.h> #include <soc/ramstage.h> #include <soc/smmrelocate.h> +#include <static.h> extern struct fru_info_str fru_strings; @@ -165,8 +167,18 @@ t->count = smbios_add_oem_string(t->eos, TBF); } +WEAK_DEV_PTR(tpm); + static void mainboard_enable(struct device *dev) { + struct device *tpm = DEV_PTR(tpm); + + gpio_input(GPP_A22); + if (tpm) + tpm->enabled = !gpio_get(GPP_A22); + + printk(BIOS_DEBUG, "TPM present: %d\n", !gpio_get(GPP_A22)); + dev->ops->get_smbios_strings = tp_oem_smbios_strings; read_fru_areas(CONFIG_BMC_KCS_BASE, CONFIG_FRU_DEVICE_ID, 0, &fru_strings); #if CONFIG(GENERATE_SMBIOS_TABLES) -- To view, visit https://review.coreboot.org/c/coreboot/+/85510?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I970033981a265eb0094bc91fc070487b34972a5a Gerrit-Change-Number: 85510 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Add missing FADT fields
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85508?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp/cpx: Add missing FADT fields ...................................................................... soc/intel/xeon_sp/cpx: Add missing FADT fields CPX uses the same PCH as SKX does, thus it has the same ACPI timer timer and PM2 control fields as SKX. Copy the code from skx to cpx to reduce code differences. Allows to merge both codebases into one. Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85508 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c 1 file changed, 16 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index c7edb22..defc69d 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -36,8 +36,22 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { - /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ - fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ + fadt->flags &= ~(ACPI_FADT_SEALED_CASE); + fadt->flags |= ACPI_FADT_SLEEP_TYPE; + + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + + /* PM Extended Registers */ + fill_fadt_extended_pm_io(fadt); } void soc_power_states_generation(int core_id, int cores_per_package) -- To view, visit https://review.coreboot.org/c/coreboot/+/85508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92fc63a6655fb915b2c06273c3259dddfb93e8bb Gerrit-Change-Number: 85508 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85507?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042 ...................................................................... soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042 None of the supported mainboards have a 8042 compatible chip, thus drop it from the common code. When such board is added it can update fadt->iapc_boot_arch by installing a mainboard_fill_fadt() method. Change-Id: I40cafcec57dd49399ce449700c81a1f27c1ded99 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85507 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/skx/soc_acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index c9d867c..2a9bd17 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -47,7 +47,7 @@ fadt->pm2_cnt_len = 1; fadt->pm_tmr_len = 4; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; /* PM Extended Registers */ fill_fadt_extended_pm_io(fadt); -- To view, visit https://review.coreboot.org/c/coreboot/+/85507?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40cafcec57dd49399ce449700c81a1f27c1ded99 Gerrit-Change-Number: 85507 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Use generate_p_state_entries
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85506?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Use generate_p_state_entries ...................................................................... soc/intel/xeon_sp: Use generate_p_state_entries Both CPX and SKX always enable EIST, thus the generic generate_p_state_entries() method can be used to generate _PSS. This also reduces code differences between skx and cpx and allows to merge both codebases into one. Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85506 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 2 files changed, 4 insertions(+), 104 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 58e67fc..c7edb22 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -40,108 +40,7 @@ fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); } -/* TODO: See if we can use the common generate_p_state_entries */ -void soc_power_states_generation(int core, int cores_per_package) +void soc_power_states_generation(int core_id, int cores_per_package) { - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - if (num_entries > PSS_MAX_ENTRIES) { - ratio_step += 1; - num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /* MHz */ - power_max, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio_turbo << 8, /* control */ - ratio_turbo << 8); /* status */ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /* MHz */ - power_max, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio_max << 8, /* control */ - ratio_max << 8); /* status */ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - /* Calculate power at this ratio */ - power = common_calculate_power_ratio(power_max, ratio_max, ratio); - clock = ratio * CONFIG_CPU_BCLK_MHZ; - //clock = 1; - acpigen_write_PSS_package( - clock, /* MHz */ - power, /* mW */ - PSS_LATENCY_TRANSITION, /* lat1 */ - PSS_LATENCY_BUSMASTER, /* lat2 */ - ratio << 8, /* control */ - ratio << 8); /* status */ - } - - /* Fix package length */ - acpigen_pop_len(); + generate_p_state_entries(core_id, cores_per_package); } diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index 541dd67..c9d867c 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -53,6 +53,7 @@ fill_fadt_extended_pm_io(fadt); } -void soc_power_states_generation(int core, int cores_per_package) +void soc_power_states_generation(int core_id, int cores_per_package) { + generate_p_state_entries(core_id, cores_per_package); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7b03eef9498f2c442745119b24fb8b5c6169a08 Gerrit-Change-Number: 85506 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85318?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists ...................................................................... mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists The board has 24 slots for DDR4 ECC RDIMMs and it has 2 CPU sockets, where each is connected to 12 DIMMs. Every socket supports up to 6 channels, thus every channel is connected to 2 DIMMs. Implement mainboard_dimm_slot_exists accordingly to advertise all slots as SMBIOS type 17. TEST: Found all installed DIMMs advertised through SMBIOS on ocp/tiogapass. Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85318 Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/romstage.c 1 file changed, 17 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Christian Walter: Looks good to me, approved diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index d3063c6..283d5f1 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -1,13 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <fsp/api.h> -#include <FspmUpd.h> #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include <gpio.h> +#include <soc/ddr.h> +#include <soc/gpio_soc_defs.h> #include <soc/romstage.h> #include <string.h> -#include <gpio.h> -#include <soc/gpio_soc_defs.h> #include <skxsp_tp_iio.h> #include "ipmi.h" @@ -64,3 +65,15 @@ mupd->FspmConfig.GpioConfig.GpioTable = NULL; mupd->FspmConfig.GpioConfig.NumberOfEntries = 0; } + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + if (socket >= CONFIG_MAX_SOCKET) + return false; + if (channel >= 6) + return false; + if (dimm >= 2) + return false; + + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31cb4a89aa11258ac04eb69a0e9c86f258280484 Gerrit-Change-Number: 85318 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/cpx: Fix register lock
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85439?usp=email ) Change subject: soc/intel/xeon_sp/cpx: Fix register lock ...................................................................... soc/intel/xeon_sp/cpx: Fix register lock Do not use a define for a PCI register to lock a MSR. The defines will be moved in the following commit to it's own header, preventing the use in CPX CPU init. Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85439 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 1 insertion(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index d90b8b5..ae3f0fb 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -115,10 +115,8 @@ set_vmx_and_lock(); set_aesni_lock(); - /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions - Lock Turbo. Did FSP-S set this up??? */ msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + msr.lo |= BIT31; /* Lock it */ wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85439?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76a8ae13dbd942291aacbb4bd84140be156bc563 Gerrit-Change-Number: 85439 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp/skx: Fix CPU init
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85289?usp=email ) Change subject: soc/intel/xeon_sp/skx: Fix CPU init ...................................................................... soc/intel/xeon_sp/skx: Fix CPU init Move CPU init closer to other SoC and CPX. FSP-S only is aware of socket 0, thus all cores must rerun all settings already done by FSP, in order to set up socket 1 as well. FSP sets the following on socket0: - Set BIT20 in MSR_VR_MISC_CONFIG - Set LTR_IIO_DISABLE in MSR_POWER_CTL Lock the following MSRs: - MSR_SNC_CONFIG - MSR_CONFIG_TDP_CONTROL - MSR_FEATURE_CONFIG - MSR_TURBO_ACTIVATION_RATIO Also do the following as done on other SoCs: - Configure VMX and lock it - Enable LAPIC TPRs (fixes MWAIT support) - Honor CONFIG_SET_MSR_AESNI_LOCK_BIT - Set TCC thermal target as set in devicetree Fixes 8 second wakeup time from LAPIC interrupts when in MWAIT. TEST: Booted on ocp/tiogapass to Linux 6.9 with all cores in ACPI C6, no boot delay or hung tasks could be found. Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85289 Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/xeon_sp/include/soc/msr.h M src/soc/intel/xeon_sp/skx/cpu.c 3 files changed, 36 insertions(+), 9 deletions(-) Approvals: Christian Walter: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 1770167..c077fb8 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -320,7 +320,7 @@ */ if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) || CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) || - CONFIG(SOC_INTEL_BROADWELL)) + CONFIG(SOC_INTEL_BROADWELL) || CONFIG(SOC_INTEL_SKYLAKE_SP)) return; /* Time Window Tau Bits [6:0] */ diff --git a/src/soc/intel/xeon_sp/include/soc/msr.h b/src/soc/intel/xeon_sp/include/soc/msr.h index 19c37f6..09f1acc 100644 --- a/src/soc/intel/xeon_sp/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/include/soc/msr.h @@ -8,6 +8,8 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_LOCK BIT(0) +#define MSR_SNC_CONFIG 0x152 + #define IA32_MCG_CAP 0x179 #define IA32_MCG_CAP_COUNT_MASK 0xff #define IA32_MCG_CAP_CTL_P_BIT 8 @@ -71,7 +73,6 @@ #define MSR_TURBO_ACTIVATION_RATIO 0x64c #define MAX_NON_TURBO_RATIO_SHIFT 0 #define MAX_NON_TURBO_RATIO (0xff << MAX_NON_TURBO_RATIO_SHIFT) - #define IA32_PM_ENABLE 0x770 #define IA32_HWP_CAPABILITIES 0x771 diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index fc49ddc..36dc63b 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -7,6 +7,7 @@ #include <cpu/intel/cpu_ids.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/mp.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> #include <cpu/intel/smm_reloc.h> @@ -84,15 +85,18 @@ cpu->path.apic.package_id); assert(chip_config); - /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/ + /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core */ msr.hi = 0; msr.lo = (PKG_CSTATE_NO_LIMIT | CFG_LOCK_ENABLE); wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Enable Energy Perf Bias Access, Dynamic switching and lock MSR */ msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (ENERGY_PERF_BIAS_ACCESS_ENABLE | PWR_PERF_TUNING_DYN_SWITCHING_ENABLE - | PROCHOT_LOCK_ENABLE); + msr.lo &= ~(POWER_CTL_C1E_MASK | BIT2); + msr.lo |= ENERGY_PERF_BIAS_ACCESS_ENABLE; + msr.lo |= PWR_PERF_TUNING_DYN_SWITCHING_ENABLE; + msr.lo |= LTR_IIO_DISABLE; + msr.lo |= PROCHOT_LOCK_ENABLE; wrmsr(MSR_POWER_CTL, msr); /* Set P-State ratio */ @@ -115,7 +119,9 @@ wrmsr(MSR_MISC_PWR_MGMT, msr); } - /* TODO MSR_VR_MISC_CONFIG */ + msr = rdmsr(MSR_VR_MISC_CONFIG); + msr.hi |= BIT20; + wrmsr(MSR_VR_MISC_CONFIG, msr); /* Set current limit lock */ msr = rdmsr(MSR_VR_CURRENT_CONFIG); @@ -132,14 +138,19 @@ msr.hi = (chip_config->turbo_ratio_limit_cores >> 32) & 0xffffffff; wrmsr(MSR_TURBO_RATIO_LIMIT_CORES, msr); - /* set Turbo Activation ratio */ - msr.hi = 0; + /* set Turbo Activation ratio - scope package */ msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); msr.lo |= MAX_NON_TURBO_RATIO; + msr.lo |= BIT31; /* Lock it */ wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); - /* Enable Fast Strings */ + /* Scope package */ + msr = rdmsr(MSR_CONFIG_TDP_CONTROL); + msr.lo |= BIT31; /* Lock it */ + wrmsr(MSR_CONFIG_TDP_CONTROL, msr); + msr = rdmsr(IA32_MISC_ENABLE); + /* Enable Fast Strings */ msr.lo |= FAST_STRINGS_ENABLE_BIT; wrmsr(IA32_MISC_ENABLE, msr); @@ -149,9 +160,18 @@ msr.hi = 0; wrmsr(MSR_IA32_ENERGY_PERF_BIAS, msr); + if (!intel_ht_sibling()) { + /* scope per core */ + msr = rdmsr(MSR_SNC_CONFIG); + msr.lo |= BIT28; /* Lock it */ + wrmsr(MSR_SNC_CONFIG, msr); + } + /* Enable Turbo */ enable_turbo(); + configure_tcc_thermal_target(); + /* Enable speed step. */ if (get_turbo_state() == TURBO_ENABLED) { msr = rdmsr(IA32_MISC_ENABLE); @@ -161,6 +181,12 @@ /* Clear out pending MCEs */ xeon_configure_mca(); + + /* Enable Vmx */ + set_vmx_and_lock(); + set_aesni_lock(); + + enable_lapic_tpr(); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85289?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If08ef5150b104b0c2329fcb64a0476ce641c831c Gerrit-Change-Number: 85289 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: arch/x86: Enable support for IOAPIC devices
by Lean Sheng Tan (Code Review) 06 Dec '24

06 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85226?usp=email ) Change subject: arch/x86: Enable support for IOAPIC devices ...................................................................... arch/x86: Enable support for IOAPIC devices On platforms with multiple IOAPICs the GSI base must not be linear, which is currently assumed by acpi_create_madt_ioapic_from_hw(). Integrate the existing struct device DEVICE_PATH_IOAPIC type and allow to assign custom GSI bases for each IOAPIC. Write out the IOAPIC devices into the MADT table if any. For now, since no platform adds IOAPIC devices, the existing behaviour remains the same. Allows to get rid of soc_get_ioapic_info(). Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85226 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/acpi/acpi_apic.c M src/arch/x86/include/arch/ioapic.h M src/arch/x86/ioapic.c M src/device/device_const.c M src/include/device/path.h 5 files changed, 66 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index fe0459b..1862195 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <acpi/acpi.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> @@ -226,6 +227,8 @@ unsigned long acpi_arch_fill_madt(acpi_madt_t *madt, unsigned long current) { + struct device *dev = NULL; + madt->lapic_addr = cpu_get_lapic_addr(); if (CONFIG(ACPI_HAVE_PCAT_8259)) @@ -237,5 +240,21 @@ if (CONFIG(ACPI_COMMON_MADT_IOAPIC)) current = acpi_create_madt_ioapic_gsi0_default(current); + while ((dev = dev_find_path(dev, DEVICE_PATH_IOAPIC)) != NULL) { + /* + CONFIG(ACPI_COMMON_MADT_IOAPIC) adds the IOAPIC with gsi_base = 0 above. + Make sure to not add it twice when it's also part of the devicetree. + Currently no SoC adds ioapic_gsi0 to the devicetree. + TODO: Add the ioapic_gsi0 to the device-tree on all SoCs and remove this check. + */ + assert(!CONFIG(ACPI_COMMON_MADT_IOAPIC) || dev->path.ioapic.gsi_base != 0); + assert(dev->path.ioapic.addr); + + current += acpi_create_madt_ioapic((void *)(uintptr_t)current, + dev->path.ioapic.ioapic_id, + dev->path.ioapic.addr, + dev->path.ioapic.gsi_base); + } + return current; } diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 530128a..6c19ed0 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -16,6 +16,9 @@ void ioapic_set_max_vectors(uintptr_t ioapic_base, int mre_count); void ioapic_lock_max_vectors(uintptr_t ioapic_base); +struct device *ioapic_create_dev(struct device *parent, + const uintptr_t ioapic_base, + const u32 gsi_base); void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id); void register_new_ioapic(uintptr_t ioapic_base); void register_new_ioapic_gsi0(uintptr_t ioapic_base); diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c index 5bb2adb5..4cde7c7 100644 --- a/src/arch/x86/ioapic.c +++ b/src/arch/x86/ioapic.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <device/device.h> #include <device/mmio.h> #include <arch/ioapic.h> #include <console/console.h> @@ -174,6 +175,44 @@ } } +/** + * Create a new IOAPIC device under the given device. + * + * @param parent The parent device. A PCI domain or PCI device (in case of PCI IOAPIC). + * @param ioapic_base The IOAPIC base address + * @param gsi_base Platform specific GSI base + * @return Pointer to the device struct. + */ +struct device *ioapic_create_dev(struct device *parent, + const uintptr_t ioapic_base, + const u32 gsi_base) +{ + struct device_path path = {0}; + struct device *dev; + + if (!parent) + return NULL; + + struct bus *bus = alloc_bus(parent); + if (!bus) + return NULL; + + if (gsi_base == 0) + register_new_ioapic_gsi0(ioapic_base); + else + register_new_ioapic(ioapic_base); + + path.type = DEVICE_PATH_IOAPIC; + path.ioapic.ioapic_id = get_ioapic_id(ioapic_base); + path.ioapic.addr = ioapic_base; + path.ioapic.gsi_base = gsi_base; + + dev = alloc_dev(bus, &path); + assert(dev); + + return dev; +} + void setup_ioapic(uintptr_t ioapic_base, u8 ioapic_id) { set_ioapic_id(ioapic_base, ioapic_id); diff --git a/src/device/device_const.c b/src/device/device_const.c index 9f3443e..2aef907 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -130,6 +130,9 @@ case DEVICE_PATH_CPU_BUS: equal = (path1->cpu_bus.id == path2->cpu_bus.id); break; + case DEVICE_PATH_IOAPIC: + equal = (path1->ioapic.ioapic_id == path2->ioapic.ioapic_id); + break; case DEVICE_PATH_GENERIC: equal = (path1->generic.id == path2->generic.id) && (path1->generic.subid == path2->generic.subid); diff --git a/src/include/device/path.h b/src/include/device/path.h index d8ef880..8e9ec3b 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -85,7 +85,9 @@ }; struct ioapic_path { + uintptr_t addr; unsigned int ioapic_id; + unsigned int gsi_base; }; struct cpu_cluster_path { -- To view, visit https://review.coreboot.org/c/coreboot/+/85226?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie13d4f5c4f0704f0935974f90e5b7cf24e94aab3 Gerrit-Change-Number: 85226 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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coreboot-gerrit December 2024