coreboot-gerrit December 2024

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[M] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry
by Jérémy Compostella (Code Review) 10 Dec '24

10 Dec '24

Jérémy Compostella has restored this change. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Program the right power_limits_config entry ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: restore Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add soc_get_sku_power_limits() support
by Jérémy Compostella (Code Review) 10 Dec '24

10 Dec '24

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85443?usp=email ) Change subject: soc/intel/pantherlake: Add soc_get_sku_power_limits() support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/85443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib89979e7933da62c8ddfec09ecf27f86b7ac0e09 Gerrit-Change-Number: 85443 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry
by Jérémy Compostella (Code Review) 10 Dec '24

10 Dec '24

Jérémy Compostella has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Program the right power_limits_config entry ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry
by Jérémy Compostella (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Hello Subrata Banik, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85545?usp=email to review the following change. Change subject: intel/common/block: Program the right power_limits_config entry ...................................................................... intel/common/block: Program the right power_limits_config entry When variant_update_cpu_power_limits() programs PL4, it systematically sets the first entry of the power_limits_config SoC chip data structure. This approach is problematic because the current SoC SKU may align with a different data structure entry, introducing inconsistencies. This commit introduces the power_limits_index field to the cpu_tdp_power_limits data structure. This field specifies the specific power limits entry that should be updated. All data structures utilized by this function are updated accordingly. BUG=b:380408956 TEST=Able to retrieve collect 28W power_limit. Change-Id: I54b74241cca29eee722178f9fb1be5e8a7a8be15 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c M src/mainboard/google/rex/variants/deku/ramstage.c M src/mainboard/google/rex/variants/screebo/variant.c M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 7 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/85545/1 diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c index e23fc9a..b1b3b9c 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c @@ -41,6 +41,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_1, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, @@ -50,6 +51,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_3, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index 14fbad2..2b920ad 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -15,6 +15,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, @@ -24,6 +25,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_5, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, @@ -36,6 +38,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, @@ -45,6 +48,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_5, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c index 0cfcae1..871313c 100644 --- a/src/mainboard/google/rex/variants/deku/ramstage.c +++ b/src/mainboard/google/rex/variants/deku/ramstage.c @@ -14,6 +14,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_1, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, @@ -23,6 +24,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_3, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c index edddd43..00ee19f5 100644 --- a/src/mainboard/google/rex/variants/screebo/variant.c +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -35,6 +35,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 40000, @@ -44,6 +45,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_5, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 40000, diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c index aee3d88..d8a171e 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c @@ -13,6 +13,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 290a3a3..d02eaa1 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -45,6 +45,7 @@ struct cpu_tdp_power_limits { uint16_t mch_id; uint8_t cpu_tdp; + uint32_t power_limits_index; unsigned int pl1_min_power; unsigned int pl1_max_power; unsigned int pl2_min_power; diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index 40a0857..b5fbe89 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -268,7 +268,8 @@ } else { struct dptf_power_limits *settings = &config->controls.power_limits; config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; + struct soc_power_limits_config *soc_config = + &conf->power_limits_config[limits[index].power_limits_index]; settings->pl1.min_power = limits[index].pl1_min_power; settings->pl1.max_power = limits[index].pl1_max_power; settings->pl2.min_power = limits[index].pl2_min_power; -- To view, visit https://review.coreboot.org/c/coreboot/+/85545?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I54b74241cca29eee722178f9fb1be5e8a7a8be15 Gerrit-Change-Number: 85545 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Jérémy Compostella (Code Review) 10 Dec '24

10 Dec '24

Hello Jamie Ryu, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85146?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... mb/google/fatcat: Limit Power Limit when battery is missing Ensure the board can boot by limiting the power limits if the battery is missing. This addresses the factory use case. BUG=b:377798581 TEST=See power limit override log message when the battery is missing on fatcat board Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/Makefile.mk A src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/85146/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 13 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/google/brya/var/uldrenite: update gpio settings
by John Su (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85522?usp=email ) Change subject: mb/google/brya/var/uldrenite: update gpio settings ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c5cb298fd0a4108af8f65abd9eeddbfe5b7afc4 Gerrit-Change-Number: 85522 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 05:01:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: drivers/amd/nova: Add Nova Card directory
by Anand Vaikar (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Ana Carolina Cabral. Anand Vaikar has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84776?usp=email ) Change subject: drivers/amd/nova: Add Nova Card directory ...................................................................... Patch Set 5: (1 comment) File src/drivers/amd/nova/Kconfig: https://review.coreboot.org/c/coreboot/+/84776/comment/b1332fd9_c908dacd?us… : PS5, Line 4: def_bool n will this be enabled via defconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/84776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Gerrit-Change-Number: 84776 Gerrit-PatchSet: 5 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Tue, 10 Dec 2024 04:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Kapil Porwal (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Nick Vaccaro, Rui Zhou. Kapil Porwal has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85535?usp=email ) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 04:43:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add memory config
by Dtrain Hsu (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Dtrain Hsu has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85542?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add memory config ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Gerrit-Change-Number: 85542 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 03:29:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/uldrenite/variant.c: https://review.coreboot.org/c/coreboot/+/85537/comment/76548793_0b42ea67?us… : PS1, Line 24: variant_init > Because we currently do not have the board and keypart for verification, so if can merge this CL first? When the proto board is obtained, I will change it and add it to driver to reduce boot time. Please add a TODO section and keep one bug open to resolve this in proper. -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 03:20:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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coreboot-gerrit December 2024