coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/uldrenite/variant.c: https://review.coreboot.org/c/coreboot/+/85537/comment/6da27f2d_f9ac64b1?us… : PS1, Line 24: variant_init > looks like we will increase the boot time by 50ms. this is 5% of total boot time. […] Because we currently do not have the board and keypart for verification, so if can merge this CL first? When the proto board is obtained, I will change it and add it to driver to reduce boot time. -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 03:10:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Julius Werner, Kapil Porwal, Paul Menzel. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 11: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/85326/comment/6fad74b3_f531a5c8?us… : PS9, Line 286: printk > So would you want to use the same timestamp index for each command? Because I think that would look very confusing, trying to figure out which timestamp came from what command. Isn't a log that can display the command code right next to the time much better for this? I was thinking we could keep a data structure that maps EC host commands to timestamps. That way, we'd always know which timestamp belongs to which EC host command. > > I'm also not sure it's a good idea in general to add Kconfig-conditional timestamps that only turn up in certain debug builds. We already have a similar feature for FSP. When we build FSP with a specific flag, it adds more timestamps that aren't needed during regular boot. Here's how it works: 1. When debug Kconfig is disabled, the timestamps look like this: ``` timestamp for foo() ---- 100ms timestamp for foo_1() ---- 300ms ``` So, the total time spent between foo() and foo_1() is 200ms. 2. When debug Kconfig is enabled, the timestamps look like this: ``` timestamp for foo() ---- 100ms timestamp for func_1() ---- 110ms timestamp for func_2() ---- 150ms timestamp for func_3() ---- 210ms timestamp for foo_1() ---- 300ms ``` This gives us a more detailed breakdown of the time spent between foo() and foo_1(), which wasn't possible with the first method. > Since the timestamp system always measures the time between two timestamps, this would shift other times around in unexpected ways when you turn on the option. I think the timestamp system is best for a consistent, high-level overview of which general parts of the boot flow take how much time, and then when drilling down into detail adding extra log messages that can be conditionally enabled is the better tool. -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 11 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 03:06:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: config GPP_F23 as ISH gpio pin
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Jérémy Compostella, Li1 Feng, Pranava Y N. Subrata Banik has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/85464?usp=email ) Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Can we handle this using FW_CONFIG ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d Gerrit-Change-Number: 85464 Gerrit-PatchSet: 4 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:59:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: acpi/acpigen: generate Create*Field() from name string directly
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85197?usp=email ) Change subject: acpi/acpigen: generate Create*Field() from name string directly ...................................................................... acpi/acpigen: generate Create*Field() from name string directly The following functions are added: _create_buffer_field acpigen_write_create_buffer_byte_field acpigen_write_create_buffer_word_field acpigen_write_create_buffer_dword_field acpigen_write_create_buffer_qword_field These functions are to generate: CreateByteField (<namestring> , offset, <field name>) CreateWordField (<namestring> , offset, <field name>) CreateDWordField (<namestring> , offset, <field name>) CreateQWordField (<namestring> , offset, <field name>) NOTE: There are set of acpigen_write_create_[byte/word/dword/qword]_field functions already, but the field can only be created from Arg[n] or Local[n] variable objects. A Name object must be first assigned to such variable. The new functions here will allow us to create field directly from Name object. BUG=none Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85197 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpigen.c M src/include/acpi/acpigen.h 2 files changed, 33 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 4049df0..f682522 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -2424,6 +2424,35 @@ _create_field(CREATE_QWORD_OP, op, byte_offset, name); } +static void _create_buffer_field(uint8_t aml_op, const char *src_buf, size_t byte_offset, + const char *field) +{ + acpigen_emit_byte(aml_op); + acpigen_emit_namestring(src_buf); + acpigen_write_integer(byte_offset); + acpigen_emit_namestring(field); +} + +void acpigen_write_create_buffer_byte_field(const char *src_buf, size_t byte_offset, const char *field) +{ + _create_buffer_field(CREATE_BYTE_OP, src_buf, byte_offset, field); +} + +void acpigen_write_create_buffer_word_field(const char *src_buf, size_t byte_offset, const char *field) +{ + _create_buffer_field(CREATE_WORD_OP, src_buf, byte_offset, field); +} + +void acpigen_write_create_buffer_dword_field(const char *src_buf, size_t byte_offset, const char *field) +{ + _create_buffer_field(CREATE_DWORD_OP, src_buf, byte_offset, field); +} + +void acpigen_write_create_buffer_qword_field(const char *src_buf, size_t byte_offset, const char *field) +{ + _create_buffer_field(CREATE_QWORD_OP, src_buf, byte_offset, field); +} + void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts) { acpigen_write_name("_PCT"); diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index d2e669f..8129263 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -536,6 +536,10 @@ void acpigen_write_create_word_field(uint8_t op, size_t byte_offset, const char *name); void acpigen_write_create_dword_field(uint8_t op, size_t byte_offset, const char *name); void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char *name); +void acpigen_write_create_buffer_byte_field(const char *src_buf, size_t byte_offset, const char *name); +void acpigen_write_create_buffer_word_field(const char *src_buf, size_t byte_offset, const char *name); +void acpigen_write_create_buffer_dword_field(const char *src_buf, size_t byte_offset, const char *name); +void acpigen_write_create_buffer_qword_field(const char *src_buf, size_t byte_offset, const char *name); void acpigen_write_field_name(const char *name, uint32_t size); /* * Generate ACPI AML code for _DSM method. -- To view, visit https://review.coreboot.org/c/coreboot/+/85197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I725f17329c501c80d42034e0f6a2fccb2cef5915 Gerrit-Change-Number: 85197 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/fatcat: Enable Intel DPTF support and configure policies
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85457?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies ...................................................................... mb/google/fatcat: Enable Intel DPTF support and configure policies This commit enables the Dynamic Platform and Thermal Framework (DPTF) for the fatcat board. DPTF is a system management framework that allows the board to dynamically adjust its power and thermal settings based on the system load and thermal conditions. This can help to improve the board's performance and battery life. The following changes were made to enable DPTF: - Added the Intel DPTF driver to the board's Kconfig file. - Overrode the default DPTF settings in the fatcat variant overridetree.cb file. - Enabled the DPTF policy on the baseboard. Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85457 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 3 files changed, 128 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Sukumar Ghorai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index b9c3768..e4c98dd 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -5,6 +5,7 @@ select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index c4e2276..f3a0a65 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -34,7 +34,7 @@ register "s0ix_enable" = "false" # DPTF enable - register "dptf_enable" = "false" + register "dptf_enable" = "true" # TODO: Safe Setting. Needs to be removed later # Disable C1 C-state auto-demotion diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index 26490f1..44ea511 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -142,6 +142,132 @@ probe DISPLAY DISPLAY_PRESENT end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""wwan"" + + ## Active Policy + # FIXME: below values are initial reference values only + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(70, 97), + TEMP_PCT(65, 90), + TEMP_PCT(60, 80), + TEMP_PCT(55, 75), + TEMP_PCT(50, 65), + TEMP_PCT(45, 45), + TEMP_PCT(43, 30), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + TEMP_PCT(45, 30), + } + } + }" + + ## Passive Policy + # TODO: below values are initial reference values only + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 80, 5000), + }" + + ## Critical Policy + # TODO: below values are initial reference values only + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 95000, + .max_power = 95000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/85457?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5042795acee3e261765ca4c392d15ef7f5ca97 Gerrit-Change-Number: 85457 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Tarun. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Program the right power_limits_config entry ...................................................................... Patch Set 11: (1 comment) Patchset: PS11: > @subratabanik@google.com and @kapilporwal@google.com, is there anyone on your side who could verify it works fine on Google MTL boards ? I tested on PTL. looks like we already started a discussion here https://b.corp.google.com/issues/380408956#comment4 Am I missing anything ? or this comment was before looking at latest update from https://b.corp.google.com/issues/380408956 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 11 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:56:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Julius Werner (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Kapil Porwal, Paul Menzel, Subrata Banik. Julius Werner has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 11: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/85326/comment/9e2a9059_95b2b655?us… : PS9, Line 286: printk > > > Please call stopwatch_tick() before accessing sw.current. […] So would you want to use the same timestamp index for each command? Because I think that would look very confusing, trying to figure out which timestamp came from what command. Isn't a log that can display the command code right next to the time much better for this? I'm also not sure it's a good idea in general to add Kconfig-conditional timestamps that only turn up in certain debug builds. Since the timestamp system always measures the time between two timestamps, this would shift other times around in unexpected ways when you turn on the option. I think the timestamp system is best for a consistent, high-level overview of which general parts of the boot flow take how much time, and then when drilling down into detail adding extra log messages that can be conditionally enabled is the better tool. -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 11 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:48:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: config GPP_F23 as ISH gpio pin
by Li1 Feng (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Jérémy Compostella, Pranava Y N, Subrata Banik. Hello Jérémy Compostella, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85464?usp=email to look at the new patch set (#4). Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin ...................................................................... mb/google/fatcat: config GPP_F23 as ISH gpio pin The GPP_F23/ISH_GP_9A pin receives the lid open/close signal from SMC_LID. This pin is not utilized in the AP firmware stack; however, the ISH firmware requires this signal for its tablet mode support. Therefore, we configure this pin as an ISH GPIO. BUG=b:370984186 TEST=Build and flash CB; run ISH main firmware; read this pin and verified it returned the correct value. fatcat-rev257 ~ # ectool --name=cros_ish gpioget lid_open GPIO lid_open = 1 Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d Signed-off-by: Li Feng <li1.feng(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85464/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d Gerrit-Change-Number: 85464 Gerrit-PatchSet: 4 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: config GPP_F23 as ISH gpio pin
by Li1 Feng (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Jérémy Compostella, Pranava Y N, Subrata Banik. Hello Jérémy Compostella, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85464?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin ...................................................................... mb/google/fatcat: config GPP_F23 as ISH gpio pin The GPP_F23/ISH_GP_9A pin receives the lid open/close signal form SMC_LID. This pin is not utilized in the AP firmware stack; however, the ISH firmware requires this signal for its tablet mode support. Therefore, we configure this pin as an ISH GPIO. BUG=b:370984186 TEST=Build and flash CB; run ISH main firmware; read this pin and verified it returned the correct value. fatcat-rev257 ~ # ectool --name=cros_ish gpioget lid_open GPIO lid_open = 1 Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d Signed-off-by: Li Feng <li1.feng(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85464/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d Gerrit-Change-Number: 85464 Gerrit-PatchSet: 3 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Eric Lai (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Eric Lai has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85535?usp=email ) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:20:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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