coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add memory config
by Eric Lai (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85542?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add memory config ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Gerrit-Change-Number: 85542 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:20:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: config GPP_F23 as ISH gpio pin
by Li1 Feng (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Jérémy Compostella. Li1 Feng has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/85464?usp=email ) Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin ...................................................................... Patch Set 2: (3 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/85464/comment/b0fef769_7536f6b0?us… : PS1, Line 6: > > `Subject line should not end with a period.` […] Done https://review.coreboot.org/c/coreboot/+/85464/comment/68fa023a_527dcdfa?us… : PS1, Line 8: > Could you add a bit more ? Like that this PIN was not used in the software stack design. […] Done https://review.coreboot.org/c/coreboot/+/85464/comment/d1400933_27df998f?us… : PS1, Line 10: TEST=Pass build and run > This is a bit light for a test. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85464?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d Gerrit-Change-Number: 85464 Gerrit-PatchSet: 2 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:17:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable Bayhub Level 2 errata
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85524?usp=email ) Change subject: mb/google/fatcat: Enable Bayhub Level 2 errata ...................................................................... mb/google/fatcat: Enable Bayhub Level 2 errata Enable the DRIVERS_GENERIC_BAYHUB_LV2 Kconfig option to apply errata for the Bayhub PCIe-based SD controller (device ID 0x8621). BUG=b:376019977 TEST=Built and booted google/fatcat with a functional x1 slot. Change-Id: Iebc5bb73d895e8b20c47a924c6665c6ad289d1c4 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85524 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 3ab4be0..b9c3768 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -54,6 +54,7 @@ config BOARD_GOOGLE_MODEL_FATCAT def_bool n select BOARD_GOOGLE_BASEBOARD_FATCAT + select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_FATCAT -- To view, visit https://review.coreboot.org/c/coreboot/+/85524?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iebc5bb73d895e8b20c47a924c6665c6ad289d1c4 Gerrit-Change-Number: 85524 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Remove redundant GPIOs for x1 slot
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85523?usp=email ) Change subject: mb/google/fatcat: Remove redundant GPIOs for x1 slot ...................................................................... mb/google/fatcat: Remove redundant GPIOs for x1 slot The following GPIOs are already implemented in fw_config.c based on CBI values: - GPP_A08: X1_PCIE_SLOT_PWR_EN - GPP_B25: X1_SLOT_WAKE_N - GPP_D19: X1_DT_PCIE_RST_N This change removes the redundant GPIO definitions from gpio.c. BUG=b:376019977 TEST=Able to build and boot google/fatcat with functional x1 slot. Change-Id: I56c6fd3ea8b9e58933548543d195621da94c882e Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85523 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 0 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 45cede6..5705179 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -28,8 +28,6 @@ /* GPP_A06: ESPI_RST_EC_R_N */ /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ - /* GPP_A08: X1_PCIE_SLOT_PWR_EN */ - PAD_CFG_GPO(GPP_A08, 1, PLTRST), /* GPP_A09: M.2_WWAN_FCP_OFF_N */ PAD_CFG_GPO(GPP_A09, 1, PLTRST), /* GPP_A10: M.2_WWAN_DISABLE_N */ @@ -101,8 +99,6 @@ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), /* GPP_B24: ESPI_ALERT0_EC_R_N */ PAD_NC(GPP_B24, NONE), - /* GPP_B25: X1_SLOT_WAKE_N */ - PAD_CFG_GPI_SCI_LOW(GPP_B25, NONE, DEEP, LEVEL), /* GPP_C00: GPP_C0_SMBCLK */ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), @@ -187,8 +183,6 @@ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* GPP_D18: CLKREQ6_X4_GEN4_M2_SSD_N */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), - /* GPP_D19: X1_DT_PCIE_RST_N */ - PAD_CFG_GPO(GPP_D19, 1, PLTRST), /* GPP_D20: CSE_EARLY_SW */ PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL), /* GPP_D21: GPP_D21_UFS_REFCLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85523?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56c6fd3ea8b9e58933548543d195621da94c882e Gerrit-Change-Number: 85523 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85536?usp=email ) Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming ...................................................................... soc/intel/ptl: Enable UFS functionality by adding IRQ programming This commit adds the necessary IRQ programming for the UFS controller, addressing an issue where the device was not operational after booting to the OS. BUG=b:382243957 TEST=Built and booted google/fatcat successfully, verifying UFS functionality. with this patch ``` [SPEW ] Interrupt assignment: [SPEW ] Dxx:Fx INTx IRQ [SPEW ] D23:F0 1 018 ``` Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85536 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/fsp_params.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Divagar Mohandass: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Jayvik Desai: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index e0b0adf..dfc47c6 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -199,6 +199,14 @@ ANY_PIRQ(PCI_DEVFN_CSE_4), }, }, +#if CONFIG(SOC_INTEL_PANTHERLAKE_U_H) + { + .slot = PCI_DEV_SLOT_UFS, + .fns = { + ANY_PIRQ(PCI_DEVFN_UFS), + }, + }, +#endif { .slot = PCI_DEV_SLOT_SIO1, .fns = { -- To view, visit https://review.coreboot.org/c/coreboot/+/85536?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib479f0adaaae64cee4d2152534dae40e32614065 Gerrit-Change-Number: 85536 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Fix UFS ACPI _ADR calculation
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85528?usp=email ) Change subject: soc/intel/pantherlake: Fix UFS ACPI _ADR calculation ...................................................................... soc/intel/pantherlake: Fix UFS ACPI _ADR calculation This patch corrects the calculation of the _ADR value for the Intel UFS controller in the `soc/ufs.h` header file. The previous calculation incorrectly included a hardcoded value (0x0007) in the lower bits of the _ADR. This is not in line with the Panther Lake EDS specification (doc: 815002) BUG=b:382243957 TEST=Able to build and boot google/fatcat. > iasl -d /sys/firmware/acpi/tables/DSDT Device (UFS) { Name (_ADR, 0x00170000) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85528 Reviewed-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/soc/intel/pantherlake/include/soc/ufs.h 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Pranava Y N: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Divagar Mohandass: Looks good to me, but someone else must approve diff --git a/src/soc/intel/pantherlake/include/soc/ufs.h b/src/soc/intel/pantherlake/include/soc/ufs.h index ffd9b1f..e5a87e6 100644 --- a/src/soc/intel/pantherlake/include/soc/ufs.h +++ b/src/soc/intel/pantherlake/include/soc/ufs.h @@ -11,7 +11,7 @@ #include <soc/pci_devs.h> /* Calculate _ADR for Intel UFS Controller */ -#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16 | 0x0007) +#define UFS_ACPI_DEVICE (PCI_DEV_SLOT_UFS << 16) #define R_SCS_CFG_PCS 0x84 #define R_SCS_CFG_PG_CONFIG 0xA2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85528?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I889403e4d33efb5818fec06d773b5aec0a74d0b3 Gerrit-Change-Number: 85528 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s. BUG=b:376156567 TEST=Boot to OS and then check link speed. Use command: lspci -s 02:00.0 -vv | grep 'LnkSta' Before LnkSta: Speed 8GT/s (downgraded), Width x1 After LnkSta: Speed 5GT/s (downgraded), Width x1 Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85533 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Wu: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 880b3dd..4e554ab 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -294,6 +294,7 @@ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_pcie_speed = SPEED_GEN2, }" chip drivers/wifi/generic register "wake" = "GPE0_DW0_03" -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Subrata Banik (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rui Zhou. Subrata Banik has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85535?usp=email ) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:06:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add memory config
by John Su (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85542?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add memory config ...................................................................... Patch Set 4: (3 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/85542/comment/04d4eadc_c047c449?us… : PS3, Line 12: TEST=emerge-nissa coreboot > Do you already have access to the device, and run-tested your code? At this stage I don't have the device, but here we're following the reference design. File src/mainboard/google/brya/variants/uldrenite/memory.c: https://review.coreboot.org/c/coreboot/+/85542/comment/b3cf60f7_80d4d620?us… : PS3, Line 84: GPIO_MEM_CONFIG_3 GPP_E13 > Also use a tab? Done https://review.coreboot.org/c/coreboot/+/85542/comment/6c7b28f5_7c385d90?us… : PS3, Line 100: Alder Lake N > Alder Lake-N Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Gerrit-Change-Number: 85542 Gerrit-PatchSet: 4 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 02:02:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 01:59:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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