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Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support
......................................................................
soc/mediatek/mt8196: Add PMIF and PMIC driver support
Implement PMIF driver for communication between SoC and PMIC. Develop
SPMI driver for communication over the SPMI bus. Add necessary
configurations and base addresses to support PMIF.
TEST=build pass
BUG=b:317009620
Change-Id: I232015f45735ee5278b09d0352410617a1565177
Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/pmif.h
A src/soc/mediatek/mt8196/include/soc/spm.h
A src/soc/mediatek/mt8196/pmif_clk.c
A src/soc/mediatek/mt8196/pmif_init.c
A src/soc/mediatek/mt8196/pmif_spmi.c
7 files changed, 1,729 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85126/17
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Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
......................................................................
mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
After modified the settings, it could be met the time sequence for
this ILIT2901 touchscreen specification via our EE's measurements.
1. We will request vendor to update F/W, which delay calibration timing.
2. Change delay RST time to 12ms.
3. F/W calibration delay time is about 700ms after RST high
BUG=b:375986645
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. Verified the sequence correctly by EE.
Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca
Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/glassway/overridetree.cb
1 file changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/85363/5
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Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85363/comment/f70a2d64_306f20c4?us… :
PS4, Line 11: which delay calibration timing
> Each panel has its own firmware, and vendor will tune the timing settings in panel firmware and with […]
Done
https://review.coreboot.org/c/coreboot/+/85363/comment/8f054c55_f31cff5b?us… :
PS4, Line 12: Change
> Same description as above.
Done
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Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85363/comment/96021052_56bbac3b?us… :
PS4, Line 11: which delay calibration timing
> Sorry, I do not understand this part. It’d be great if you rephrased it.
Each panel has its own firmware, and vendor will tune the timing settings in panel firmware and with this CL that would be met the touchscreen power sequence via EE's reports.
https://review.coreboot.org/c/coreboot/+/85363/comment/e4da1118_84a15bcd?us… :
PS4, Line 12: Change
> Double
Same description as above.
https://review.coreboot.org/c/coreboot/+/85363/comment/9e726443_ba74516b?us… :
PS4, Line 14:
> Which firmware version di you test with?
Each firmware of panel might be specific requirement for the project. In this time, the tuned firmware version is 005c_0700.0000.0000.0006.bin.
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Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
......................................................................
mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s.
BUG=b:376156567
TEST=Boot to OS and then check link speed.
Use command: lspci -s 02:00.0 -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/jubilant/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85533/5
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Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85533/comment/5bcc9cf6_4b2f291b?us… :
PS3, Line 9: The decision to set PCIe root port 5 speed to Gen2 is based on experiment setup for b/376156567 and analysis results in comment #86.
> Please try to summarize the comments: […]
updated.
https://review.coreboot.org/c/coreboot/+/85533/comment/97c719ad_8daf1c2d?us… :
PS3, Line 9: The decision to set PCIe root port 5 speed to Gen2 is based on experiment setup for b/376156567 and analysis results in comment #86.
: The setting will fix the issue of Wifi 7 M.2 module doesn't work.
> Please reflow for 72 characters per line.
fixed.
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Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
......................................................................
mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s.
BUG=b:376156567
TEST=Boot to OS and then check link speed.
Use command: lspci -vv | grep 'LnkSta'
Before
LnkSta: Speed 8GT/s (downgraded), Width x1
After
LnkSta: Speed 5GT/s (downgraded), Width x1
Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/jubilant/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/85533/4
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Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
Patch Set 9:
(1 comment)
File src/lib/bootblock.c:
https://review.coreboot.org/c/coreboot/+/82695/comment/7d545581_4796212c?us… :
PS5, Line 62: if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK) && !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) {
> > So it sounds like we're going with the "always have MEASURED_BOOT initialize the TPM and then just […]
Sorry, I'm still not really following to be honest. So you're worried about the rare edge cases where the vboot code that calls `tpm_setup()` does extra stuff if it doesn't return success? But I still don't see what that has to do with STARTS_IN_BOOTBLOCK. You'd should have that same problem for STARTS_IN_ROMSTAGE as well if you initialize the TPM early and skip the vboot code for it.
I don't think any of these cases are really worth worrying about. The ones where it returns TPM_CB_MUST_REBOOT should really have been handled in the non-vboot instances of `tpm_setup()` already anyway, they're only in vboot because vboot wants to keep state for these reboots to avoid an endless reboot loop if something is severely broken. In practice this only really happens when the TPM is misconfigured in a weird way and can be resolved with a manual reset anyway.
The other case sets a recovery reason in vboot, but that's not a big deal because it would go into recovery mode from not reading correct secdata anyway. The only difference that makes is the reason code. And the SETUP_HIBERNATE_ON_ERR thing I honestly don't remember what that's there for, but it was a rare bug on Chromeboxes so if you're not using a Chromebox it probably doesn't matter.
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Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email )
Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/e99aac03_cf6111aa?us… :
PS4, Line 47: }
> I could not find a way to assign the GSI base address. […]
Agree. Thanks!
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