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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> do you wish to rebase this CL on main and i can merge it ?
Done
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Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85363/comment/380f64a4_a69565a6?us… :
PS4, Line 10: touchscreen specification
Please add the name of the specification.
https://review.coreboot.org/c/coreboot/+/85363/comment/05db5d38_791a8df0?us… :
PS4, Line 11: which delay calibration timing
Sorry, I do not understand this part. It’d be great if you rephrased it.
https://review.coreboot.org/c/coreboot/+/85363/comment/d3257fd7_97179a02?us… :
PS4, Line 12: Change
Double
https://review.coreboot.org/c/coreboot/+/85363/comment/e3bda951_a044f8be?us… :
PS4, Line 14:
Which firmware version di you test with?
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Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85195/comment/60f75e5c_8baea443?us… :
PS7, Line 12:
Were you able to test this? If yes, please add a TEST= entry maybe filled with the new debug logs?
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Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
......................................................................
Patch Set 7:
(1 comment)
File src/soc/amd/phoenix/pci_irq_routing.c:
https://review.coreboot.org/c/coreboot/+/85195/comment/14a37f0a_e06e4ad0?us… :
PS6, Line 18: reserved
> the reserved fields don't need to be named; see for example some of the bitfield structs in src/soc/ […]
Yep, those Jenkins warnings are annoying, but the struct looks better without the reserved names.
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Change subject: security: Allow vboot when INTEL_TXT enabled
......................................................................
Patch Set 9:
(1 comment)
File src/lib/bootblock.c:
https://review.coreboot.org/c/coreboot/+/82695/comment/52c8825a_b754ef70?us… :
PS5, Line 62: if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK) && !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) {
> So it sounds like we're going with the "always have MEASURED_BOOT initialize the TPM and then just have vboot assume it is already initialized" approach now, right?
Not quite. The ultimate goal is to be able to select TPM_MEASURED_BOOT_INIT_BOOTBLOCK with VBOOT (essentially to be able to select INTEL_TXT and have VBOOT) and still keep vboot happy. Having the vboot assume the TPM was already initialized will accomplish this.
> I'm just not sure why you are adding the extra !STARTS_IN_BOOTBLOCK check here
Because we lose the error information from vboot_setup_tpm if something goes wrong (as in my first answer to this thread). So my proposal was (at least for bootblock when both TPM_MEASURED_BOOT_INIT_BOOTBLOCK and VBOOT_STARTS_IN_BOOTBLOCK are selected) to skip initializing the TPM by bootblock itself.
To make it clearer: maybe I could add a function which can return the expected TPM initialization state `tpm_startup_should_run` (something like `verification_should_run` but for tpm_startup). Based on the current stage and state of vboot logic, we may clearly say when/where the startup happens and avoid INVALID_POSTINIT as much as possible.
Intel BootGuard/TXT has TPM_Startup success bits in the registers, which we could use to determine if the TPM_Sartup was issued by the ACM.
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
......................................................................
soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
Populate the PCI bridge IRQ routing table for Phoenix from the SMN
registers to replace the stub implementation. The base addresses are
copied from Genoa OpenSIL headers, which also correspond to Phoenix.
Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4
Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com>
---
M src/soc/amd/phoenix/pci_irq_routing.c
1 file changed, 62 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85195/7
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Change subject: intel/common/block: Program the right power_limits_config entry
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
@subratabanik@google.com and @kapilporwal@google.com, is there anyone on your side who could verify it works fine on Google MTL boards ? I tested on PTL.
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Hello Patrick Rudolph, build bot (Jenkins),
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Change subject: Documentation: Convert cbfs.txt to markdown
......................................................................
Documentation: Convert cbfs.txt to markdown
Convert the document to Markdown while retaining the original for
legacy purposes. Needs to be updated in a follow-up commit as it
doesn't reflect the latest coreboot version.
Original commit is CB:33663
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Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com>
---
A Documentation/architecture_and_design/lib/cbfs.md
M Documentation/architecture_and_design/lib/index.md
2 files changed, 374 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85541/2
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