coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Subrata Banik (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Jayvik Desai, Julius Werner, Kapil Porwal, Paul Menzel. Subrata Banik has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 11: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/85326/comment/2edde0d2_fe984ef1?us… : PS9, Line 286: printk > > Please call stopwatch_tick() before accessing sw.current. > > Added > > > The absolute timestamp isn't really meant to be accessed at all. Is there a reason to print it here (rather than just the duration)? coreboot timers aren't guaranteed to start at 0 at boot, so absolute timer values are basically meaningless anyway. > > you are right, the timestamps doesn't make much sense, the only reason it's there is because some external team required it at some point. > > Removed. I still believe adding entry inside cbmem is better as this will solve two problems 1. Allow partners to measure the time takes for each host cmd w/o any additional parsing 2. Allow platform team like us to debug boot regression easilly, we just need to enable some Kconfig to verbose the EC host cmd telemetry data. -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 11 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 16:31:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[S] Change in coreboot[main]: Documentation: Convert AMD-S3.txt to markdown
by Nick Kochlowski (Code Review) 09 Dec '24

09 Dec '24

Nick Kochlowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85543?usp=email ) Change subject: Documentation: Convert AMD-S3.txt to markdown ...................................................................... Documentation: Convert AMD-S3.txt to markdown Convert the document to Markdown to be rendered as a link within the AMD index page. Change-Id: I56647c9e2d96c3cdfbe0a870496bb892f6e0c6f7 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- R Documentation/architecture_and_design/soc/amd/AMD-S3.md M Documentation/architecture_and_design/soc/amd/index.md 2 files changed, 23 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/85543/1 diff --git a/Documentation/architecture_and_design/soc/amd/AMD-S3.txt b/Documentation/architecture_and_design/soc/amd/AMD-S3.md similarity index 88% rename from Documentation/architecture_and_design/soc/amd/AMD-S3.txt rename to Documentation/architecture_and_design/soc/amd/AMD-S3.md index bfabcbe..e0f3f4b 100644 --- a/Documentation/architecture_and_design/soc/amd/AMD-S3.txt +++ b/Documentation/architecture_and_design/soc/amd/AMD-S3.md @@ -1,3 +1,4 @@ +```shell _____ ____ _____ ______ ____ ____ ____ _______ / ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __| | | | | | | |__) | |__ | |_) | | | | | | | | | @@ -12,21 +13,20 @@ / ____ \| | | | |__| | ____) | ___) | /_/ \_\_| |_|_____/ |_____/ |____/ +``` - S3 in coreboot (V 1.2) ----------------------------------------- - Zheng Bao - <zheng.bao(a)amd.com> - <fishbaozi(a)gmail.com> +# S3 in coreboot (V 1.2) -Introduction -============ +**Author:** Zheng Bao +<zheng.bao(a)amd.com> +<fishbaozi(a)gmail.com> + +## Introduction This document is about how the feature S3 is implemented on coreboot, specifically on AMD platform. This topic deals with ACPI spec, hardware, BIOS, OS. We try to help coreboot users to realize their own S3. -S3 in a nutshell -================ +## S3 in a nutshell The S3 sleeping state is a low wake latency sleeping state where all system context is lost except system memory. [1]. S3 is a ACPI definition. @@ -52,8 +52,7 @@ to linux kernel or some other open source projects to find out how they handle S3 resume. -ACPI registers -============== +## ACPI registers ACPI specification defines a group of registers. OSes handle all these registers to read and write status to all the platform. On AMD platform, these registers are provided by southbridge. For @@ -62,8 +61,7 @@ are. BIOS has the responsibility to allocated the IO resources and write all these address to FADT, a ACPI defined table. -Memory Layout -============= +## Memory Layout Restoring memory is the most important job done by BIOS. When the power is off, the memory is maintained by standby power. BIOS need to make sure that when flow goes to OS, everything in memory should be @@ -86,8 +84,7 @@ 2efe0000 --- 2f000000 heap in highmem 2f000000 TOM -AMD requirements in S3 -====================== +## AMD requirements in S3 Chip vendor like AMD will provide bunch of routines to restore the board.[2] * AmdS3Save: It is called in cold boot, save required register into @@ -99,8 +96,7 @@ Provided by Southbridge vendor code. Early is called before PCI enumeration, and Late is called after that. -Lifecycle of booting, sleeping and waking coreboot and Ubuntu -============================================================= +## Lifecycle of booting, sleeping and waking coreboot and Ubuntu 1. Cold boot. For a system with S3 feature, the BIOS needs to save some data to non-volatile storage at cold boot stage. What data need to be save are @@ -115,16 +111,18 @@ 2. OS goes in S3. For Linux, besides the kernel needs to do some saving, most distributions run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d. - # ls /usr/lib/pm-utils/sleep.d + ```shell + # ls /usr/lib/pm-utils/sleep.d 000kernel-change 49bluetooth 90clock 95led 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler 00powersave 60_wpa_supplicant 95anacron 99video 01PulseAudio 75modules 95hdparm-apm -The script with lower prefix runs before the one with higher prefix. -99video is the last one. -Those scripts have hooks called hibernate, suspend, thaw, resume. For -each script, suspend is called when system sleeps and wakeup is called -when system wakeups. + ``` + The script with lower prefix runs before the one with higher prefix. + 99video is the last one. + Those scripts have hooks called hibernate, suspend, thaw, resume. For + each script, suspend is called when system sleeps and wakeup is called + when system wakeups. 3. Firmware detects S3 wakeup As we mentioned, Firmware detects the SLP_TYPx to find out if the board @@ -144,8 +142,7 @@ coreboot/Kconfig. That needs more troubleshooting. -Reference -========= +## Reference [1] ACPI40a, http://www.acpi.info/spec40a.htm [2] coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/ [3] coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c diff --git a/Documentation/architecture_and_design/soc/amd/index.md b/Documentation/architecture_and_design/soc/amd/index.md index 0ad8816..1c81f3c 100644 --- a/Documentation/architecture_and_design/soc/amd/index.md +++ b/Documentation/architecture_and_design/soc/amd/index.md @@ -10,6 +10,7 @@ Family 15h <family15h.md> Family 17h <family17h.md> Platform Security Processor Integration <psp_integration.md> +S3 Feature Implementation <AMD-S3.md> ``` ## amd_blobs Repository License -- To view, visit https://review.coreboot.org/c/coreboot/+/85543?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56647c9e2d96c3cdfbe0a870496bb892f6e0c6f7 Gerrit-Change-Number: 85543 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by Subrata Banik (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/uldrenite/variant.c: https://review.coreboot.org/c/coreboot/+/85537/comment/96da98d6_9238ef1a?us… : PS1, Line 24: variant_init looks like we will increase the boot time by 50ms. this is 5% of total boot time. Can't this be managed by ACPI code at runtime ? why we need to perform the WWAN init seq in AP FW ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Dec 2024 16:29:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add memory config
by Subrata Banik (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85542?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add memory config ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Gerrit-Change-Number: 85542 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 09 Dec 2024 16:27:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Felix Held (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski. Felix Held has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/soc/amd/phoenix/pci_irq_routing.c: https://review.coreboot.org/c/coreboot/+/85195/comment/8d28cb84_2aa1aac0?us… : PS6, Line 18: reserved the reserved fields don't need to be named; see for example some of the bitfield structs in src/soc/amd/phoenix/include/soc/data_fabric.h. same below. jenkins will complain about those a bit, but that's mainly due to it being a rather uncommon thing and jenkins not knowing that construct, so i've just ignored jenkins' comments on those -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 6 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 16:01:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add memory config
by John Su (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85542?usp=email to look at the new patch set (#3). Change subject: mb/google/trulo/var/uldrenite: Add memory config ...................................................................... mb/google/trulo/var/uldrenite: Add memory config Fill in memory config based on the schematic_20241203. BUG=b:380476928, b:380789023 TEST=emerge-nissa coreboot Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/Makefile.mk A src/mainboard/google/brya/variants/uldrenite/memory.c 2 files changed, 114 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85542/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Gerrit-Change-Number: 85542 Gerrit-PatchSet: 3 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by Paul Menzel (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Ren Kuo. Paul Menzel has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85533/comment/3894fee4_ac7c2551?us… : PS3, Line 9: The decision to set PCIe root port 5 speed to Gen2 is based on experiment setup for b/376156567 and analysis results in comment #86. Please try to summarize the comments: Currently, with default speed X the Wifi 7 M.2 module is not detected by coreboot/Linux(?). This is due to Y, and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s. -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 15:33:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by Paul Menzel (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Karthik Ramasubramanian, Ren Kuo. Paul Menzel has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85533/comment/a35bb356_bb5bd9ef?us… : PS3, Line 9: The decision to set PCIe root port 5 speed to Gen2 is based on experiment setup for b/376156567 and analysis results in comment #86. : The setting will fix the issue of Wifi 7 M.2 module doesn't work. Please reflow for 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 15:31:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add PCU PCI drivers
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85316?usp=email ) Change subject: soc/intel/xeon_sp: Add PCU PCI drivers ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Gerrit-Change-Number: 85316 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 15:07:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... Patch Set 11: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85170/comment/1e787218_be485b4b?us… : PS7, Line 10: all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, > > `'excat' may be misspelled - perhaps 'exact'?` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 15:06:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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coreboot-gerrit December 2024