coreboot-gerrit December 2024

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[S] Change in coreboot[main]: arch/x86: Rename breakpoint removal function
by Patrick Rudolph (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Andrey Petrov, Jérémy Compostella, Ronak Kanabar. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85540?usp=email ) Change subject: arch/x86: Rename breakpoint removal function ...................................................................... arch/x86: Rename breakpoint removal function Match function name "init" with "remove" by renaming all *_breakpoint_disable() to *_breakpoint_remove(). Change-Id: Id3da25cfa6fc0594887f3112e269e57e8ecb32b3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/include/arch/null_breakpoint.h M src/arch/x86/include/arch/stack_canary_breakpoint.h M src/arch/x86/null_breakpoint.c M src/arch/x86/stack_canary_breakpoint.c M src/device/oprom/realmode/x86.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c 8 files changed, 21 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85540/1 diff --git a/src/arch/x86/include/arch/null_breakpoint.h b/src/arch/x86/include/arch/null_breakpoint.h index 9d69d3c..030ebee 100644 --- a/src/arch/x86/include/arch/null_breakpoint.h +++ b/src/arch/x86/include/arch/null_breakpoint.h @@ -7,13 +7,13 @@ /* Places data and instructions breakpoints at address zero. */ void null_breakpoint_init(void); -void null_breakpoint_disable(void); +void null_breakpoint_remove(void); #else static inline void null_breakpoint_init(void) { /* Not implemented */ } -static inline void null_breakpoint_disable(void) +static inline void null_breakpoint_remove(void) { /* Not implemented */ } diff --git a/src/arch/x86/include/arch/stack_canary_breakpoint.h b/src/arch/x86/include/arch/stack_canary_breakpoint.h index 98c7922..01ab5e2 100644 --- a/src/arch/x86/include/arch/stack_canary_breakpoint.h +++ b/src/arch/x86/include/arch/stack_canary_breakpoint.h @@ -7,13 +7,13 @@ /* Places a data breakpoint at stack canary. */ void stack_canary_breakpoint_init(void); -void stack_canary_breakpoint_disable(void); +void stack_canary_breakpoint_remove(void); #else static inline void stack_canary_breakpoint_init(void) { /* Not implemented */ } -static inline void stack_canary_breakpoint_disable(void) +static inline void stack_canary_breakpoint_remove(void) { /* Not implemented */ } diff --git a/src/arch/x86/null_breakpoint.c b/src/arch/x86/null_breakpoint.c index 44c7ae9..e07566f 100644 --- a/src/arch/x86/null_breakpoint.c +++ b/src/arch/x86/null_breakpoint.c @@ -58,16 +58,16 @@ create_instruction_breakpoint(); } -void null_breakpoint_disable(void) +void null_breakpoint_remove(void) { breakpoint_remove(null_fetch_bp); breakpoint_remove(null_deref_bp); } -static void null_breakpoint_disable_hook(void *unused) +static void null_breakpoint_remove_hook(void *unused) { - null_breakpoint_disable(); + null_breakpoint_remove(); } -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_remove_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_remove_hook, NULL); diff --git a/src/arch/x86/stack_canary_breakpoint.c b/src/arch/x86/stack_canary_breakpoint.c index 6db8d63..d1dc3c3 100644 --- a/src/arch/x86/stack_canary_breakpoint.c +++ b/src/arch/x86/stack_canary_breakpoint.c @@ -49,15 +49,15 @@ create_stack_canary_breakpoint(addr); } -void stack_canary_breakpoint_disable(void) +void stack_canary_breakpoint_remove(void) { breakpoint_remove(stack_canary_bp); } -static void stack_canary_breakpoint_disable_hook(void *unused) +static void stack_canary_breakpoint_remove_hook(void *unused) { - stack_canary_breakpoint_disable(); + stack_canary_breakpoint_remove(); } -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, stack_canary_breakpoint_disable_hook, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, stack_canary_breakpoint_disable_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, stack_canary_breakpoint_remove_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, stack_canary_breakpoint_remove_hook, NULL); diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index c3adf40..15dd8b5 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -181,7 +181,7 @@ /* It's expected that we write to the NULL page in the first two iterations of the following loop, so temporarily disable the NULL breakpoint. */ - null_breakpoint_disable(); + null_breakpoint_remove(); /* Copy IDT stub code for each interrupt. This might seem wasteful * but it is really simple diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 39d7ce9..ce0d283 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -412,8 +412,8 @@ fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); /* FSP disables the interrupt handler so remove debug exceptions temporarily */ - null_breakpoint_disable(); - stack_canary_breakpoint_disable(); + null_breakpoint_remove(); + stack_canary_breakpoint_remove(); post_code(POSTCODE_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 3ec78d5..358589d 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -78,8 +78,8 @@ post_code(data->post_code_before); /* FSP disables the interrupt handler so remove debug exceptions temporarily */ - null_breakpoint_disable(); - stack_canary_breakpoint_disable(); + null_breakpoint_remove(); + stack_canary_breakpoint_remove(); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params); else diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 1e1ff99..1caf00f 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -132,8 +132,8 @@ post_code(POSTCODE_FSP_SILICON_INIT); /* FSP disables the interrupt handler so remove debug exceptions temporarily */ - null_breakpoint_disable(); - stack_canary_breakpoint_disable(); + null_breakpoint_remove(); + stack_canary_breakpoint_remove(); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); else -- To view, visit https://review.coreboot.org/c/coreboot/+/85540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3da25cfa6fc0594887f3112e269e57e8ecb32b3 Gerrit-Change-Number: 85540 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/lbg: Add support to hide HDA
by Patrick Rudolph (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Hello Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Paul Menzel, Shuo Liu, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85496?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Paul Menzel, Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA ...................................................................... soc/intel/xeon_sp/lbg: Add support to hide HDA The azalia audio device is usually unused on server platforms. Add code to hide it since FSP lacks this option and there's no official bit in the IFD to disable it. The device is disabled early to: 1. Prevent FSP from seeing the device being present. It could keep an internal state that the device is working. 2. Prevent FSP-M from trying to detect codecs. This would increase boot time. 3. Prevent FSP from becomming confused or crash when the device is suddently missing as disabled by a ramstage PCI driver. TEST: No HDA PCI device visible on ocp/tiogapass. Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lbg/Makefile.mk A src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h M src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/lbg/include/soc/pmc.h M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/skx/romstage.c 8 files changed, 56 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85496/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Gerrit-Change-Number: 85496 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Patrick Rudolph (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Hello Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85170?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+2 by Angel Pons, Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... soc/intel/xeon_sp/skx: Configure IOAPICs FSP only configures the PCH IOAPIC. Let coreboot reconfigure all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI address for each IOAPIC instead of assume it's a linear address space. Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info() from advertising wrong GSI addresses. TEST: Booted on ocp/tiogapass with correct GSI bases asigned matching the _PRT advertised GSI bases. Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2. See Document Reference Number: 329595-002 Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/lpc_gen1.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk A src/soc/intel/xeon_sp/skx/ioapic.c 4 files changed, 74 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85170/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Patrick Rudolph (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Morgan Jang, Shuo Liu, yuchi.chen(a)intel.com. Hello Angel Pons, Christian Walter, Johnny Lin, Morgan Jang, Shuo Liu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85492?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+1 by Christian Walter, Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... mb/ocp/tiogapass: Wait for BMC The mainboard code relies on IPMI communication with the BMC. Since the x86 and BMC start booting at the same time on ACPI G3 exit and the x86 is a bit faster, wait for the BMC to signal it's done booting by pulling GPP_F4 low. Fixes lot's of error messages about not working IPMI. TEST: Once GPP_F4 is low IPMI communication over the KCS is also working on ocp/tiogapass. Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h M src/mainboard/ocp/tiogapass/romstage.c 2 files changed, 29 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/85492/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add PCU PCI drivers
by Patrick Rudolph (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85316?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add PCU PCI drivers ...................................................................... soc/intel/xeon_sp: Add PCU PCI drivers Move PCU specific code into separate files: - PCUs registers are now locked by the PCI driver final call - set_bios_init_completion() is not part of PCU1 driver - Integrate config_reset_cpl3_csrs() into PCU driver TEST: Still boots on ocp/tiogapass. Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/Makefile.mk M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/include/soc/pcu.h M src/soc/intel/xeon_sp/include/soc/util.h A src/soc/intel/xeon_sp/pcu0.c A src/soc/intel/xeon_sp/pcu1.c A src/soc/intel/xeon_sp/pcu2.c A src/soc/intel/xeon_sp/pcu3.c A src/soc/intel/xeon_sp/pcu6.c M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/Makefile.mk M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/util.c 21 files changed, 457 insertions(+), 581 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85316/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4a58b80a1c9fd766946b17c11c629a9df79c573 Gerrit-Change-Number: 85316 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85284?usp=email ) Change subject: soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq ...................................................................... soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq pcr_read16(PID_ITSS, itss_soc_get_on_chip_dev_pir(dev)) returns the register content and should not be compared with PCI_ITSS_PIR(0) which is an address offset. By now, we assume the returned PIR is always effective and usable. Change-Id: I2e61629bdcdea33f260bfbc47f22d40d9a869c6b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85284 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: <yuchi.chen(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/itss/itss.c 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified yuchi.chen(a)intel.com: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index e2ff3ef..8409e96 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -142,8 +142,6 @@ return PIRQ_INVALID; uint16_t pir = pcr_read16(PID_ITSS, itss_soc_get_on_chip_dev_pir(dev)); - if (pir < PCI_ITSS_PIR(0)) - return PIRQ_INVALID; /* The lower 3 bits of every 4 bits indicates which PIRQ is connect to INT. */ unsigned int pir_shift = (pin - PCI_INT_A) * 4; -- To view, visit https://review.coreboot.org/c/coreboot/+/85284?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e61629bdcdea33f260bfbc47f22d40d9a869c6b Gerrit-Change-Number: 85284 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[XS] Change in coreboot[main]: soc/intel/common/block: Add const qualifier for input of pirq ops
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85283?usp=email ) Change subject: soc/intel/common/block: Add const qualifier for input of pirq ops ...................................................................... soc/intel/common/block: Add const qualifier for input of pirq ops Add const qualifer for itss_get_on_chip_dev_pirq and itss_soc_get_on_chip_dev_pir so that these ops could be used for both struct device * input and const struct device * input. Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85283 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/itss/itss.c M src/soc/intel/snowridge/itss.c 3 files changed, 4 insertions(+), 4 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified yuchi.chen(a)intel.com: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/include/intelblocks/itss.h b/src/soc/intel/common/block/include/intelblocks/itss.h index 45a71cc..0a9e365 100644 --- a/src/soc/intel/common/block/include/intelblocks/itss.h +++ b/src/soc/intel/common/block/include/intelblocks/itss.h @@ -48,10 +48,10 @@ void itss_clock_gate_8254(void); /* SoC implementation to return corresponding PIR register offset. */ -uint32_t itss_soc_get_on_chip_dev_pir(struct device *dev); +uint32_t itss_soc_get_on_chip_dev_pir(const struct device *dev); /* Return which PIRQx the device's INTx is connected to. */ -enum pirq itss_get_on_chip_dev_pirq(struct device *dev, enum pci_pin pin); +enum pirq itss_get_on_chip_dev_pirq(const struct device *dev, enum pci_pin pin); #endif /* !defined(__ACPI__) */ diff --git a/src/soc/intel/common/block/itss/itss.c b/src/soc/intel/common/block/itss/itss.c index 4d9b7a5..e2ff3ef 100644 --- a/src/soc/intel/common/block/itss/itss.c +++ b/src/soc/intel/common/block/itss/itss.c @@ -135,7 +135,7 @@ show_irq_polarities("After"); } -enum pirq itss_get_on_chip_dev_pirq(struct device *dev, enum pci_pin pin) +enum pirq itss_get_on_chip_dev_pirq(const struct device *dev, enum pci_pin pin) { /* Check if device is on chip. */ if (dev->upstream->dev->path.type != DEVICE_PATH_DOMAIN) diff --git a/src/soc/intel/snowridge/itss.c b/src/soc/intel/snowridge/itss.c index 07f5b1d..7f2b567 100644 --- a/src/soc/intel/snowridge/itss.c +++ b/src/soc/intel/snowridge/itss.c @@ -11,7 +11,7 @@ #include "ramstage.h" -uint32_t itss_soc_get_on_chip_dev_pir(struct device *dev) +uint32_t itss_soc_get_on_chip_dev_pir(const struct device *dev) { /* Check if device is on chip. */ if (dev->upstream->dev->path.type != DEVICE_PATH_DOMAIN) -- To view, visit https://review.coreboot.org/c/coreboot/+/85283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I65b4de3f51b109bfcabfaa0ebe47a22bdd69d1a0 Gerrit-Change-Number: 85283 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove lpc_lockdown_config
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85286?usp=email ) Change subject: soc/intel/xeon_sp: Remove lpc_lockdown_config ...................................................................... soc/intel/xeon_sp: Remove lpc_lockdown_config If CHIPSET_LOCKDOWN_COREBOOT is selected, lpc_lockdown_config() will be executed in common pch/lockdown firstly. Remove xeon_sp layer lpc_lockdown_config() to avoid duplication. The duplicated part are in src/soc/intel/common/pch/lockdown/lockdown.c: static void platform_lockdown_config(void *unused) { int chipset_lockdown; chipset_lockdown = get_lockdown_config(); /* SPI lock down configuration */ fast_spi_lockdown_cfg(chipset_lockdown); /* LPC/eSPI lock down configuration */ lpc_lockdown_config(chipset_lockdown); ... } Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85286 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/lockdown.c 1 file changed, 0 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index a3d17b4..f638c2b 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -6,25 +6,11 @@ #include <soc/lockdown.h> #include <soc/pm.h> -static void lpc_lockdown_config(void) -{ - /* Set BIOS Interface Lock, BIOS Lock */ - lpc_set_bios_interface_lock_down(); - - /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { - lpc_set_eiss(); - lpc_enable_wp(); - } - lpc_set_lock_enable(); -} - void soc_lockdown_config(int chipset_lockdown) { if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP) return; - lpc_lockdown_config(); pmc_lockdown_config(); sata_lockdown_config(chipset_lockdown); spi_lockdown_config(chipset_lockdown); -- To view, visit https://review.coreboot.org/c/coreboot/+/85286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibec389a6d55c7885def6896a0ea435514b75a323 Gerrit-Change-Number: 85286 Gerrit-PatchSet: 4 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: haswell NRI: Initialise MPLL
by Lean Sheng Tan (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Maximilian Brune, Nico Huber, Patrick Rudolph. Lean Sheng Tan has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/64184?usp=email ) Change subject: haswell NRI: Initialise MPLL ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/64184?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6 Gerrit-Change-Number: 64184 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 09 Dec 2024 13:46:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add debug timestamp for host EC commands
by Jayvik Desai (Code Review) 09 Dec '24

09 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Julius Werner, Kapil Porwal, Paul Menzel, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85326?usp=email ) Change subject: ec/google/chromeec: Add debug timestamp for host EC commands ...................................................................... Patch Set 11: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/85326/comment/347e64ef_195a475b?us… : PS9, Line 286: printk > Please call stopwatch_tick() before accessing sw.current. Added > The absolute timestamp isn't really meant to be accessed at all. Is there a reason to print it here (rather than just the duration)? coreboot timers aren't guaranteed to start at 0 at boot, so absolute timer values are basically meaningless anyway. you are right, the timestamps doesn't make much sense, the only reason it's there is because some external team required it at some point. Removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ab89830ede940d2237ad21187b137dca9689fb0 Gerrit-Change-Number: 85326 Gerrit-PatchSet: 11 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Mon, 09 Dec 2024 13:28:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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