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Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/ptl: Enable UFS functionality by adding IRQ programming
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 11:
(1 comment)
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/9090fa1c_dfe3cbe9?us… :
PS10, Line 42: assert (dn.stack < MAX_LOGIC_IIO_STACK);
> Almost done.
Done
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Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com.
Hello Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85170?usp=email
to look at the new patch set (#11).
Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
soc/intel/xeon_sp/skx: Configure IOAPICs
FSP only configures the PCH IOAPIC. Let coreboot reconfigure
all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs,
and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact
GSI address for each IOAPIC instead of assume it's a linear address
space.
Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.
TEST: Booted on ocp/tiogapass with correct GSI bases asigned
matching the _PRT advertised GSI bases.
Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002
Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/lpc_gen1.c
M src/soc/intel/xeon_sp/skx/Kconfig
M src/soc/intel/xeon_sp/skx/Makefile.mk
A src/soc/intel/xeon_sp/skx/ioapic.c
4 files changed, 74 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85170/11
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA
......................................................................
soc/intel/xeon_sp/lbg: Add support to hide HDA
The azalia audio device is usually unused on server platforms.
Add code to hide it since FSP lacks this option and there's no
official bit in the IFD to disable it. The device is disabled
early to:
1. Prevent FSP from seeing the device being present. It could keep
an internal state that the device is working.
2. Prevent FSP-M from trying to detect codecs. This would increase
boot time.
3. Prevent FSP from becoming confused or crash when the device is
suddently missing as disabled by a ramstage PCI driver.
TEST: No HDA PCI device visible on ocp/tiogapass.
Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/lbg/Makefile.mk
A src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h
M src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h
M src/soc/intel/xeon_sp/lbg/include/soc/pmc.h
M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h
M src/soc/intel/xeon_sp/lbg/soc_pch.c
M src/soc/intel/xeon_sp/skx/romstage.c
8 files changed, 56 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/85496/6
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Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85457?usp=email )
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Change subject: mb/google/fatcat: Enable Intel DPTF support and configure policies
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
do you wish to rebase this CL on main and i can merge it ?
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Change subject: mb/google/trulo/var/uldrenite: Add memory config
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/xeon_sp/skx/ioapic.c:
https://review.coreboot.org/c/coreboot/+/85170/comment/0a40cdd4_1e91d95d?us… :
PS10, Line 42: assert (dn.stack < MAX_LOGIC_IIO_STACK);
> Will fix.
Almost done.
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