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Change subject: ec/google/chromeec: Add indexed IO support
......................................................................
Patch Set 2:
(1 comment)
File src/ec/google/chromeec/ec_lpc.c:
https://review.coreboot.org/c/coreboot/+/85449/comment/53dc2613_9202e5a7?us… :
PS2, Line 169: EC_LPC_ADDR_MEMMAP
> This would be a different address.
yes, I am planning to add another patch that updates the EC_LPC_ADDR_MEMMAP.
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Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/uldrenite/variant.c:
https://review.coreboot.org/c/coreboot/+/85537/comment/8da3fba9_e53082cf?us… :
PS1, Line 24: variant_init
> > Because we currently do not have the board and keypart for verification, so if can merge this CL f […]
Created issue b/383212261 to track it.
And the proto board is obtained, I will change it and reduce boot time.
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Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
......................................................................
mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
Uldrenite support WWAN 5G device, use variant.c to handle the
power on sequence for WWAN RW350R-GL.
BUG=b:381393809, b:383212261
BRANCH=None
TEST=emerge-nissa coreboot
Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/uldrenite/Makefile.mk
A src/mainboard/google/brya/variants/uldrenite/variant.c
2 files changed, 38 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85537/2
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Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................
Patch Set 14: Code-Review+2
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Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................
Patch Set 14: Code-Review+2
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
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Verified+1 by build bot (Jenkins)
Change subject: intel/common/block: Program the right power_limits_config entry
......................................................................
intel/common/block: Program the right power_limits_config entry
When variant_update_cpu_power_limits() programs PL4, it systematically
sets the first entry of the power_limits_config SoC chip data
structure. This approach is problematic because the current SoC SKU
may align with a different data structure entry, introducing
inconsistencies.
This commit introduces the power_limits_index field to the
cpu_tdp_power_limits data structure. This field specifies the specific
power limits entry that should be updated.
All data structures utilized by this function are updated accordingly.
BUG=b:380408956
TEST=Able to retrieve collect 28W power_limit.
Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c
M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c
M src/mainboard/google/rex/variants/deku/ramstage.c
M src/mainboard/google/rex/variants/screebo/variant.c
M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c
M src/soc/intel/common/block/include/intelblocks/power_limit.h
M src/soc/intel/common/block/power_limit/power_limit.c
7 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/85244/12
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