coreboot-gerrit December 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu, yuchi.chen(a)intel.com. Lean Sheng Tan has uploaded a new patch set (#12) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... soc/intel/xeon_sp/skx: Configure IOAPICs FSP only configures the PCH IOAPIC. Let coreboot reconfigure all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI address for each IOAPIC instead of assume it's a linear address space. Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info() from advertising wrong GSI addresses. TEST: Booted on ocp/tiogapass with correct GSI bases asigned matching the _PRT advertised GSI bases. Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2. See Document Reference Number: 329595-002 Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/lpc_gen1.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk A src/soc/intel/xeon_sp/skx/ioapic.c 4 files changed, 74 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85170/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85128?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... Patch Set 23: Code-Review+2 (1 comment) File src/soc/mediatek/common/mt6363_sdmadc.c: https://review.coreboot.org/c/coreboot/+/85128/comment/3e2f77ee_60ffdc7e?us… : PS23, Line 64: int > unsigned int enum auxadc_channel -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 23 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 08:55:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in blobs[main]: soc/meidatek/mt8196/blobs: Add SPM firmware v1.0
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Wenzhen Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Wenzhen Yu. ( https://review.coreboot.org/c/blobs/+/85285?usp=email ) Change subject: soc/meidatek/mt8196/blobs: Add SPM firmware v1.0 ...................................................................... Patch Set 5: (2 comments) Patchset: PS4: > Please correct the file name to `spm_firmware.bin`. Done Patchset: PS5: Please rebase -- To view, visit https://review.coreboot.org/c/blobs/+/85285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic5b5417b9b746fcca225209d9b17108a2499ac71 Gerrit-Change-Number: 85285 Gerrit-PatchSet: 5 Gerrit-Owner: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 08:53:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
by Daniel Peng (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Daniel Peng has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/85363?usp=email ) Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence ...................................................................... Patch Set 6: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85363/comment/ac772b79_58af1339?us… : PS4, Line 10: touchscreen specification > I do not see it. Sorry. I don't understand what your mean for not see it. I'll confirm with our EE what they refer for the document of the touchscreen specification. https://review.coreboot.org/c/coreboot/+/85363/comment/6a26379b_8b7c82cf?us… : PS4, Line 12: Change > My suggestion is: […] Done https://review.coreboot.org/c/coreboot/+/85363/comment/064a166a_91741e69?us… : PS4, Line 14: > Please add it to the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Gerrit-Change-Number: 85363 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 08:51:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
by Daniel Peng (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85363?usp=email to look at the new patch set (#6). Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence ...................................................................... mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence After modified the settings, it could be met the time sequence for this ILIT2901 touchscreen specification via our EE's measurements. 1. We will request vendor to update F/W, which delay calibration timing. 2. Double delay RST time to 12ms. 3. F/W calibration delay time is about 700ms after RST high. The tuned firmware version is 005c_0700.0000.0000.0006.bin. BUG=b:375986645 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. Verified the sequence correctly by EE. Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/variants/glassway/overridetree.cb 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/85363/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Gerrit-Change-Number: 85363 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[S] Change in coreboot[main]: arch/x86: Rename breakpoint removal function
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85540?usp=email ) Change subject: arch/x86: Rename breakpoint removal function ...................................................................... arch/x86: Rename breakpoint removal function Match function name "init" with "remove" by renaming all *_breakpoint_disable() to *_breakpoint_remove(). Change-Id: Id3da25cfa6fc0594887f3112e269e57e8ecb32b3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85540 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/null_breakpoint.h M src/arch/x86/include/arch/stack_canary_breakpoint.h M src/arch/x86/null_breakpoint.c M src/arch/x86/stack_canary_breakpoint.c M src/device/oprom/realmode/x86.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c 8 files changed, 21 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/arch/x86/include/arch/null_breakpoint.h b/src/arch/x86/include/arch/null_breakpoint.h index 9d69d3c..030ebee 100644 --- a/src/arch/x86/include/arch/null_breakpoint.h +++ b/src/arch/x86/include/arch/null_breakpoint.h @@ -7,13 +7,13 @@ /* Places data and instructions breakpoints at address zero. */ void null_breakpoint_init(void); -void null_breakpoint_disable(void); +void null_breakpoint_remove(void); #else static inline void null_breakpoint_init(void) { /* Not implemented */ } -static inline void null_breakpoint_disable(void) +static inline void null_breakpoint_remove(void) { /* Not implemented */ } diff --git a/src/arch/x86/include/arch/stack_canary_breakpoint.h b/src/arch/x86/include/arch/stack_canary_breakpoint.h index 98c7922..01ab5e2 100644 --- a/src/arch/x86/include/arch/stack_canary_breakpoint.h +++ b/src/arch/x86/include/arch/stack_canary_breakpoint.h @@ -7,13 +7,13 @@ /* Places a data breakpoint at stack canary. */ void stack_canary_breakpoint_init(void); -void stack_canary_breakpoint_disable(void); +void stack_canary_breakpoint_remove(void); #else static inline void stack_canary_breakpoint_init(void) { /* Not implemented */ } -static inline void stack_canary_breakpoint_disable(void) +static inline void stack_canary_breakpoint_remove(void) { /* Not implemented */ } diff --git a/src/arch/x86/null_breakpoint.c b/src/arch/x86/null_breakpoint.c index 44c7ae9..e07566f 100644 --- a/src/arch/x86/null_breakpoint.c +++ b/src/arch/x86/null_breakpoint.c @@ -58,16 +58,16 @@ create_instruction_breakpoint(); } -void null_breakpoint_disable(void) +void null_breakpoint_remove(void) { breakpoint_remove(null_fetch_bp); breakpoint_remove(null_deref_bp); } -static void null_breakpoint_disable_hook(void *unused) +static void null_breakpoint_remove_hook(void *unused) { - null_breakpoint_disable(); + null_breakpoint_remove(); } -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_disable_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, null_breakpoint_remove_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, null_breakpoint_remove_hook, NULL); diff --git a/src/arch/x86/stack_canary_breakpoint.c b/src/arch/x86/stack_canary_breakpoint.c index 6db8d63..d1dc3c3 100644 --- a/src/arch/x86/stack_canary_breakpoint.c +++ b/src/arch/x86/stack_canary_breakpoint.c @@ -49,15 +49,15 @@ create_stack_canary_breakpoint(addr); } -void stack_canary_breakpoint_disable(void) +void stack_canary_breakpoint_remove(void) { breakpoint_remove(stack_canary_bp); } -static void stack_canary_breakpoint_disable_hook(void *unused) +static void stack_canary_breakpoint_remove_hook(void *unused) { - stack_canary_breakpoint_disable(); + stack_canary_breakpoint_remove(); } -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, stack_canary_breakpoint_disable_hook, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, stack_canary_breakpoint_disable_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, stack_canary_breakpoint_remove_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, stack_canary_breakpoint_remove_hook, NULL); diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index c3adf40..15dd8b5 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -181,7 +181,7 @@ /* It's expected that we write to the NULL page in the first two iterations of the following loop, so temporarily disable the NULL breakpoint. */ - null_breakpoint_disable(); + null_breakpoint_remove(); /* Copy IDT stub code for each interrupt. This might seem wasteful * but it is really simple diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 39d7ce9..ce0d283 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -412,8 +412,8 @@ fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); /* FSP disables the interrupt handler so remove debug exceptions temporarily */ - null_breakpoint_disable(); - stack_canary_breakpoint_disable(); + null_breakpoint_remove(); + stack_canary_breakpoint_remove(); post_code(POSTCODE_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 3ec78d5..358589d 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -78,8 +78,8 @@ post_code(data->post_code_before); /* FSP disables the interrupt handler so remove debug exceptions temporarily */ - null_breakpoint_disable(); - stack_canary_breakpoint_disable(); + null_breakpoint_remove(); + stack_canary_breakpoint_remove(); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params); else diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 1e1ff99..1caf00f 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -132,8 +132,8 @@ post_code(POSTCODE_FSP_SILICON_INIT); /* FSP disables the interrupt handler so remove debug exceptions temporarily */ - null_breakpoint_disable(); - stack_canary_breakpoint_disable(); + null_breakpoint_remove(); + stack_canary_breakpoint_remove(); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); else -- To view, visit https://review.coreboot.org/c/coreboot/+/85540?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id3da25cfa6fc0594887f3112e269e57e8ecb32b3 Gerrit-Change-Number: 85540 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: arch/x86: Add breakpoint to stack canary
by Lean Sheng Tan (Code Review) 10 Dec '24

10 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84833?usp=email ) Change subject: arch/x86: Add breakpoint to stack canary ...................................................................... arch/x86: Add breakpoint to stack canary In order to debug stack smashing add a write breakpoint to the stack canary (at _stack or _car_stack) and print the IP when the stack canary is written. TEST: Wrote to address _stack in ramstage and got the EIP of the code that smashed the stack canary. Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84833 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.mk M src/arch/x86/exception.c A src/arch/x86/include/arch/stack_canary_breakpoint.h A src/arch/x86/stack_canary_breakpoint.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/notify.c M src/drivers/intel/fsp2_0/silicon_init.c M src/include/symbols.h 9 files changed, 113 insertions(+), 0 deletions(-) Approvals: Shuo Liu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e99b3af..2077405 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -368,6 +368,18 @@ default y depends on DEBUG_NULL_DEREF_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES +config DEBUG_STACK_OVERFLOW_BREAKPOINTS + bool + default y + depends on DEBUG_HW_BREAKPOINTS + help + Enable support for catching stack overflows + +config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES + bool + default y + depends on DEBUG_STACK_OVERFLOW_BREAKPOINTS && DEBUG_HW_BREAKPOINTS_IN_ALL_STAGES + # Some EC need an "EC firmware pointer" (a data structure hinting the address # of its firmware blobs) being put at a fixed position. Its space # (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a diff --git a/src/arch/x86/Makefile.mk b/src/arch/x86/Makefile.mk index 43c7bd4..a455a09 100644 --- a/src/arch/x86/Makefile.mk +++ b/src/arch/x86/Makefile.mk @@ -69,6 +69,7 @@ bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c bootblock-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c +bootblock-$(CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES) += stack_canary_breakpoint.c bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c bootblock-y += gdt_init.S bootblock-y += id.S @@ -116,6 +117,7 @@ verstage-$(CONFIG_ARCH_VERSTAGE_X86_64) += memmove_64.S verstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c verstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c +verstage-$(CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES) += stack_canary_breakpoint.c # If verstage is a separate stage it means there's no need # for a chipset-specific car_stage_entry() so use the generic one # which just calls verstage(). @@ -152,6 +154,7 @@ romstage-y += memset.c romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c romstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c +romstage-$(CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES) += stack_canary_breakpoint.c romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c @@ -194,6 +197,7 @@ postcar-y += memset.c postcar-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c postcar-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS_IN_ALL_STAGES) += null_breakpoint.c +postcar-$(CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES) += stack_canary_breakpoint.c postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c postcar-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c @@ -238,6 +242,7 @@ ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS) += null_breakpoint.c +ramstage-$(CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS) += stack_canary_breakpoint.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-y += rdrand.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index aecce7b..224f0e1 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -2,6 +2,7 @@ #include <arch/cpu.h> #include <arch/breakpoint.h> #include <arch/null_breakpoint.h> +#include <arch/stack_canary_breakpoint.h> #include <arch/exception.h> #include <arch/registers.h> #include <commonlib/helpers.h> @@ -665,4 +666,5 @@ load_idt(idt, sizeof(idt)); null_breakpoint_init(); + stack_canary_breakpoint_init(); } diff --git a/src/arch/x86/include/arch/stack_canary_breakpoint.h b/src/arch/x86/include/arch/stack_canary_breakpoint.h new file mode 100644 index 0000000..98c7922 --- /dev/null +++ b/src/arch/x86/include/arch/stack_canary_breakpoint.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _STACK_CANARY_BREAKPOINT_H_ +#define _STACK_CANARY_BREAKPOINT_H_ + +#if CONFIG(DEBUG_STACK_OVERFLOW_BREAKPOINTS) && \ + (CONFIG(DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES) || ENV_RAMSTAGE) + +/* Places a data breakpoint at stack canary. */ +void stack_canary_breakpoint_init(void); +void stack_canary_breakpoint_disable(void); +#else +static inline void stack_canary_breakpoint_init(void) +{ + /* Not implemented */ +} +static inline void stack_canary_breakpoint_disable(void) +{ + /* Not implemented */ +} +#endif +#endif /* _STACK_CANARY_BREAKPOINT_H_ */ diff --git a/src/arch/x86/stack_canary_breakpoint.c b/src/arch/x86/stack_canary_breakpoint.c new file mode 100644 index 0000000..6db8d63 --- /dev/null +++ b/src/arch/x86/stack_canary_breakpoint.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/breakpoint.h> +#include <arch/stack_canary_breakpoint.h> +#include <arch/symbols.h> +#include <bootstate.h> +#include <console/console.h> +#include <types.h> +#include <symbols.h> + +static struct breakpoint_handle stack_canary_bp; + +static int handle_stack_canary_written(struct breakpoint_handle handle, struct eregs *regs) +{ +#if ENV_X86_64 + printk(BIOS_ERR, "Stack corruption detected at rip: 0x%llx\n", regs->rip); +#else + printk(BIOS_ERR, "Stack corruption detected at eip: 0x%x\n", regs->eip); +#endif + return 0; +} + +static void create_stack_canary_breakpoint(uintptr_t *addr) +{ + enum breakpoint_result res = + breakpoint_create_data(&stack_canary_bp, addr, sizeof(uintptr_t), true); + + if (res != BREAKPOINT_RES_OK) { + printk(BIOS_ERR, "Failed to create stack canary breakpoint\n"); + return; + } + + breakpoint_set_handler(stack_canary_bp, &handle_stack_canary_written); + breakpoint_enable(stack_canary_bp, true); +} + +void stack_canary_breakpoint_init(void) +{ + uintptr_t *addr; + + if (CONFIG(RESET_VECTOR_IN_RAM)) { + addr = (uintptr_t *)_earlyram_stack; + } else if (ENV_CACHE_AS_RAM) { + addr = (uintptr_t *)_car_stack; + } else { + addr = (uintptr_t *)_stack; + } + + create_stack_canary_breakpoint(addr); +} + +void stack_canary_breakpoint_disable(void) +{ + breakpoint_remove(stack_canary_bp); +} + +static void stack_canary_breakpoint_disable_hook(void *unused) +{ + stack_canary_breakpoint_disable(); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, stack_canary_breakpoint_disable_hook, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, stack_canary_breakpoint_disable_hook, NULL); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7e9676c..39d7ce9 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/null_breakpoint.h> +#include <arch/stack_canary_breakpoint.h> #include <arch/symbols.h> #include <assert.h> #include <cbfs.h> @@ -412,6 +413,7 @@ /* FSP disables the interrupt handler so remove debug exceptions temporarily */ null_breakpoint_disable(); + stack_canary_breakpoint_disable(); post_code(POSTCODE_FSP_MEMORY_INIT); timestamp_add_now(TS_FSP_MEMORY_INIT_START); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) @@ -421,6 +423,7 @@ else status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); null_breakpoint_init(); + stack_canary_breakpoint_init(); post_code(POSTCODE_FSP_MEMORY_EXIT); timestamp_add_now(TS_FSP_MEMORY_INIT_END); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 22bbf53..3ec78d5 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/null_breakpoint.h> +#include <arch/stack_canary_breakpoint.h> #include <bootstate.h> #include <console/console.h> #include <cpu/x86/mtrr.h> @@ -78,11 +79,13 @@ /* FSP disables the interrupt handler so remove debug exceptions temporarily */ null_breakpoint_disable(); + stack_canary_breakpoint_disable(); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params); else ret = fspnotify(&notify_params); null_breakpoint_init(); + stack_canary_breakpoint_init(); timestamp_add_now(data->timestamp_after); post_code(data->post_code_after); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index cea894c..1e1ff99 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/null_breakpoint.h> +#include <arch/stack_canary_breakpoint.h> #include <bootsplash.h> #include <bootstate.h> #include <cbfs.h> @@ -132,11 +133,13 @@ /* FSP disables the interrupt handler so remove debug exceptions temporarily */ null_breakpoint_disable(); + stack_canary_breakpoint_disable(); if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd); else status = silicon_init(upd); null_breakpoint_init(); + stack_canary_breakpoint_init(); fsp_printk(status, BIOS_INFO, "FSPS"); diff --git a/src/include/symbols.h b/src/include/symbols.h index ef23814..36e4c10 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -82,6 +82,7 @@ DECLARE_OPTIONAL_REGION(bl31) DECLARE_REGION(transfer_buffer) DECLARE_OPTIONAL_REGION(watchdog_tombstone) +DECLARE_OPTIONAL_REGION(earlyram_stack) /* Returns true when pre-RAM symbols are known to the linker. * (Does not necessarily mean that the memory is accessible.) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Gerrit-Change-Number: 84833 Gerrit-PatchSet: 20 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu, yuchi.chen(a)intel.com. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85170/comment/67fea6bd_187951ce?us… : PS11, Line 9: FSP only configures the PCH IOAPIC. Let coreboot reconfigure : all IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, : and the IOAPICs on Socket1 start at GSI 72, thus calculate the exact : GSI address for each IOAPIC instead of assume it's a linear address : space. If you re-flowed for 72 characters per line, maybe you could save the last one. -- To view, visit https://review.coreboot.org/c/coreboot/+/85170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f Gerrit-Change-Number: 85170 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 08:47:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85128?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... Patch Set 23: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85128/comment/82b64782_c732f55a?us… : PS23, Line 9: Add MT6363 AUXADC driver support. It’d be great if you elaborated a little. File src/soc/mediatek/common/mt6363_sdmadc.c: https://review.coreboot.org/c/coreboot/+/85128/comment/275f430b_302d7e18?us… : PS23, Line 23: AUXADC_AVG_TIME Please append the unit to the name. https://review.coreboot.org/c/coreboot/+/85128/comment/64adfd39_552738d9?us… : PS23, Line 24: AUXADC_POLL_TIME Ditto. https://review.coreboot.org/c/coreboot/+/85128/comment/4444c0e4_9d64d496?us… : PS23, Line 64: int unsigned int -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 23 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 08:45:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/85363?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85363/comment/fc1639f3_47fb6709?us… : PS4, Line 10: touchscreen specification > Done I do not see it. https://review.coreboot.org/c/coreboot/+/85363/comment/928d97a1_ce7ec847?us… : PS4, Line 11: which delay calibration timing > Done Sorry, I still do not understand item 1. What are you requesting from the vendor exactly? https://review.coreboot.org/c/coreboot/+/85363/comment/abcad2a3_8aa9d9a4?us… : PS4, Line 12: Change My suggestion is: > 2. Double delay RST time to 12 ms https://review.coreboot.org/c/coreboot/+/85363/comment/70efa2fe_d499dd53?us… : PS4, Line 14: > Each firmware of panel might be specific requirement for the project. […] Please add it to the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/85363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Gerrit-Change-Number: 85363 Gerrit-PatchSet: 5 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 08:43:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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