coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Ren Kuo. Paul Menzel has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85533/comment/d9e94ad9_63066d35?us… : PS6, Line 9: Currently, with default speed auto the Wifi 7 M.2 module will not work under speed Gen3. This is due to driver iwlwifi for wifi7 is not stable and decreasing the speed to Gen2 gets the card working without any downsides, as the Wifi 7 speed can be serviced by 5 GT/s. Please reflow for 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 11:22:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85128?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... Patch Set 27: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85128/comment/94129c51_e7d98403?us… : PS23, Line 9: Add MT6363 AUXADC driver support. > Done I think there are some terms for different kinds of drivers/interactions, like mailbox or so. If available it’d be great if you could add such a term for the driver you implemented. -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 11:19:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... Patch Set 21: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85126/comment/40cbbaa7_d927a922?us… : PS17, Line 13: TEST=build pass > Done Thank you! -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 21 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 11:16:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... soc/mediatek/mt8196: Add booker driver The MediaTek booker (the customized ARM CI-700) is a high-performance interconnect architecture designed for multi-core processor systems, providing high bandwidth, low latency data transfer. And booker mainly uses CHI protocol, but doesn't support coherence (which is achieved through ACP solution). Additionally, the booker also uses other protocols such as AXI, which translates CHI transactions into EMI's AXI transactions. Currently, the mt8196 booker only uses the functions of SLC CMO routing. If downstream SLC needs CMO command propagation from the DSU, it is needed to clear bit 3 (disable_cmo_prop) in por_sbsx_cfg_ctl register of each SBSX node in order to propagate the CMO command. Increase the bootblock size from 75K to 78K to support booker. TEST=build pass, check boot log with: [booker_init] AP hash rule: 0xbe00. BUG=b:317009620 Signed-off-by: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85362 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/booker.c M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/booker.h M src/soc/mediatek/mt8196/include/soc/memlayout.ld 5 files changed, 50 insertions(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 3f76811..b3a0834 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -10,6 +10,7 @@ all-y += timer.c timer_prepare.c all-y += ../common/uart.c +bootblock-y += booker.c bootblock-y += bootblock.c bootblock-y += ../common/bootblock.c bootblock.c bootblock-y += ../common/early_init.c diff --git a/src/soc/mediatek/mt8196/booker.c b/src/soc/mediatek/mt8196/booker.c new file mode 100644 index 0000000..020af9a --- /dev/null +++ b/src/soc/mediatek/mt8196/booker.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/booker.h> + +#define REG_READ_ONLY_HASH_VALUE (MCUCFG_BASE + 0x059C) +#define REG_MCUSYS_RESERVED_REG2 (MCUCFG_BASE + 0xFFE8) + +#define POR_SBSX_CFG_CTL_OFFSET (0x00450000 + 0x0A00) +#define INSTANCE0_SBSX_POR_SBSX_CFG_CTL (0x0A000000 + POR_SBSX_CFG_CTL_OFFSET) +#define INSTANCE1_SBSX_POR_SBSX_CFG_CTL (0x0A800000 + POR_SBSX_CFG_CTL_OFFSET) +#define INSTANCE2_SBSX_POR_SBSX_CFG_CTL (0x0B000000 + POR_SBSX_CFG_CTL_OFFSET) +#define INSTANCE3_SBSX_POR_SBSX_CFG_CTL (0x0B800000 + POR_SBSX_CFG_CTL_OFFSET) +#define BIT_DISABLE_CMO_PROP BIT(3) + +/* + * Configure booker and disable HN-D coherence request to avoid + * receiving NDE(Non-data Error) before MMU enabled. + */ +void booker_init(void) +{ + /* Enable CMO(cache maintenance operations) propagation */ + clrbits64p(INSTANCE0_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP); + clrbits64p(INSTANCE1_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP); + clrbits64p(INSTANCE2_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP); + clrbits64p(INSTANCE3_SBSX_POR_SBSX_CFG_CTL, BIT_DISABLE_CMO_PROP); + dsb(); + isb(); + + /* CHI Splitter - for Q-Channel setting */ + setbits32p(REG_MCUSYS_RESERVED_REG2, BIT(0)); + + printk(BIOS_DEBUG, "[%s] AP hash rule: 0x%x\n", + __func__, + read32p(REG_READ_ONLY_HASH_VALUE)); +} diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 578d353..365a4e0 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/booker.h> #include <bootblock_common.h> #include <soc/early_init.h> #include <soc/lastbus_v2.h> @@ -9,6 +10,7 @@ void bootblock_soc_init(void) { + booker_init(); mtk_mmu_init(); lastbus_init(); mtk_wdt_init(); diff --git a/src/soc/mediatek/mt8196/include/soc/booker.h b/src/soc/mediatek/mt8196/include/soc/booker.h new file mode 100644 index 0000000..a9f8d63 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/booker.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8196_BOOKER_H +#define SOC_MEDIATEK_MT8196_BOOKER_H + +void booker_init(void); + +#endif diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index f038e23..1529a69 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -46,7 +46,7 @@ DRAM_INIT_CODE(0x02000000, 600K) #else /* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */ - BOOTBLOCK(0x02001000, 75K) + BOOTBLOCK(0x02001000, 78K) #endif OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) PRERAM_CBFS_CACHE(0x020DA000, 48K) -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add booker driver
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Dehui Sun, Hung-Te Lin, Jarried Lin, Paul Menzel. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85362?usp=email ) Change subject: soc/mediatek/mt8196: Add booker driver ...................................................................... Patch Set 14: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85362?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6bde1e20137890addf18b23b47f17b1f63824b22 Gerrit-Change-Number: 85362 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dehui Sun <dehui.sun(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 11:04:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Jayvik Desai (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email ) Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec_lpc.c: https://review.coreboot.org/c/coreboot/+/85449/comment/4dec47a5_a9384da9?us… : PS2, Line 169: EC_LPC_ADDR_MEMMAP > yes, I am planning to add another patch that updates the EC_LPC_ADDR_MEMMAP. Added the patch in relational chain, updated the macro name as well to accommodate the changes. -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 10:40:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jayvik Desai <jayvik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO.
by Jayvik Desai (Code Review) 10 Dec '24

10 Dec '24

Jayvik Desai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85547?usp=email ) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO. ...................................................................... mb/google/brya: Adjust EC memory map range to support indexed IO. Adjust the EC memory map range for indexed IO access in trulo variant from 0x900 to 0x380 BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85547/1 diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index 3090bb5..d407f00 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -9,7 +9,7 @@ register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" + register "gen3_dec" = "CONFIG(EC_GOOGLE_CHROMEEC_MEMMAP_INDEXED_IO) ? 0x00fc0381 : 0x00fc0901" register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Morgan Jang, Patrick Rudolph, yuchi.chen(a)intel.com. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email ) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... Patch Set 5: Code-Review+1 (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85492/comment/7f4a04cf_dd787aee?us… : PS5, Line 15: Fixes lot's of error messages about not working IPMI. Paste one of these error messages? https://review.coreboot.org/c/coreboot/+/85492/comment/ccb82ee9_cb901171?us… : PS5, Line 17: Once GPP_F4 is low IPMI communication over the KCS is also : working on ocp/tiogapass. : Paste the new log message with the elapsed time? File src/mainboard/ocp/tiogapass/romstage.c: https://review.coreboot.org/c/coreboot/+/85492/comment/8f76dfbb_0cba9ab0?us… : PS5, Line 61: timeout Add the unit to the name? https://review.coreboot.org/c/coreboot/+/85492/comment/14ce0554_7c94344d?us… : PS5, Line 70: %ldms Add a space before the unit? -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 10:34:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
by Paul Menzel (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Gwendal Grignou, Rob Barnes. Paul Menzel has posted comments on this change by Rob Barnes. ( https://review.coreboot.org/c/coreboot/+/85461?usp=email ) Change subject: ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85461?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia476263620acc269f9dd8a6b3c9e5e247b403aee Gerrit-Change-Number: 85461 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Tue, 10 Dec 2024 10:30:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Jayvik Desai (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik. Hello Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85449?usp=email to look at the new patch set (#4). Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... ec/google/chromeec: Add indexed IO support Add support for indexed IO for ec communication, Indexed I/O allows memory access using a single I/O port base address usually called an index register and another port address called a data register. BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/ec_commands.h M src/ec/google/chromeec/ec_lpc.c 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85449/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com>

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coreboot-gerrit December 2024