coreboot-gerrit December 2024

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[S] Change in coreboot[main]: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
by Felix Held (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Ana Carolina Cabral. Felix Held has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Tue, 10 Dec 2024 16:04:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
by Ana Carolina Cabral (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Felix Held. Hello Felix Held, Fred Reitberger, Jason Glenesk, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85498?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] ...................................................................... mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] Fix VDD_MEM_VID[0,1] pin assignments that was causing boot issues. Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> --- M src/mainboard/amd/birman/gpio.c M src/mainboard/amd/birman_plus/gpio.c 2 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/85498/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: intelp2m/patform/ebg: Add unit tests
by Maxim (Code Review) 10 Dec '24

10 Dec '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85552?usp=email ) Change subject: intelp2m/patform/ebg: Add unit tests ...................................................................... intelp2m/patform/ebg: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I10c313aa543a4e07c6685a7ae4e9d665eef7bf75 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/platforms/ebg/ebg_test.go 1 file changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/85552/1 diff --git a/util/intelp2m/platforms/ebg/ebg_test.go b/util/intelp2m/platforms/ebg/ebg_test.go new file mode 100644 index 0000000..f80d0a6 --- /dev/null +++ b/util/intelp2m/platforms/ebg/ebg_test.go @@ -0,0 +1,110 @@ +package ebg_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/ebg" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + emmitsburg := ebg.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_A2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", emmitsburg) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-EMMITSBURG-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", emmitsburg) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-EMMITSBURG-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", emmitsburg) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10c313aa543a4e07c6685a7ae4e9d665eef7bf75 Gerrit-Change-Number: 85552 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

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[M] Change in coreboot[main]: intelp2m/patform/mtl: Add unit tests
by Maxim (Code Review) 10 Dec '24

10 Dec '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85551?usp=email ) Change subject: intelp2m/patform/mtl: Add unit tests ...................................................................... intelp2m/patform/mtl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I5965f2362626c0ca1f51bf5f4dbe275b76c392ea Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/platforms/mtl/mtl_test.go 1 file changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/85551/1 diff --git a/util/intelp2m/platforms/mtl/mtl_test.go b/util/intelp2m/platforms/mtl/mtl_test.go new file mode 100644 index 0000000..ca5cb0a --- /dev/null +++ b/util/intelp2m/platforms/mtl/mtl_test.go @@ -0,0 +1,110 @@ +package mtl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/mtl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + meteorlake := mtl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_A2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", meteorlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A5, UP_2K, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A6, INVALID, PWROK, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF7) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", meteorlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A11, INVALID, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF3) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-METEOR-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", meteorlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85551?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5965f2362626c0ca1f51bf5f4dbe275b76c392ea Gerrit-Change-Number: 85551 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

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[M] Change in coreboot[main]: intelp2m/patform/adl: Add unit tests
by Maxim (Code Review) 10 Dec '24

10 Dec '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85550?usp=email ) Change subject: intelp2m/patform/adl: Add unit tests ...................................................................... intelp2m/patform/adl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: I1ef3e9eeccdde8824a921ece02edbc4ba1187a00 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/platforms/adl/adl_test.go 1 file changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/85550/1 diff --git a/util/intelp2m/platforms/adl/adl_test.go b/util/intelp2m/platforms/adl/adl_test.go new file mode 100644 index 0000000..0b24aa3 --- /dev/null +++ b/util/intelp2m/platforms/adl/adl_test.go @@ -0,0 +1,110 @@ +package adl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/adl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + alderlake := adl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_A2, 0, INVALID, RSMRST),", + Long: "_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", alderlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A5, UP_2K, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A6, INVALID, PWROK, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF7) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", alderlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A9, UP_20K, RSMRST, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF4) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A11, INVALID, PWROK, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF3) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-ALDER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", alderlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ef3e9eeccdde8824a921ece02edbc4ba1187a00 Gerrit-Change-Number: 85550 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

1 0

[M] Change in coreboot[main]: intelp2m/patform/jsl: Add unit tests
by Maxim (Code Review) 10 Dec '24

10 Dec '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85549?usp=email ) Change subject: intelp2m/patform/jsl: Add unit tests ...................................................................... intelp2m/patform/jsl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: Ie2acd675a6239768d23593cd5ca273b56480a890 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/platforms/jsl/jsl_test.go 1 file changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/85549/1 diff --git a/util/intelp2m/platforms/jsl/jsl_test.go b/util/intelp2m/platforms/jsl/jsl_test.go new file mode 100644 index 0000000..2bbbfd4 --- /dev/null +++ b/util/intelp2m/platforms/jsl/jsl_test.go @@ -0,0 +1,110 @@ +package jsl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/jsl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + jasperlake := jsl.PlatformSpecific{ + InheritanceMacro: cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + }, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_A2, 0, INVALID, PWROK),", + Long: "_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", jasperlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", jasperlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A9, UP_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-JASPER-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", jasperlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85549?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2acd675a6239768d23593cd5ca273b56480a890 Gerrit-Change-Number: 85549 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

1 0

[M] Change in coreboot[main]: intelp2m/patform/cnl: Add unit tests
by Maxim (Code Review) 10 Dec '24

10 Dec '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85548?usp=email ) Change subject: intelp2m/patform/cnl: Add unit tests ...................................................................... intelp2m/patform/cnl: Add unit tests 1) Siding one in nibble: DW = 0001 0001 0001 0001 <- <- <- <- 2) Siding zero in nibble: DW = 1110 1110 1110 1110 <- <- <- <- 3) Siding one one in nibble: DW = 0011 0011 0011 0011 <- <- <- <- Change-Id: Icb0b6506a07b96903e6bc7994e5f97d483d0a330 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/platforms/cnl/cnl_test.go 1 file changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/85548/1 diff --git a/util/intelp2m/platforms/cnl/cnl_test.go b/util/intelp2m/platforms/cnl/cnl_test.go new file mode 100644 index 0000000..4ab9346 --- /dev/null +++ b/util/intelp2m/platforms/cnl/cnl_test.go @@ -0,0 +1,107 @@ +package cnl_test + +import ( + "testing" + + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/cnl" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/snr" + "review.coreboot.org/coreboot.git/util/intelp2m/platforms/test" +) + +func TestGenMacro(t *testing.T) { + cannonlake := cnl.PlatformSpecific{ + InheritanceMacro: snr.PlatformSpecific{}, + } + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A1", DW0: 0x11111111, DW1: 0x11111111, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A1, DN_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF4) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(DN_20K) | PAD_IOSSTATE(Tx1RxDCRx1) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A2", DW0: 0x22222222, DW1: 0x22222222, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_TERM_GPO(GPP_A2, 0, INVALID, PWROK),", + Long: "_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(GPIO) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx1) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A3", DW0: 0x44444444, DW1: 0x44444444, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A3, INVALID, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SMI), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx0RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A4", DW0: 0x88888888, DW1: 0x88888888, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A4, DN_5K, PLTRST, NF2),", + Long: "_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT), PAD_PULL(DN_5K) | PAD_IOSSTATE(Tx0RxDCRx1)),", + }, + }, + }.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-IN-NIBBLE-TEST", cannonlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A5", DW0: 0xEEEEEEEE, DW1: 0xEEEEEEEE, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A5, UP_2K, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_2K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPD) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A6", DW0: 0xDDDDDDDD, DW1: 0xDDDDDDDD, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A6, INVALID, RSMRST, NF7),", + Long: "_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF7) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(HIZCRx0) | PAD_IOSTERM(DISPUPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A7", DW0: 0xBBBBBBBB, DW1: 0xBBBBBBBB, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A7, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(NMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(INVALID) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A8", DW0: 0x77777777, DW1: 0x77777777, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A8, UP_667, DEEP, NF5),", + Long: "_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF5) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_667) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU)),", + }, + }, + }.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ZERO-IN-NIBBLE-TEST", cannonlake) + + test.Suite{ + { + Pad: test.Pad{ID: "GPP_A9", DW0: 0x33333333, DW1: 0x33333333, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A9, UP_20K, PWROK, NF4),", + Long: "_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF4) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(TX_RX_DISABLE) | (1 << 29) | (1 << 28) | (1 << 1) | 1, PAD_CFG1_TOL_1V8PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE) | PAD_IOSTERM(ENPU) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A10", DW0: 0x66666666, DW1: 0x66666666, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF_1V8(GPP_A10, UP_1K, DEEP, NF1),", + Long: "_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_BOTH) | PAD_IRQ_ROUTE(SMI) | PAD_IRQ_ROUTE(NMI) | PAD_BUF(RX_DISABLE) | (1 << 29) | (1 << 1), PAD_CFG1_TOL_1V8PAD_PULL(UP_1K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(ENPD)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A11", DW0: 0xCCCCCCCC, DW1: 0xCCCCCCCC, Ownership: 1}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A11, INVALID, RSMRST, NF3),", + Long: "_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(NF3) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_IRQ_ROUTE(SCI) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT), PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxDCRx0) | PAD_CFG_OWN_GPIO(DRIVER)),", + }, + }, + { + Pad: test.Pad{ID: "GPP_A12", DW0: 0x99999999, DW1: 0x99999999, Ownership: 0}, + Macro: test.Macro{ + Short: "PAD_CFG_NF(GPP_A12, INVALID, PLTRST, NF6),", + Long: "_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(NF6) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 28) | 1, PAD_PULL(INVALID) | PAD_IOSSTATE(Tx1RxE) | PAD_IOSTERM(DISPUPD)),", + }, + }, + }.Run(t, "INTEL-CANNON-LAKE-PCH/SLIDING-ONE-ONE-IN-NIBBLE-TEST", cannonlake) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85548?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb0b6506a07b96903e6bc7994e5f97d483d0a330 Gerrit-Change-Number: 85548 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

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[L] Change in coreboot[main]: util/intelp2m/parser: Add unit test
by Maxim (Code Review) 10 Dec '24

10 Dec '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/67701?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/intelp2m/parser: Add unit test ...................................................................... util/intelp2m/parser: Add unit test Also add an interface for printing macros to override this in the test and not create a new gpio file for comparison. Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/parser/parser_test.go A util/intelp2m/parser/test/inteltool_test.log 4 files changed, 292 insertions(+), 126 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/67701/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/67701?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16c9b4451cd4418b49043a925cb879a982a56461 Gerrit-Change-Number: 67701 Gerrit-PatchSet: 16 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC mt6373 driver
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85129?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC mt6373 driver ...................................................................... Patch Set 29: (2 comments) File src/soc/mediatek/common/mt6373.c: https://review.coreboot.org/c/coreboot/+/85129/comment/0350e18e_f779f2a9?us… : PS19, Line 270: mt6373_enable_vcn33_3(true); : mt6373_set_vcn33_3_voltage(3300000); > It is for display. Put them in the condition of `if (display_init_required())` in mainboard.c. Please also make sure that the kernel does not rely on this power-on sequence in the FW. File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85129/comment/8382a03a_fdd71207?us… : PS29, Line 34: romstage-y += ../common/mt6373.c mt6373.c Please explain why it is needed in romstage and ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 29 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 14:52:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yidi Lin (Code Review) 10 Dec '24

10 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/mt8196/sspm.c: PS11: rename to sspm_sram.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Dec 2024 14:45:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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