Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80304?usp=email )
Change subject: commonlib: Add generic word-at-a-time optimization to ipchksum()
......................................................................
commonlib: Add generic word-at-a-time optimization to ipchksum()
This patch adds a generic optimization to calculate a machine-word-sized
"wide sum" for the ipchksum() algorithm. This is often not as
efficient as handcrafted assembly (about half as fast on arm64 and
x86_32, about the same speed on x86_64), but likely still much better
than nothing on architectures that we don't have handcrafted assembly
for.
Change-Id: I8f0fe117e2788d1b6801b73824b97e1e31ecc694
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80304
Reviewed-by: Yu-Ping Wu <yupingso(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/commonlib/bsd/ipchksum.c
1 file changed, 14 insertions(+), 2 deletions(-)
Approvals:
Yu-Ping Wu: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/commonlib/bsd/ipchksum.c b/src/commonlib/bsd/ipchksum.c
index b7434e5..10f343f 100644
--- a/src/commonlib/bsd/ipchksum.c
+++ b/src/commonlib/bsd/ipchksum.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
+#include <commonlib/bsd/helpers.h>
#include <commonlib/bsd/ipchksum.h>
/* See RFC 1071 for mathematical explanations of why we can first sum in a larger register and
@@ -34,7 +35,7 @@
:: "cc"
);
}
-#elif defined(__i386__) || defined(__x86_64__)
+#elif defined(__i386__) || defined(__x86_64__) /* __aarch64__ */
size_t size8 = size / 8;
const uint64_t *p8 = data;
i = size8 * 8;
@@ -57,7 +58,18 @@
[size8] "+c" (size8) /* put size in ECX so we can JECXZ */
:: "cc"
);
-#endif /* __i386__ || __x86_64__ */
+#else /* __i386__ || __x86_64__ */
+ size_t aligned_size = ALIGN_DOWN(size, sizeof(unsigned long));
+ const unsigned long *p_long = data;
+ for (; i < aligned_size; i += sizeof(unsigned long)) {
+ unsigned long new_sum = wide_sum + *p_long++;
+ /* Overflow check to emulate a manual "add with carry" in C. The compiler seems
+ to be clever enough to find ways to elide the branch on most archs. */
+ if (new_sum < wide_sum)
+ new_sum++;
+ wide_sum = new_sum;
+ }
+#endif
while (wide_sum) {
sum += wide_sum & 0xFFFF;
--
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Change subject: soc/mediatek/mt8196: Add mtcmos init support
......................................................................
Patch Set 40: Code-Review+2
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Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS17:
@subratabanik@google.com, I re-tested this patch today and I realized the current implementation may be a bit problematic as all the board without a battery attached will lower PL4. Would it make sense to have a FW_CONFIG flag to not apply this policy ?
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Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin
......................................................................
Patch Set 6: Code-Review+2
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Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:
https://review.coreboot.org/c/coreboot/+/85464/comment/afbf5494_5500d311?us… :
PS5, Line 461: PAD_NC(GPP_E05, NONE),
> /* GPP_F23: Not used */ […]
Done
File src/mainboard/google/fatcat/variants/fatcat/gpio.c:
https://review.coreboot.org/c/coreboot/+/85464/comment/9f1cf537_b527e683?us… :
PS5, Line 302: /* GPP_F23: Not used */
: PAD_NC(GPP_F23, NONE),
> please drop
Done
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Hello Jérémy Compostella, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85464?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin
......................................................................
mb/google/fatcat: config GPP_F23 as ISH gpio pin
The GPP_F23/ISH_GP_9A pin receives the lid open/close signal from
SMC_LID. This pin is not utilized in the AP firmware stack; however
the ISH firmware requires this signal for its tablet mode support.
Therefore, we configure this pin as an ISH GPIO.
BUG=b:370984186
TEST=Build and flash CB; run ISH main firmware; read this pin and
verified it returned the correct value.
fatcat-rev257 ~ # ectool --name=cros_ish gpioget lid_open
GPIO lid_open = 1
Change-Id: I19a4d6967acf96aefe2f38d628f898811d8a6e6d
Signed-off-by: Li Feng <li1.feng(a)intel.com>
---
M src/mainboard/google/fatcat/variants/fatcat/fw_config.c
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/85464/6
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Change subject: commonlib: Add generic word-at-a-time optimization to ipchksum()
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/fatcat: config GPP_F23 as ISH gpio pin
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:
https://review.coreboot.org/c/coreboot/+/85464/comment/0df95e87_6a382f04?us… :
PS5, Line 461: PAD_NC(GPP_E05, NONE),
/* GPP_F23: Not used */
PAD_NC(GPP_F23, NONE),
File src/mainboard/google/fatcat/variants/fatcat/gpio.c:
https://review.coreboot.org/c/coreboot/+/85464/comment/9bbc4b82_62408e5c?us… :
PS5, Line 302: /* GPP_F23: Not used */
: PAD_NC(GPP_F23, NONE),
please drop
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Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................
Patch Set 17: Code-Review+2
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