coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85511?usp=email ) Change subject: mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config ...................................................................... mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config BUG=b:377377766 TEST=emerge-rex coreboot pass Change-Id: I2020c431444f21d82f8722d24065558a62e0cb93 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85511 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/variants/kanix/overridetree.cb 1 file changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index d23589b..244f974 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -533,6 +533,7 @@ end end #I2C5 device ref pcie_rp5 on + probe WIFI_TYPE WIFI_PCIE # Enable WLAN Card PCIE 5 using clk 5 register "pcie_rp[PCH_RP(5)]" = "{ .clk_src = 5, @@ -543,13 +544,17 @@ register "wake" = "GPE0_DW2_09" register "add_acpi_dma_property" = "true" use usb2_port10 as bluetooth_companion - device pci 00.0 on end + device pci 00.0 on + probe WIFI_TYPE WIFI_PCIE + end end chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E22)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F08)" register "srcclk_pin" = "5" - device generic 0 on end + device generic 0 on + probe WIFI_TYPE WIFI_PCIE + end end end #PCIE5 WLAN card device ref pcie_rp6 on -- To view, visit https://review.coreboot.org/c/coreboot/+/85511?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2020c431444f21d82f8722d24065558a62e0cb93 Gerrit-Change-Number: 85511 Gerrit-PatchSet: 2 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: intel/common/block: Program the right power_limits_config entry
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85244?usp=email ) Change subject: intel/common/block: Program the right power_limits_config entry ...................................................................... intel/common/block: Program the right power_limits_config entry When variant_update_cpu_power_limits() programs PL4, it systematically sets the first entry of the power_limits_config SoC chip data structure. This approach is problematic because the current SoC SKU may align with a different data structure entry, introducing inconsistencies. This commit introduces the power_limits_index field to the cpu_tdp_power_limits data structure. This field specifies the specific power limits entry that should be updated. All data structures utilized by this function are updated accordingly. BUG=b:380408956 TEST=Able to retrieve collect 28W power_limit. Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85244 Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c M src/mainboard/google/rex/variants/baseboard/rex/ramstage.c M src/mainboard/google/rex/variants/deku/ramstage.c M src/mainboard/google/rex/variants/screebo/variant.c M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 7 files changed, 15 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Bora Guvendik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c index e23fc9a..b1b3b9c 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c @@ -41,6 +41,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_1, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, @@ -50,6 +51,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_3, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, diff --git a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c index 14fbad2..2b920ad 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/rex/ramstage.c @@ -15,6 +15,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, @@ -24,6 +25,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_5, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, @@ -36,6 +38,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, @@ -45,6 +48,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_5, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c index 0cfcae1..871313c 100644 --- a/src/mainboard/google/rex/variants/deku/ramstage.c +++ b/src/mainboard/google/rex/variants/deku/ramstage.c @@ -14,6 +14,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_1, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, @@ -23,6 +24,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_3, .cpu_tdp = 28, + .power_limits_index = MTL_P_682_482_CORE, .pl1_min_power = 19000, .pl1_max_power = 28000, .pl2_min_power = 64000, diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c index edddd43..00ee19f5 100644 --- a/src/mainboard/google/rex/variants/screebo/variant.c +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -35,6 +35,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 40000, @@ -44,6 +45,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_5, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 40000, diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c index aee3d88..16f85ba 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <chip.h> #include <device/pci_ids.h> #include <intelblocks/power_limit.h> @@ -13,6 +14,7 @@ { .mch_id = PCI_DID_INTEL_MTL_P_ID_2, .cpu_tdp = 15, + .power_limits_index = MTL_P_282_242_CORE, .pl1_min_power = 10000, .pl1_max_power = 15000, .pl2_min_power = 57000, diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 290a3a3..d02eaa1 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -45,6 +45,7 @@ struct cpu_tdp_power_limits { uint16_t mch_id; uint8_t cpu_tdp; + uint32_t power_limits_index; unsigned int pl1_min_power; unsigned int pl1_max_power; unsigned int pl2_min_power; diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index 40a0857..b5fbe89 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -268,7 +268,8 @@ } else { struct dptf_power_limits *settings = &config->controls.power_limits; config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; + struct soc_power_limits_config *soc_config = + &conf->power_limits_config[limits[index].power_limits_index]; settings->pl1.min_power = limits[index].pl1_min_power; settings->pl1.max_power = limits[index].pl1_max_power; settings->pl2.min_power = limits[index].pl2_min_power; -- To view, visit https://review.coreboot.org/c/coreboot/+/85244?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32de8a24a2b5aee3eb5a6eee2d1d91e203085e65 Gerrit-Change-Number: 85244 Gerrit-PatchSet: 14 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Jamie Ryu, Jérémy Compostella, Paul Menzel. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: > As an alternative, could we filter out on the type of power supply ? > Only if this is a Type-C charger and the battery is missing we would lower PL4. It is my understanding that we use barrel jack power supply at the moment. I am just brainstorming here. valid point, but we might need to stop using barrels and use TCSS#2 as a power source that way we could enable low power mode and other USB-C functionality like PD and USB-C. if we keep on using barrels then we will miss out on creating a CrOS device configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 04:32:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Jérémy Compostella (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Jamie Ryu, Paul Menzel, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: > > @subratabanik@google. […] As an alternative, could we filter out on the type of power supply ? Only if this is a Type-C charger and the battery is missing we would lower PL4. It is my understanding that we use barrel jack power supply at the moment. I am just brainstorming here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 04:17:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
by 9elements QA (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Ren Kuo. 9elements QA has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85533?usp=email ) Change subject: mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2 ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/226769 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/226767 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/226766 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/226765 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/226764 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/226763 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/226762 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/226761 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/226760 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/226759 FAIL: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/226758 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/226757 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/85533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e8a02061251f73ee5ec2299e62fa423ff4b0965 Gerrit-Change-Number: 85533 Gerrit-PatchSet: 6 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 03:07:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC mt6373 driver
by Yidi Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85129?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC mt6373 driver ...................................................................... Patch Set 30: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85129/comment/b38414cf_b2617d39?us… : PS30, Line 9: mt6373 MT6373 https://review.coreboot.org/c/coreboot/+/85129/comment/917582e5_1a7b6a6e?us… : PS30, Line 9: add Add https://review.coreboot.org/c/coreboot/+/85129/comment/5030db3a_1e1c3575?us… : PS30, Line 10: api API https://review.coreboot.org/c/coreboot/+/85129/comment/9bd4eb54_6cd38ce6?us… : PS30, Line 10: SD power powering on SD card https://review.coreboot.org/c/coreboot/+/85129/comment/54a88173_028e76c2?us… : PS30, Line 11: add implement interface for vcn33_3 Can we just say `Add regulator API for VCN33_3` ? https://review.coreboot.org/c/coreboot/+/85129/comment/e365ddea_2f353544?us… : PS30, Line 12: enable Enable https://review.coreboot.org/c/coreboot/+/85129/comment/afa7e254_f59f4450?us… : PS30, Line 13: 5. add MT6373 LDO enable api Add https://review.coreboot.org/c/coreboot/+/85129/comment/11576a09_0484b7e0?us… : PS30, Line 13: api API -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 30 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 02:47:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Yidi Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85128?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... Patch Set 29: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 29 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 02:44:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Yu-Ping Wu (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85128?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... Patch Set 29: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 29 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 02:29:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yu-Ping Wu (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Xiwen Shao, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 14: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84929/comment/09e15bb6_58fb8ed0?us… : PS12, Line 10: hen bus > move to previous line Done https://review.coreboot.org/c/coreboot/+/84929/comment/2dc31d4b_2f3b6356?us… : PS12, Line 13: build > Build Done https://review.coreboot.org/c/coreboot/+/84929/comment/53ad7057_04aba77f?us… : PS12, Line 13: hw > HW or hwardware Done https://review.coreboot.org/c/coreboot/+/84929/comment/461b1a20_3782e586?us… : PS12, Line 14: causes the platform to restart > triggers a reset to the platform, Done https://review.coreboot.org/c/coreboot/+/84929/comment/4a29fa01_e8fbdc6d?us… : PS12, Line 19: has a bus timeout. > move to previous line. Done File src/soc/mediatek/mt8196/include/soc/tracker.h: https://review.coreboot.org/c/coreboot/+/84929/comment/06da4bf9_88ff0fbb?us… : PS14, Line 19: Remove extra blank line. File src/soc/mediatek/mt8196/tracker.c: https://review.coreboot.org/c/coreboot/+/84929/comment/3337d2ed_86a4aaa8?us… : PS14, Line 27: AW_TRACK_L_OFFSET, AW_TRACK_H_OFFSET Adding a trailing `,` -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 14 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 02:26:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
by Daniel Peng (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Daniel Peng has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/85363?usp=email ) Change subject: mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence ...................................................................... Patch Set 7: Code-Review+1 (3 comments) Patchset: PS7: Update the document and calibration 700ms delay time image on tracker for reference. Thanks. Commit Message: https://review.coreboot.org/c/coreboot/+/85363/comment/2401c609_73aa7fb6?us… : PS4, Line 10: touchscreen specification > Sorry. I don't understand what your mean for not see it. […] I had update to issue tracker for reference. Thanks. https://partnerissuetracker.corp.google.com/issues/375986645#comment14 https://review.coreboot.org/c/coreboot/+/85363/comment/845ff5ee_bf995fb3?us… : PS4, Line 11: which delay calibration timing > Sorry, I still do not understand item 1. […] Sorry, same as item 3. I had remove it and add the ILI2901 specification file name. -- To view, visit https://review.coreboot.org/c/coreboot/+/85363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15e30ee72541b4f12b3ec4ea509cb09dc29659ca Gerrit-Change-Number: 85363 Gerrit-PatchSet: 7 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 02:17:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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