coreboot-gerrit December 2024

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85547?usp=email ) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85547/comment/30e5e164_c912af7f?us… : PS1, Line 6: > > `Subject line should not end with a period.` […] Acknowledged File src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb: https://review.coreboot.org/c/coreboot/+/85547/comment/17a4124c_c54fb59e?us… : PS1, Line 11: # EC memory map range is 0x900-0x9ff > this comment is stale now Updated -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 3 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 06:33:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85547?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... mb/google/brya: Adjust EC memory map range to support indexed IO Adjust the EC memory map range for indexed IO access in trulo variant from 0x900 to 0x380 BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85547/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 3 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6373 driver
by Yu-Ping Wu (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85129?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6373 driver ...................................................................... Patch Set 33: (6 comments) File src/soc/mediatek/common/include/soc/mt6373.h: https://review.coreboot.org/c/coreboot/+/85129/comment/940abef9_c2902b17?us… : PS33, Line 78: #endif /* __SOC_MEDIATEK_MT6373_H__ */ Blank line above. File src/soc/mediatek/common/mt6373.c: https://review.coreboot.org/c/coreboot/+/85129/comment/e7234abd_d6d2b862?us… : PS33, Line 24: u32 u8 https://review.coreboot.org/c/coreboot/+/85129/comment/e6057228_d83cdda0?us… : PS33, Line 46: lock Align https://review.coreboot.org/c/coreboot/+/85129/comment/89047c7d_61f84432?us… : PS33, Line 56: ( These parentheses can be removed. https://review.coreboot.org/c/coreboot/+/85129/comment/74f4e12c_f43d138e?us… : PS33, Line 88: ( Remove. Same for other similar functions. https://review.coreboot.org/c/coreboot/+/85129/comment/d68df2ac_0e5b62fa?us… : PS33, Line 109: Extra blank line. -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 33 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 06:29:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85535?usp=email ) Change subject: mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters ...................................................................... mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters The DPTF parameters were defined by the thermal team. Based on thermal table in b:383032918#comment1 BUG=b:383032918 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85535 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/rull/overridetree.cb 1 file changed, 125 insertions(+), 9 deletions(-) Approvals: Lei Cao: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/rull/overridetree.cb b/src/mainboard/google/brya/variants/rull/overridetree.cb index d51fe0b..92bc5d4 100644 --- a/src/mainboard/google/brya/variants/rull/overridetree.cb +++ b/src/mainboard/google/brya/variants/rull/overridetree.cb @@ -157,23 +157,23 @@ # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), - [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { .min_power = 6000, - .max_power = 15000, + .max_power = 6000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -195,9 +195,125 @@ [3] = { 8, 500 } }" - device generic 0 on end + device generic 0 on + probe THERMAL THERMAL_6W + end + end + + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU_VR"" + register "options.tsr[1].desc" = ""CPU"" + register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(54, 64), + TEMP_PCT(52, 52), + TEMP_PCT(50, 44), + TEMP_PCT(48, 38), + TEMP_PCT(45, 34), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_1, + .thresholds = { + TEMP_PCT(75, 90), + TEMP_PCT(70, 80), + TEMP_PCT(65, 70), + TEMP_PCT(60, 60), + TEMP_PCT(55, 50), + TEMP_PCT(50, 40), + } + }, + [2] = { + .target = DPTF_TEMP_SENSOR_2, + .thresholds = { + TEMP_PCT(90, 90), + TEMP_PCT(85, 80), + TEMP_PCT(75, 70), + TEMP_PCT(70, 50), + } + }, + [3] = { + .target = DPTF_TEMP_SENSOR_3, + .thresholds = { + TEMP_PCT(80, 90), + TEMP_PCT(75, 80), + TEMP_PCT(70, 70), + TEMP_PCT(65, 50), + } + } + }" + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 85, 6000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 6000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 85, 6000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2000 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 4000, 220, 1640, }, + [1] = { 90, 3700, 220, 1640, }, + [2] = { 80, 3500, 180, 1310, }, + [3] = { 70, 3300, 145, 1030, }, + [4] = { 60, 3100, 115, 765, }, + [5] = { 50, 2800, 90, 545, }, + [6] = { 40, 2500, 55, 365, }, + [7] = { 30, 2100, 30, 220, }, + [8] = { 20, 1500, 15, 120, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + device generic 1 on + probe THERMAL THERMAL_15W + end end end + device ref igpu on chip drivers/gfx/generic register "device_count" = "4" -- To view, visit https://review.coreboot.org/c/coreboot/+/85535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I354d50edb014783c7422985c39eb65208ef4fe91 Gerrit-Change-Number: 85535 Gerrit-PatchSet: 4 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lei Cao <caolei6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyle Lin <kylelinck(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add indexed IO support
by Jayvik Desai (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Boris Mittelberg, Caveh Jalali, Kapil Porwal, Subrata Banik. Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/85449?usp=email ) Change subject: ec/google/chromeec: Add indexed IO support ...................................................................... Patch Set 4: (1 comment) File src/ec/google/chromeec/ec_commands.h: https://review.coreboot.org/c/coreboot/+/85449/comment/e5f82041_d8d51424?us… : PS4, Line 152: 0x380 > how generic is this address ? I don't think it's generic, but this is the address used by ENE for indexed access. -- To view, visit https://review.coreboot.org/c/coreboot/+/85449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6c1aab3fc914eb5af2736a8ea3adf447040905e0 Gerrit-Change-Number: 85449 Gerrit-PatchSet: 4 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 06:27:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: mb/google/brya: Adjust EC memory map range to support indexed IO
by Jayvik Desai (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85547?usp=email to look at the new patch set (#2). Change subject: mb/google/brya: Adjust EC memory map range to support indexed IO ...................................................................... mb/google/brya: Adjust EC memory map range to support indexed IO Adjust the EC memory map range for indexed IO access in trulo variant from 0x900 to 0x380 BUG=b:379224648 TEST= able to build nissa/trulo. Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/85547/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85547?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide5026b35da7c00deab4464eedfca9d52d294fd6 Gerrit-Change-Number: 85547 Gerrit-PatchSet: 2 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yu-Ping Wu (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 15: Code-Review+1 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85516/comment/6a9ef472_00f79e10?us… : PS15, Line 11: enable enable it File src/soc/mediatek/common/include/soc/sspm.h: https://review.coreboot.org/c/coreboot/+/85516/comment/2e4ced45_44e488d1?us… : PS15, Line 13: void sspm_enable_sram(void); Can we add a blank line above, and another blank line below `sspm_init`? File src/soc/mediatek/mt8196/sspm_sram.c: https://review.coreboot.org/c/coreboot/+/85516/comment/b1695a86_98c62523?us… : PS15, Line 14: ( remove -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 06:14:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/var/jubilant: Disable Tccold Handshake
by Ren Kuo (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: David Wu, Karthik Ramasubramanian, Subrata Banik. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85555?usp=email ) Change subject: mb/google/brox/var/jubilant: Disable Tccold Handshake ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f22067b81fa1b1b9addd7d1f49de59136d221c0 Gerrit-Change-Number: 85555 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 06:14:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Enable CNVI WLAN based on fw_config
by Tyler Wang (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun. Tyler Wang has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85534?usp=email ) Change subject: mb/google/rex/var/kanix: Enable CNVI WLAN based on fw_config ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/rex/variants/kanix/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85534/comment/2414d27e_526fdc6b?us… : PS1, Line 378: cnvi_wifi > Do you also want to add BT companion device? […] Hi Kapil, If I understand correctly, the purpose of set `bluetooth_companion` is for enable BRDS, right? AFAIK our RF team hasn't request us to enable BRDS for CNVI. If they have this request in the future, I will submit another CL to set `bluetooth_companion`. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/85534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdf01e16267aa64bcf376001e108e2eaa677aaa6 Gerrit-Change-Number: 85534 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 05:49:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yidi Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 15: Code-Review+1 (2 comments) File src/soc/mediatek/common/sspm.c: https://review.coreboot.org/c/coreboot/+/85516/comment/62b4c695_26274b9f?us… : PS15, Line 19: void sspm_init(void) : { : sspm.load_buffer = _dram_dma; : sspm.buffer_size = REGION_SIZE(dram_dma); : : mtk_init_mcu(&sspm); : } ``` __weak void sspm_enable_sram(void) { /* do nothing. */ } void sspm_init(void) { sspm_enable_sram(); sspm.load_buffer = _dram_dma; sspm.buffer_size = REGION_SIZE(dram_dma); mtk_init_mcu(&sspm); } ``` File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/85516/comment/d8a338ae_dcf3c752?us… : PS15, Line 30: sspm_enable_sram(); remove -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 05:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024