coreboot-gerrit December 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 12:16:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Lean Sheng Tan (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85153/comment/bf394bf8_e0c5cc5a?us… : PS11, Line 9: 1. Route IRQ for on-chip end-points only. > Updated the commit message with additional info Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 12:16:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 20: (7 comments) File src/soc/mediatek/mt8196/bootblock.c: https://review.coreboot.org/c/coreboot/+/84929/comment/6c35dcc1_1e4fed4c?us… : PS12, Line 8: tracker_common > tracker. […] Done File src/soc/mediatek/mt8196/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/84929/comment/f4fe0b83_97383de0?us… : PS12, Line 49: 78K) > The change is probably no longer needed. Done File src/soc/mediatek/mt8196/include/soc/tracker.h: https://review.coreboot.org/c/coreboot/+/84929/comment/b372c37d_c1727a67?us… : PS14, Line 19: > Remove extra blank line. Done File src/soc/mediatek/mt8196/include/soc/tracker.h: https://review.coreboot.org/c/coreboot/+/84929/comment/f86bef37_e344bd8f?us… : PS12, Line 5: > #include <soc/tracker_common. […] Done File src/soc/mediatek/mt8196/tracker.c: https://review.coreboot.org/c/coreboot/+/84929/comment/2c6ef72f_e2e6cfc2?us… : PS12, Line 8: #include <soc/tracker_common.h> > remove Done https://review.coreboot.org/c/coreboot/+/84929/comment/0d9f661c_991e21ce?us… : PS12, Line 71: ( > parentheses is not needed. Done File src/soc/mediatek/mt8196/tracker.c: https://review.coreboot.org/c/coreboot/+/84929/comment/e7c9a728_d2fb45eb?us… : PS14, Line 27: AW_TRACK_L_OFFSET, AW_TRACK_H_OFFSET > Adding a trailing `,` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 20 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 11:36:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Xiwen Shao, Yidi Lin. Hello Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#20). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=Build pass, When we encounter a bus hang and HW watchdog triggers a reset to the platform, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 4 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 20 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove hardcoded value for child nodes
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85531?usp=email ) Change subject: soc/intel/pantherlake: Remove hardcoded value for child nodes ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/pantherlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/85531/comment/19f0ec3c_f603ec0e?us… : PS4, Line 319: cpu_cl_disc_tab.header.fields.count = CRASHLOG_NODES_COUNT; > We hardcoded the child nodes to 2 to match previous x32 implementation. > Summary : MTL has 5 crash nodes for different dielets in the North only. > 1) PUNIT > 2) SOCN > 3) DMU > 4) Compute Die > 5) Graphics Die (GCD) > 6) Adamantine Die (ADM) – e RAM (This is not part of the MTL as of now) > But the crash log discovery for Graphics die (5th child node ) had incorrect offset and buffer size for storing crash record. I did not debug this further. This might be because bios is not configuring discovery table for graphics Die properly or it has completely disabled crashlog for Graphics die. Since we wanted the bert file to match the previous implementation x32 (which was iterating only 2 times due to the bug in the pointer implementation which went away when we converted to x64),we read only PUNIT and SOCN crashlog into SRAM even though DMU and compute Die were having valid crash record. > Coming back : The count should be read from the discovery table always and should not be hardcoded. For PTL the count is just 1 which is at the offset 0x50 and the record buffer is 0x12ec dwords. In the south PCD handled by PMC and does not belong to CPU crashlog handled by PUNIT I'm not sure why you want to bring the 32-bit vs 64-bit implementation into this discussion. The real problem is how many nodes to parse when looking for a crash. My experience has shown that two nodes are sufficient, even though other nodes might contain additional information. If you're not sure that enabling all nodes will work seamlessly for all platforms, you shouldn't enable this feature dynamically. As we've seen in the past, that can lead to breakage. I don't see how you think you can avoid introducing the same problem this time. My suggestion is to keep only two nodes for existing platforms and use PTL to experiment on all five nodes. If you wish, you can use a static Kconfig to control this feature. -- To view, visit https://review.coreboot.org/c/coreboot/+/85531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e Gerrit-Change-Number: 85531 Gerrit-PatchSet: 4 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 11:19:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Adding device id for Crashlog and Telemetry
by Subrata Banik (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85372?usp=email ) Change subject: soc/intel/pantherlake: Adding device id for Crashlog and Telemetry ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2959623986108a2c5e3dce16e892913a42d71755 Gerrit-Change-Number: 85372 Gerrit-PatchSet: 8 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 10:54:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Remove hardcoded value for child nodes
by Sowmya Aralguppe (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85531?usp=email ) Change subject: soc/intel/pantherlake: Remove hardcoded value for child nodes ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/pantherlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/85531/comment/65c9b5d0_e1415732?us… : PS4, Line 319: cpu_cl_disc_tab.header.fields.count = CRASHLOG_NODES_COUNT; > I'm wondering why the previously discussed items are now being ignored. […] We hardcoded the child nodes to 2 to match previous x32 implementation. Summary : MTL has 5 crash nodes for different dielets in the North only. 1) PUNIT 2) SOCN 3) DMU 4) Compute Die 5) Graphics Die (GCD) 6) Adamantine Die (ADM) – e RAM (This is not part of the MTL as of now) But the crash log discovery for Graphics die (5th child node ) had incorrect offset and buffer size for storing crash record. I did not debug this further. This might be because bios is not configuring discovery table for graphics Die properly or it has completely disabled crashlog for Graphics die. Since we wanted the bert file to match the previous implementation x32 (which was iterating only 2 times due to the bug in the pointer implementation which went away when we converted to x64),we read only PUNIT and SOCN crashlog into SRAM even though DMU and compute Die were having valid crash record. Coming back : The count should be read from the discovery table always and should not be hardcoded. For PTL the count is just 1 which is at the offset 0x50 and the record buffer is 0x12ec dwords. In the south PCD handled by PMC and does not belong to CPU crashlog handled by PUNIT -- To view, visit https://review.coreboot.org/c/coreboot/+/85531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I209366d324c95b7a32afdcfb792c34d927a0508e Gerrit-Change-Number: 85531 Gerrit-PatchSet: 4 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 10:52:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yu-Ping Wu (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 10:21:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add SPM firmware v1.0
by Yu-Ping Wu (Code Review) 11 Dec '24

11 Dec '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/blobs/+/85285?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add SPM firmware v1.0 ...................................................................... soc/mediatek/mt8196: Add SPM firmware v1.0 Add initial SPM firmware. TEST=build pass BUG=b:348147674 Change-Id: Ic5b5417b9b746fcca225209d9b17108a2499ac71 Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/spm_firmware.bin A soc/mediatek/mt8196/spm_firmware.bin.md5 A soc/mediatek/mt8196/spm_release_notes.txt 4 files changed, 26 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Verified; Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md index 7f83d7a..9af056e 100644 --- a/soc/mediatek/mt8196/README.md +++ b/soc/mediatek/mt8196/README.md @@ -4,6 +4,7 @@ - dpm.dm - dpm.pm - dram.elf +- spm_firmware.bin -------------------------------------------------------------------------------- # MCUPM introduction @@ -174,3 +175,23 @@ `$ strings dram.elf | grep "firmware version"` -------------------------------------------------------------------------------- +# SPM introduction +SPM is "System Power Manager" that provides power control for low power task. +SPM provides power related features, e.g. Suspend, Vcore dvfs + +SPM firmware is loaded into SPM SRAM at system initialization. + +## Who uses it +Coreboot will load spm_firmware.bin to SPM SRAM at ramstage. + +## How to load `spm_firmware.bin +Use CBFS to load `spm_firmware.bin`. +No need to pass other parameters to SPM. + +## Return value +No return value. + +## Version +`$ strings spm_firmware.bin | grep "spm firmware"` + +-------------------------------------------------------------------------------- diff --git a/soc/mediatek/mt8196/spm_firmware.bin b/soc/mediatek/mt8196/spm_firmware.bin new file mode 100644 index 0000000..53bdb78 --- /dev/null +++ b/soc/mediatek/mt8196/spm_firmware.bin Binary files differ diff --git a/soc/mediatek/mt8196/spm_firmware.bin.md5 b/soc/mediatek/mt8196/spm_firmware.bin.md5 new file mode 100644 index 0000000..e43ad13 --- /dev/null +++ b/soc/mediatek/mt8196/spm_firmware.bin.md5 @@ -0,0 +1 @@ +6fb3df16f2475f46cef3a11460debc82 *spm_firmware.bin diff --git a/soc/mediatek/mt8196/spm_release_notes.txt b/soc/mediatek/mt8196/spm_release_notes.txt new file mode 100644 index 0000000..f3b09fd --- /dev/null +++ b/soc/mediatek/mt8196/spm_release_notes.txt @@ -0,0 +1,4 @@ +** Build from MediaTek Internal ** + +# Version 1.0 +1. Initial release. -- To view, visit https://review.coreboot.org/c/blobs/+/85285?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ic5b5417b9b746fcca225209d9b17108a2499ac71 Gerrit-Change-Number: 85285 Gerrit-PatchSet: 7 Gerrit-Owner: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Jarried Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Kenji Yu, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 17: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85516/comment/8b472073_a917d005?us… : PS15, Line 11: enable > enable it Done File src/soc/mediatek/common/include/soc/sspm.h: https://review.coreboot.org/c/coreboot/+/85516/comment/37310035_5ea7153e?us… : PS15, Line 13: void sspm_enable_sram(void); > Can we add a blank line above, and another blank line below `sspm_init`? Done File src/soc/mediatek/common/sspm.c: https://review.coreboot.org/c/coreboot/+/85516/comment/aed7e9d1_99be383f?us… : PS15, Line 19: void sspm_init(void) : { : sspm.load_buffer = _dram_dma; : sspm.buffer_size = REGION_SIZE(dram_dma); : : mtk_init_mcu(&sspm); : } > ``` […] Done File src/soc/mediatek/mt8196/soc.c: https://review.coreboot.org/c/coreboot/+/85516/comment/f78e8c42_61c46857?us… : PS15, Line 30: sspm_enable_sram(); > remove Done File src/soc/mediatek/mt8196/sspm_sram.c: https://review.coreboot.org/c/coreboot/+/85516/comment/ebb94798_b29e463e?us… : PS15, Line 14: ( > remove Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 10:17:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit December 2024