coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by Paul Menzel (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85537/comment/c2f87e82_71ffc9a9?us… : PS5, Line 9: The boot time is estimated to increase by 50ms. Maybe: Due to no hardware access, the boot time is estimated to increase by 50 ms. https://review.coreboot.org/c/coreboot/+/85537/comment/69825477_8fa7cba0?us… : PS5, Line 9: Uldrenite supports the WWAN 5G device and uses variant.c to handle the power-on sequence according to the Rolling Wireless_RW350R-GL_Hardware Guide_Generic_V1.1. The boot time is estimated to increase by 50ms. : : At this stage, we do not yet have the board or key parts for verification. However, I still need to merge the CL to ensure that the WWAN functionality works. Once the motherboard is available, I will make adjustments to optimize and reduce the boot time. Please re-flow for 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 15:32:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Paul Menzel (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski. Paul Menzel has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... Patch Set 8: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85195/comment/9ba8e46b_71db5a43?us… : PS8, Line 13: TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. Please re-flow for 72 characters per line. https://review.coreboot.org/c/coreboot/+/85195/comment/242d198c_c7f19a0d?us… : PS8, Line 18: [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' : structure does not exist This could be one line, as it’s logs. -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Dec 2024 15:29:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85195/comment/ffcffa0d_b7494712?us… : PS7, Line 12: > Were you able to test this? If yes, please add a TEST= entry maybe filled with the new debug logs? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Dec 2024 15:14:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski. Hello Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85195?usp=email to look at the new patch set (#8). Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table Populate the PCI bridge IRQ routing table for Phoenix from the SMN registers to replace the stub implementation. The base addresses are copied from Genoa OpenSIL headers, which also correspond to Phoenix. TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. Before applying patch: [NOTE ] get_pci_routing_table stub: returning empty IRQ routing table [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist After applying patch: [DEBUG] 01.1: group: 0, swizzle: 0, irq: 0 [DEBUG] 01.2: group: 1, swizzle: 0, irq: 0 [DEBUG] 01.4: group: 0, swizzle: 2, irq: 2 [DEBUG] 01.5: group: 3, swizzle: 0, irq: 0 [DEBUG] 01.6: group: 4, swizzle: 0, irq: 0 [DEBUG] 02.5: group: 5, swizzle: 0, irq: 0 [DEBUG] 02.4: group: 0, swizzle: 1, irq: 2 [DEBUG] 01.3: group: 1, swizzle: 1, irq: 2 [DEBUG] 02.1: group: 2, swizzle: 2, irq: 3 [DEBUG] 02.2: group: 1, swizzle: 2, irq: 2 [DEBUG] 02.3: group: 3, swizzle: 2, irq: 1 [DEBUG] 02.6: group: 4, swizzle: 2, irq: 1 [DEBUG] 03.1: group: 2, swizzle: 0, irq: 0 [DEBUG] 03.2: group: 5, swizzle: 0, irq: 1 [DEBUG] 03.3: group: 5, swizzle: 2, irq: 1 [DEBUG] 03.4: group: 5, swizzle: 2, irq: 1 [DEBUG] 04.1: group: 2, swizzle: 2, irq: 1 [DEBUG] 08.1: group: 3, swizzle: 2, irq: 4 [DEBUG] 08.2: group: 4, swizzle: 2, irq: 4 [DEBUG] 08.3: group: 5, swizzle: 2, irq: 4 [DEBUG] PCI_CFG IRQ: Write PCI config space IRQ assignments [DEBUG] PCI_CFG IRQ: Finished writing PCI config space IRQ assignments Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/soc/amd/phoenix/pci_irq_routing.c 1 file changed, 62 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85195/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. John Su has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85537?usp=email ) Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85537/comment/8f7bdd72_49e80b2a?us… : PS3, Line 11: > Please add it. Done https://review.coreboot.org/c/coreboot/+/85537/comment/7dbe4a6e_1d58a62c?us… : PS3, Line 14: TEST=emerge-nissa coreboot > Thank you for the confirmation. Maybe add your answer to the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 11 Dec 2024 15:06:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: John Su <john_su(a)compal.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
by John Su (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85537?usp=email to look at the new patch set (#5). Change subject: mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence ...................................................................... mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence Uldrenite supports the WWAN 5G device and uses variant.c to handle the power-on sequence according to the Rolling Wireless_RW350R-GL_Hardware Guide_Generic_V1.1. The boot time is estimated to increase by 50ms. At this stage, we do not yet have the board or key parts for verification. However, I still need to merge the CL to ensure that the WWAN functionality works. Once the motherboard is available, I will make adjustments to optimize and reduce the boot time. BUG=b:381393809, b:383212261 BRANCH=None TEST=emerge-nissa coreboot Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldrenite/Makefile.mk A src/mainboard/google/brya/variants/uldrenite/variant.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85537/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85537?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8695920c2b3d2a27da62afcbe75e70d1ea09792 Gerrit-Change-Number: 85537 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Merge SKX and CPX
by Patrick Rudolph (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85557?usp=email to look at the new patch set (#4). Change subject: soc/intel/xeon_sp: Merge SKX and CPX ...................................................................... soc/intel/xeon_sp: Merge SKX and CPX Start merging SKX and CPX into one codebase: - Create a new 14nm folder - Add new Kconfig: SOC_INTEL_XEON_SP_14NM - Add shared Kconfig settings - Add combined CPU driver - Add combined ACPI and romstage code TODO: Merge additional code from skx/cpx folders. TEST: Still boots on ocp/tiogapass. Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/intel/cedarisland_crb/dsdt.asl M src/mainboard/ocp/deltalake/dsdt.asl M src/mainboard/ocp/tiogapass/dsdt.asl A src/soc/intel/xeon_sp/14nm/Kconfig A src/soc/intel/xeon_sp/14nm/Makefile.mk R src/soc/intel/xeon_sp/14nm/acpi/gpio.asl R src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl R src/soc/intel/xeon_sp/14nm/acpi/pch.asl R src/soc/intel/xeon_sp/14nm/acpi/pch_irq.asl R src/soc/intel/xeon_sp/14nm/acpi/pci_irqs.asl R src/soc/intel/xeon_sp/14nm/acpi/southcluster.asl R src/soc/intel/xeon_sp/14nm/acpi/uncore.asl R src/soc/intel/xeon_sp/14nm/acpi/uncore_irq.asl R src/soc/intel/xeon_sp/14nm/cpu.c R src/soc/intel/xeon_sp/14nm/iio_ioapic.c A src/soc/intel/xeon_sp/14nm/romstage.c R src/soc/intel/xeon_sp/14nm/soc_acpi.c M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.mk D src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_msr.h M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/skx/Makefile.mk M src/soc/intel/xeon_sp/skx/romstage.c D src/soc/intel/xeon_sp/skx/soc_acpi.c 27 files changed, 182 insertions(+), 534 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/85557/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Gerrit-Change-Number: 85557 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER
by Patrick Rudolph (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85561?usp=email to look at the new patch set (#4). Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER ...................................................................... soc/intel/xeon_sp: Allow OS to control LTR and AER There's no reason to tell the OS to disable LTR. On UEFI and on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP. There's no SMM (RAS) code that is able to parse AER structures, thus let the OS always control AER. On coreboot's GNR AER is also always granted to the OS. TEST: Run code on ocp/tiogapass and observed dmesg: The OS now prints: acpi PNP0A08:04: _OSC: OS now controls [PME PCIeCapability LTR] Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/14nm/acpi/iiostack.asl M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/85561/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Gerrit-Change-Number: 85561 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Initialize SSPM
by Yidi Lin (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Kenji Yu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85516?usp=email ) Change subject: soc/mediatek/mt8196: Initialize SSPM ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic56f0bad2f4cbf11d5711425d57c3b5b6bf283f0 Gerrit-Change-Number: 85516 Gerrit-PatchSet: 17 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kenji Yu <kenji.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 14:19:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr/acpi: Fix regression
by Patrick Rudolph (Code Review) 11 Dec '24

11 Dec '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85562?usp=email ) Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression ...................................................................... soc/intel/xeon_sp/spr/acpi: Fix regression Fix regression introduced in 177bb5e9b9789cc830f504815e711973190def4e "soc/intel/xeon_sp: Revise IIO domain ACPI name encoding". Ensure domain ACPI names in the DSDT are in sync with SSDT ACPI names. Fixes PCI devices not discovered on socket 1-3. TEST: Booted in ibm/sbp1 and found all PCI devices working, no errors in dmesg are shown. Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/85562/1 diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 553ca9d..7676a3f 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -8,7 +8,7 @@ #define _IIO_DEVICE_UID(str, skt, stk) STR(str##skt##stk) #define IIO_DEVICE_UID(str, skt, stk) _IIO_DEVICE_UID(str, skt, stk) -Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK)) +Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK)) { Name (_HID, "ACPI0017") /* CXL */ Name (_CID, Package (0x02) @@ -16,7 +16,7 @@ EisaId ("PNP0A08") /* PCI Express Bus */, EisaId ("PNP0A03") /* PCI Bus */ }) - Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) + Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET_NAME, STACK)) Method (_STA, 0, NotSerialized) { /* diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index fdb599e..a2cc03f 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -8,11 +8,11 @@ #define _IIO_DEVICE_UID(str, skt, stk) STR(str##skt##stk) #define IIO_DEVICE_UID(str, skt, stk) _IIO_DEVICE_UID(str, skt, stk) -Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK)) +Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK)) { Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) - Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) + Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET_NAME, STACK)) Method (_STA, 0, NotSerialized) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/85562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658 Gerrit-Change-Number: 85562 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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coreboot-gerrit December 2024