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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85128?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIC MT6363 ADC driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6363 ADC driver Add MT6363 AUXADC driver support, which is essential for handling the Analog-to-Digital Conversion (ADC) functionalities in the MT8196 SoC. TEST=build pass BUG=b:317009620 Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85128 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/common/include/soc/mt6363_sdmadc.h A src/soc/mediatek/common/mt6363_sdmadc.c M src/soc/mediatek/mt8196/Makefile.mk 3 files changed, 203 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h new file mode 100644 index 0000000..ae990c9 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6363_sdmadc.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MT6363_SDMADC_H__ +#define __MT6363_SDMADC_H__ + +#include <soc/spmi.h> +#include <types.h> + +enum { + PMIC_AUXADC_ADC_OUT_CH12_L_ADDR = 0x10d2, + MT6363_AUXADC_RQST1 = 0x1109, + PMIC_SDMADC_EXT_THR_SRC_SEL_ADDR = 0x11c4, +}; + +/* + * enum auxadc_channels - enumeration of auxadc channels + */ +enum auxadc_channel { + AUXADC_CHAN_VIN1, + AUXADC_CHAN_VIN2, + AUXADC_CHAN_VIN3, + AUXADC_CHAN_VIN4, + AUXADC_CHAN_VIN5, + AUXADC_CHAN_VIN6, + AUXADC_CHAN_VIN7, + AUXADC_CHAN_MAX, +}; + +/* + * enum sdmadc_pures - enumeration of sdmadc pull up resistor + */ +enum sdmadc_pures { + SDMADC_100K, + SDMADC_30K, + SDMADC_400K, + SDMADC_OPEN, +}; + +/** + * enum auxadc_val_type - enumeration of auxadc value's type + */ +enum auxadc_val_type { + AUXADC_VAL_PROCESSED, + AUXADC_VAL_RAW, +}; + +/** + * struct auxadc_chan_spec - specification of an auxadc channel + * @channel: What auxadc_channel is it. + * @hw_info: Hardware design level information + * @hw_info.ref_volt Reference voltage + * @hw_info.ratio: Resistor Ratio. + * If read operation is not provided, the processed + * value will be calculated as following: + * (raw value * ratio[0] * ref_volt) / ratio[1] + * @hw_info.max_time: Maximum wait time(us). + * @hw_info.min_time: Minimum wait time(us). + * @hw_info.poll_time: Wait time(us) between every polling during retry. + * @hw_info.enable_reg Register address of enable control. + * @hw_info.enable_mask Mask of enable control. + * @hw_info.ready_reg Register address of channel's ready status. + * @hw_info.ready_mask Mask of ready status. + * @hw_info.value_reg Register address of raw value. + * @hw_info.res Resolution of this channel (number of valid bits). + */ +struct auxadc_chan_spec { + int channel; + struct { + u32 ref_volt; + u32 ratio[2]; + u32 max_time; + u32 min_time; + u32 poll_time; + u32 enable_reg; + u32 enable_mask; + u32 ready_reg; + u32 ready_mask; + u32 value_reg; + u8 res; + } hw_info; + struct { + u32 set_reg; + u32 cmd; + } sdmadc_hw_info; +}; + +int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, enum sdmadc_pures pures, + enum auxadc_val_type type); + +#endif /* __MT6363_SDMADC_H__ */ diff --git a/src/soc/mediatek/common/mt6363_sdmadc.c b/src/soc/mediatek/common/mt6363_sdmadc.c new file mode 100644 index 0000000..eb4b978 --- /dev/null +++ b/src/soc/mediatek/common/mt6363_sdmadc.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6363TP_PMIC_Design_Notice_for_MT8196G_V0.2" + * Chapter number: 2.15. + * The setting values are provided by MeidaTek designers. + */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6363.h> +#include <soc/mt6363_sdmadc.h> +#include <soc/pmif.h> +#include <timer.h> + +#define ERR_INVALID_ARGS (-8) +#define ERR_TIMED_OUT (-13) + +#define AUXADC_RDY_BIT BIT(15) +/* 0.385us(2.89MHz) x 42T (SPL(100K=29T)+ADC_compare(12T)+sync(1T)) ~= 16us */ +#define AUXADC_AVG_TIME_US 16 +#define AUXADC_POLL_TIME_US 100 +#define AUXADC_TIMEOUT_US 32000 +#define VOLT_FULL 1840 + +#define EXT_THR_SEL_DEF_VALUE 0x80 +#define EXT_THR_PURES_SHIFT 3 + +#define SDMADC_CHAN_SPEC(src_sel) \ +{ \ + .hw_info = { \ + .ref_volt = VOLT_FULL, \ + .min_time = 128 * AUXADC_AVG_TIME_US, \ + .max_time = AUXADC_TIMEOUT_US, \ + .poll_time = AUXADC_POLL_TIME_US, \ + .ratio = { 1, 1 }, \ + .enable_reg = MT6363_AUXADC_RQST1, \ + .enable_mask = BIT(4), \ + .ready_reg = PMIC_AUXADC_ADC_OUT_CH12_L_ADDR, \ + .ready_mask = AUXADC_RDY_BIT, \ + .res = 15, \ + }, \ + .sdmadc_hw_info = { \ + .set_reg = PMIC_SDMADC_EXT_THR_SRC_SEL_ADDR, \ + .cmd = EXT_THR_SEL_DEF_VALUE | src_sel, \ + }, \ +} + +static const struct auxadc_chan_spec mt6363_sdmadc_chan_specs[] = { + [AUXADC_CHAN_VIN1] = SDMADC_CHAN_SPEC(1), + [AUXADC_CHAN_VIN2] = SDMADC_CHAN_SPEC(2), + [AUXADC_CHAN_VIN3] = SDMADC_CHAN_SPEC(3), + [AUXADC_CHAN_VIN4] = SDMADC_CHAN_SPEC(4), + [AUXADC_CHAN_VIN5] = SDMADC_CHAN_SPEC(5), + [AUXADC_CHAN_VIN6] = SDMADC_CHAN_SPEC(6), + [AUXADC_CHAN_VIN7] = SDMADC_CHAN_SPEC(7), +}; + +_Static_assert(ARRAY_SIZE(mt6363_sdmadc_chan_specs) == AUXADC_CHAN_MAX, + "Wrong array size for mt6363_sdmadc_chan_specs"); + +int mt6363_sdmadc_read(enum auxadc_channel channel, int *val, + enum sdmadc_pures pures, enum auxadc_val_type type) +{ + u8 wdata; + u32 regval; + u32 elapsed = 0; + const struct auxadc_chan_spec *chan; + + if (channel < AUXADC_CHAN_VIN1 || channel >= AUXADC_CHAN_MAX) { + printk(BIOS_ERR, "[%s] Invalid channel %d\n", __func__, channel); + return ERR_INVALID_ARGS; + } + + mt6363_init_pmif_arb(); + chan = &mt6363_sdmadc_chan_specs[channel]; + + wdata = chan->sdmadc_hw_info.cmd | (pures << EXT_THR_PURES_SHIFT); + mt6363_write8(chan->sdmadc_hw_info.set_reg, wdata); + + wdata = chan->hw_info.enable_mask; + mt6363_write8(chan->hw_info.enable_reg, wdata); + + udelay(chan->hw_info.min_time); + elapsed += chan->hw_info.min_time; + + while (1) { + regval = mt6363_read16(chan->hw_info.ready_reg); + if (regval & chan->hw_info.ready_mask) + break; + if (elapsed > chan->hw_info.max_time) { + printk(BIOS_ERR, "[%s] Auxadc read time out", __func__); + return ERR_TIMED_OUT; + } + udelay(chan->hw_info.poll_time); + elapsed += chan->hw_info.poll_time; + } + + regval &= (BIT(chan->hw_info.res) - 1); + switch (type) { + case AUXADC_VAL_RAW: + *val = regval; + break; + case AUXADC_VAL_PROCESSED: + *val = ((regval * chan->hw_info.ratio[0] * chan->hw_info.ref_volt) / + chan->hw_info.ratio[1]) >> chan->hw_info.res; + break; + } + return 0; +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 7a950d2..2a01ee5 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -45,6 +45,7 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c ramstage-y += ../common/mt6363.c mt6363.c +ramstage-y += ../common/mt6363_sdmadc.c ramstage-y += soc.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85128?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice3c286cd207e445392d5f0126a07ce4f40dcf8a Gerrit-Change-Number: 85128 Gerrit-PatchSet: 30 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6363 driver
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85127?usp=email ) ( 20 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add PMIC MT6363 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6363 driver 1. Add MT6363 driver in SoC folder 2. Add vtref18 set/get api 3. Add MT6363 LDO/BUCK enable api 4. Add pmif_arb for MT6363 TEST=build pass BUG=b:317009620 Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85127 Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/include/soc/mt6363.h A src/soc/mediatek/common/mt6363.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6363.c 4 files changed, 782 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mt6363.h b/src/soc/mediatek/common/include/soc/mt6363.h new file mode 100644 index 0000000..7e4487f --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6363.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6363_H__ +#define __SOC_MEDIATEK_MT6363_H__ + +#include <soc/spmi.h> +#include <types.h> + +enum { + PMIC_HWCID = 0x0008, + PMIC_SWCID0 = 0x000A, + PMIC_SWCID1 = 0x000B, + PMIC_TOP_CKPDN_CON0 = 0x010C, + PMIC_TOP_CKHWEN_CON0 = 0x012A, + PMIC_TOP_RST_MISC1 = 0x0139, + PMIC_TOP_RST_MISC1_SET = 0x013A, + PMIC_TOP_RST_MISC1_CLR = 0x013B, + PMIC_TOP_VRCTL_DBG_CON0 = 0x0231, + PMIC_VRCTL_VOSEL_VBUCK2 = 0x024E, + PMIC_OTP_CON0 = 0x038A, + PMIC_OTP_CON8 = 0x039A, + PMIC_OTP_CON11 = 0x03A0, + PMIC_OTP_CON12 = 0x03A2, + PMIC_OTP_CON13 = 0x03A4, + PMIC_PWRHOLD = 0x0A08, + PMIC_VCORE_DBG0 = 0x1526, + PMIC_VCORE_ELR0 = 0x152C, + PMIC_VBUCK2_DBG0 = 0x1596, + PMIC_VGPU11_DBG0 = 0x15A6, + PMIC_VBUCK4_DBG0 = 0x1696, + PMIC_VBUCK5_OP_EN_2 = 0x170F, + PMIC_VBUCK5_DBG0 = 0x1716, + PMIC_VS2_VOTER = 0x18AA, + PMIC_VS2_VOTER_CFG = 0x18B0, + PMIC_VS2_ELR0 = 0x18B4, + PMIC_VPA_CON0 = 0x1908, + PMIC_VPA_CON1 = 0x190E, + PMIC_VPA_DBG0 = 0x1914, + PMIC_BUCK_VPA_DLC_CON0 = 0x1918, + PMIC_BUCK_VPA_DLC_CON1 = 0x191A, + PMIC_VSRAM_PROC1_ELR = 0x1B44, + PMIC_VSRAM_PROC2_ELR = 0x1B46, + PMIC_LDO_VCN15_CON0 = 0x1B87, + PMIC_LDO_VRF09_CON0 = 0x1B95, + PMIC_LDO_VRF12_CON0 = 0x1Ba3, + PMIC_LDO_VRF13_CON0 = 0x1BB1, + PMIC_LDO_VRF18_CON0 = 0x1BBF, + PMIC_LDO_VTREF18_CON0 = 0x1C07, + PMIC_VSIM1_CON0 = 0x1CD0, + PMIC_LDO_VSRAM_DIGRF_CON0 = 0x1D1D, + PMIC_LDO_VSRAM_MDFE_CON0 = 0x1D87, + PMIC_VM18_CON0 = 0x1D88, + PMIC_VSRAM_PROC1_VOSEL1 = 0x1E90, + PMIC_VSRAM_PROC2_VOSEL1 = 0x1EB0, + PMIC_VTREF18_ANA_CON0 = 0x1F08, + PMIC_VTREF18_ANA_CON1 = 0x1F09, + PMIC_VM18_ANA_CON0 = 0x1F1F, + PMIC_VM18_ANA_CON1 = 0x1F20, + PMIC_VSIM1_ANA_CON0 = 0x1FA2, +}; + +struct pmic_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; +}; + +struct pmic_efuse { + unsigned short efuse_bit; + unsigned short addr; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6363_VBUCK1 = 0, + MT6363_VBUCK2, + MT6363_VBUCK3, + MT6363_VBUCK4, + MT6363_VM18 = 7, + MT6363_MAX, +}; + +#define EFUSE_WAIT_US 5000 +#define EFUSE_BUSY 1 + +#define EFUSE_RG_VPA_OC_FT 78 + +void mt6363_init(void); +void mt6363_buck_set_voltage(u32 buck_id, u32 buck_uv); +u32 mt6363_buck_get_voltage(u32 buck_id); +void mt6363_set_vm18_voltage(u32 vm18_uv); +u32 mt6363_get_vm18_voltage(void); +void mt6363_set_vtref18_voltage(u32 vtref18_uv); +u32 mt6363_get_vtref18_voltage(void); +void mt6363_set_vsim1_voltage(u32 vsim1_uv); +u32 mt6363_get_vsim1_voltage(void); +void mt6363_enable_vpa(bool enable); +void mt6363_enable_vsim1(bool enable); +void mt6363_enable_vm18(bool enable); +void mt6363_enable_vtref18(bool enable); +void mt6363_enable_buck5(bool enable); +void mt6363_enable_vcn15(bool enable); +void mt6363_enable_vrf09(bool enable); +void mt6363_enable_vrf12(bool enable); +void mt6363_enable_vrf13(bool enable); +void mt6363_enable_vrf18(bool enable); +void mt6363_enable_vram_digrf(bool enable); +void mt6363_enable_vram_mdfe(bool enable); +void mt6363_init_pmif_arb(void); +u32 mt6363_read16(u32 reg); +void mt6363_write8(u32 reg, u8 reg_val); +void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift); +void pmic_init_setting(void); + +#endif /* __SOC_MEDIATEK_MT6363_H__ */ diff --git a/src/soc/mediatek/common/mt6363.c b/src/soc/mediatek/common/mt6363.c new file mode 100644 index 0000000..9619d44 --- /dev/null +++ b/src/soc/mediatek/common/mt6363.c @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6363.h> +#include <soc/pmif.h> +#include <timer.h> + +#define MT6363_SET_DELAY_US 200 + +static const struct pmic_setting key_protect_setting[] = { + {0x39E, 0x9C, 0xFF}, + {0x39F, 0x9C, 0xFF}, + {0xFAB, 0x63, 0xFF}, + {0xFAC, 0x63, 0xFF}, + {0x142A, 0x43, 0xFF}, + {0x142B, 0x55, 0xFF}, + {0x3A7, 0x9C, 0xFF}, + {0x3A8, 0x9C, 0xFF}, + {0xA33, 0x29, 0xFF}, + {0xA34, 0x47, 0xFF}, + {0xC42, 0x06, 0xFF}, + {0xC43, 0x17, 0xFF}, +}; + +static struct pmif *pmif_arb; +u32 mt6363_read16(u32 reg) +{ + u16 rdata = 0; + + assert(pmif_arb); + pmif_arb->read16(pmif_arb, SPMI_SLAVE_4, reg, &rdata); + return rdata; +} + +void mt6363_write8(u32 reg, u8 data) +{ + assert(pmif_arb); + pmif_arb->write(pmif_arb, SPMI_SLAVE_4, reg, data); +} + +static void mt6363_write16(u32 reg, u16 data) +{ + assert(pmif_arb); + pmif_arb->write16(pmif_arb, SPMI_SLAVE_4, reg, data); +} + +static u32 mt6363_read_field(u32 reg, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_4, reg, mask, shift); +} + +void mt6363_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + assert(pmif_arb); + pmif_arb->write_field(pmif_arb, SPMI_SLAVE_4, reg, val, mask, shift); +} + +static void pmic_set_power_hold(void) +{ + printk(BIOS_INFO, "[%s]before POWER_HOLD = 0x%x\n", __func__, + mt6363_read_field(PMIC_PWRHOLD, 0x1, 0)); + mt6363_write_field(PMIC_PWRHOLD, 0x1, 0x1, 0); + printk(BIOS_INFO, "[%s]POWER_HOLD = 0x%x\n", __func__, + mt6363_read_field(PMIC_PWRHOLD, 0x1, 0)); +} + +static void pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + mt6363_write_field(PMIC_TOP_RST_MISC1_SET, 0x20, 0xFFFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + mt6363_write_field(PMIC_TOP_RST_MISC1_CLR, 0x02, 0xFFFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + mt6363_write_field(PMIC_TOP_RST_MISC1_SET, 0x01, 0xFFFF, 0); + /* Enable BUCK/LDO WDT VOSEL Debug */ + mt6363_write_field(PMIC_TOP_VRCTL_DBG_CON0, 0x1, 0x1, 0); + /* Clear WDT status */ + mt6363_write_field(PMIC_TOP_RST_MISC1_SET, 0x1, 0x1, 3); + udelay(50); + mt6363_write_field(PMIC_TOP_RST_MISC1_CLR, 0x1, 0x1, 3); + printk(BIOS_INFO, "[%s]WDTRSTB[0x%x]=0x%x\n", __func__, PMIC_TOP_RST_MISC1, + mt6363_read_field(PMIC_TOP_RST_MISC1, 0xFF, 0)); +} + +static void pmic_protect_key_setting(bool lock) +{ + const struct pmic_setting *entry; + + for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) { + entry = &key_protect_setting[i]; + mt6363_write16(entry->addr, lock ? 0 : entry->val); + } + printk(BIOS_INFO, "%s done\n", __func__); +} + +void mt6363_buck_set_voltage(u32 buck_id, u32 buck_uv) +{ + u32 vol_offset, vol_reg, vol, vol_step; + + switch (buck_id) { + case MT6363_VBUCK2: + vol_offset = 0; + vol_reg = PMIC_VRCTL_VOSEL_VBUCK2; + vol_step = 6250; + break; + default: + printk(BIOS_WARNING, "[%s] Unknown buck_id %u", __func__, buck_id); + return; + }; + + vol = (buck_uv - vol_offset) / vol_step; + mt6363_write_field(vol_reg, vol, 0xFF, 0); + udelay(MT6363_SET_DELAY_US); + printk(BIOS_INFO, "%s: %d, %d\n", __func__, buck_id, vol); +} + +u32 mt6363_buck_get_voltage(u32 buck_id) +{ + u32 vol_shift, vol_offset, vol_reg, vol, vol_step; + + switch (buck_id) { + case MT6363_VBUCK2: + vol_shift = 0; + vol_offset = 0; + vol_reg = PMIC_VBUCK2_DBG0; + vol_step = 6250; + break; + case MT6363_VBUCK4: + vol_shift = 0; + vol_offset = 0; + vol_reg = PMIC_VBUCK4_DBG0; + vol_step = 6250; + break; + default: + printk(BIOS_WARNING, "[%s] Unknown buck_id %u", __func__, buck_id); + return 0; + }; + + vol = mt6363_read_field(vol_reg, 0xFF, vol_shift); + printk(BIOS_INFO, "%s: %d, %d\n", __func__, buck_id, vol); + return vol_offset + vol * vol_step; +} + +void mt6363_set_vm18_voltage(u32 vm18_uv) +{ + u8 reg_vol; + + assert(pmif_arb); + assert(vm18_uv >= 1700000); + assert(vm18_uv < 2000000); + + reg_vol = ((vm18_uv - 1700000) / 50000) + 12; + mt6363_write8(PMIC_VM18_ANA_CON1, reg_vol); + mt6363_write8(PMIC_VM18_ANA_CON0, 0x0); + udelay(MT6363_SET_DELAY_US); + printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vm18_uv); +} + +u32 mt6363_get_vm18_voltage(void) +{ + u32 reg_vol, reg_cali, voltage; + + assert(pmif_arb); + + reg_cali = mt6363_read_field(PMIC_VM18_ANA_CON0, 0xF, 0); + reg_vol = mt6363_read_field(PMIC_VM18_ANA_CON1, 0xF, 0); + voltage = (reg_vol - 12) * 50000 + reg_cali * 5000 + 1700000; + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, %d\n", __func__, + reg_vol, reg_cali, voltage); + return voltage; +} + +void mt6363_set_vtref18_voltage(u32 vtref18_uv) +{ + u8 reg_vol, reg_cali; + + assert(pmif_arb); + assert(vtref18_uv >= 1800000); + assert(vtref18_uv <= 3400000); + + reg_cali = ((vtref18_uv - 1800000) % 100000) / 10000; + reg_vol = (vtref18_uv - 1800000) / 100000; + mt6363_write8(PMIC_VTREF18_ANA_CON0, reg_cali); + mt6363_write8(PMIC_VTREF18_ANA_CON1, reg_vol); + udelay(MT6363_SET_DELAY_US); + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, %d\n", __func__, reg_vol, reg_cali, + vtref18_uv); +} + +u32 mt6363_get_vtref18_voltage(void) +{ + u32 reg_vol, reg_cali, vtref18_uv; + + assert(pmif_arb); + + reg_cali = mt6363_read_field(PMIC_VTREF18_ANA_CON0, 0xF, 0); + reg_vol = mt6363_read_field(PMIC_VTREF18_ANA_CON1, 0xF, 0); + vtref18_uv = reg_cali * 10000 + reg_vol * 100000 + 1800000; + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, %d\n", __func__, reg_vol, reg_cali, + vtref18_uv); + return vtref18_uv; +} + +void mt6363_enable_vtref18(bool enable) +{ + mt6363_write_field(PMIC_LDO_VTREF18_CON0, enable, 0x1, 0); +} + +void mt6363_enable_buck5(bool enable) +{ + mt6363_write_field(PMIC_VBUCK5_OP_EN_2, enable, 0x7, 0); +} + +void mt6363_enable_vcn15(bool enable) +{ + mt6363_write_field(PMIC_LDO_VCN15_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf09(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF09_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf12(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF12_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf13(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF13_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vrf18(bool enable) +{ + mt6363_write_field(PMIC_LDO_VRF18_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vram_digrf(bool enable) +{ + mt6363_write_field(PMIC_LDO_VSRAM_DIGRF_CON0, enable, 0x1, 0); +} + +void mt6363_enable_vram_mdfe(bool enable) +{ + mt6363_write_field(PMIC_LDO_VSRAM_MDFE_CON0, enable, 0x1, 0); +} + +void mt6363_init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1); + assert(pmif_arb); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spi"); + + printk(BIOS_INFO, "[%s][MT6363]CHIP ID = 0x%x\n", __func__, + mt6363_read_field(PMIC_SWCID1, 0xFF, 0)); +} + +void mt6363_init(void) +{ + mt6363_init_pmif_arb(); + pmic_set_power_hold(); + pmic_wdt_set(); + pmic_protect_key_setting(false); + pmic_init_setting(); + pmic_protect_key_setting(true); +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index f898775..7a950d2 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -30,6 +30,7 @@ romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c @@ -43,6 +44,7 @@ ramstage-y += ../common/mcu.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c +ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += soc.c ramstage-y += ../common/pmif_clk.c pmif_clk.c ramstage-y += ../common/pmif.c pmif_init.c diff --git a/src/soc/mediatek/mt8196/mt6363.c b/src/soc/mediatek/mt8196/mt6363.c new file mode 100644 index 0000000..e41ce0e --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6363.c @@ -0,0 +1,390 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6363TP_PMIC_Design_Notice_for_MT8196G_V0.2". + * The setting values are provided by MeidaTek designers. + */ + +#include <console/console.h> +#include <soc/mt6363.h> + +static const struct pmic_setting init_setting[] = { + {0x16, 0xA, 0xA}, + {0x19, 0x1F, 0x1F}, + {0x21, 0x1, 0x1}, + {0x22, 0x1, 0x1}, + {0x47, 0x0, 0xFF}, + {0x4A, 0x0, 0x80}, + {0x55, 0x5, 0x5}, + {0x8E, 0x60, 0xFF}, + {0x91, 0xC0, 0xFF}, + {0xAD, 0x0, 0x38}, + {0x10F, 0x10, 0x10}, + {0x112, 0x4, 0x4}, + {0x12D, 0x1, 0x1}, + {0x139, 0x21, 0x21}, + {0x230, 0x0, 0x1}, + {0x413, 0x7, 0xFF}, + {0x416, 0x12, 0xFF}, + {0x417, 0x0, 0x7}, + {0x90D, 0x10, 0x10}, + {0x98A, 0x10, 0x10}, + {0xA08, 0x1, 0x1}, + {0xA0C, 0x78, 0x7F}, + {0xA0E, 0x0, 0x2}, + {0xA0F, 0x1, 0x1}, + {0xA10, 0xE0, 0xE0}, + {0xA14, 0x40, 0x60}, + {0xA22, 0x80, 0x80}, + {0xA26, 0xFF, 0xFF}, + {0xA27, 0xFF, 0xFF}, + {0xA28, 0xFF, 0xFF}, + {0xA29, 0xFF, 0xFF}, + {0xA2A, 0x1, 0x1}, + {0xA39, 0x35, 0xFF}, + {0xA3A, 0x1, 0xFF}, + {0xA3B, 0x2, 0xFF}, + {0xA3C, 0x1C, 0xFF}, + {0xA3D, 0x20, 0xFF}, + {0xA3E, 0x34, 0xFF}, + {0xA3F, 0x34, 0xFF}, + {0xA40, 0x3, 0xFF}, + {0xA41, 0x1E, 0xFF}, + {0xA42, 0x1C, 0xFF}, + {0xA43, 0x2B, 0xFF}, + {0xA44, 0x1F, 0xFF}, + {0xA45, 0x1F, 0xFF}, + {0xA46, 0x2, 0xFF}, + {0xA47, 0x1F, 0xFF}, + {0xA48, 0x22, 0xFF}, + {0xA49, 0x22, 0xFF}, + {0xA4A, 0x22, 0xFF}, + {0xA4B, 0xFF, 0xFF}, + {0xA4C, 0x21, 0xFF}, + {0xA4D, 0x24, 0xFF}, + {0xA4E, 0x34, 0xFF}, + {0xA4F, 0x24, 0xFF}, + {0xA50, 0x30, 0xFF}, + {0xA51, 0x2A, 0xFF}, + {0xA52, 0x2B, 0xFF}, + {0xA53, 0x22, 0xFF}, + {0xA54, 0x23, 0xFF}, + {0xA55, 0xFF, 0xFF}, + {0xA56, 0x34, 0xFF}, + {0xA57, 0x5, 0xFF}, + {0xA58, 0x20, 0xFF}, + {0xA59, 0xFF, 0xFF}, + {0xA5A, 0xFF, 0xFF}, + {0xA5B, 0xFF, 0xFF}, + {0xC88, 0x10, 0x10}, + {0xC89, 0x18, 0xFE}, + {0xC8A, 0x4, 0xFF}, + {0xC90, 0x44, 0x7F}, + {0xD08, 0x0, 0x1}, + {0xDA1, 0x4, 0x7}, + {0xE88, 0x0, 0x40}, + {0xE89, 0x40, 0x40}, + {0xF8C, 0x15, 0x15}, + {0xF8D, 0x5, 0x5}, + {0x1188, 0x0, 0x80}, + {0x140E, 0x0, 0x40}, + {0x1445, 0x0, 0xFF}, + {0x1446, 0x0, 0xFF}, + {0x1447, 0x0, 0xF}, + {0x1487, 0x6C, 0xFF}, + {0x1488, 0x0, 0x1}, + {0x148A, 0x19, 0x7F}, + {0x148B, 0x33, 0x7F}, + {0x1507, 0x40, 0xFF}, + {0x1508, 0x0, 0x1}, + {0x150A, 0x5, 0x7F}, + {0x150B, 0x19, 0x7F}, + {0x1587, 0xA8, 0xFF}, + {0x1588, 0x0, 0x1}, + {0x158A, 0x5, 0x7F}, + {0x158B, 0x19, 0x7F}, + {0x1607, 0x40, 0xFF}, + {0x1608, 0x0, 0x1}, + {0x160A, 0x5, 0x7F}, + {0x160B, 0x19, 0x7F}, + {0x1687, 0x78, 0xFF}, + {0x1688, 0x0, 0x1}, + {0x168A, 0xC, 0x7F}, + {0x168B, 0x19, 0x7F}, + {0x1707, 0x40, 0xFF}, + {0x1708, 0x0, 0x1}, + {0x170A, 0xC, 0x7F}, + {0x1787, 0x40, 0xFF}, + {0x1788, 0x0, 0x1}, + {0x178A, 0x5, 0x7F}, + {0x1807, 0x40, 0xFF}, + {0x1808, 0x0, 0x1}, + {0x180A, 0x5, 0x7F}, + {0x1887, 0x98, 0xFF}, + {0x1888, 0x0, 0x1}, + {0x188A, 0x19, 0x7F}, + {0x188B, 0x33, 0x7F}, + {0x1907, 0xA0, 0xFF}, + {0x1908, 0x0, 0x1}, + {0x190A, 0xC, 0x7F}, + {0x190B, 0x19, 0x7F}, + {0x198A, 0x2E, 0x2F}, + {0x198C, 0xF8, 0xF8}, + {0x198D, 0x32, 0x3F}, + {0x198F, 0xC, 0xC}, + {0x1990, 0xED, 0xFF}, + {0x1991, 0x10, 0xFF}, + {0x1992, 0x0, 0xF}, + {0x1995, 0x60, 0x60}, + {0x1996, 0x45, 0xFF}, + {0x1997, 0x2, 0x2}, + {0x1998, 0x10, 0x10}, + {0x1999, 0x2D, 0x2F}, + {0x199B, 0xF8, 0xF8}, + {0x199C, 0x32, 0x3F}, + {0x199E, 0xC, 0xC}, + {0x199F, 0xED, 0xFF}, + {0x19A0, 0x0, 0xFF}, + {0x19A4, 0x60, 0x60}, + {0x19A5, 0x45, 0xFF}, + {0x19A6, 0x2, 0x2}, + {0x19AC, 0x85, 0x87}, + {0x19AF, 0x0, 0x1}, + {0x19B4, 0x3, 0x87}, + {0x19B7, 0x0, 0x1}, + {0x1A08, 0x10, 0x10}, + {0x1A09, 0x2D, 0x2F}, + {0x1A0B, 0xF8, 0xF8}, + {0x1A0C, 0x32, 0x3F}, + {0x1A0E, 0xC, 0xC}, + {0x1A0F, 0xED, 0xFF}, + {0x1A10, 0x0, 0xFF}, + {0x1A12, 0x10, 0x50}, + {0x1A13, 0x2D, 0x2F}, + {0x1A14, 0xC1, 0xC1}, + {0x1A15, 0xFA, 0xFF}, + {0x1A16, 0x32, 0x3F}, + {0x1A18, 0xC, 0xC}, + {0x1A19, 0x77, 0xFF}, + {0x1A1A, 0xC0, 0xFF}, + {0x1A1B, 0x2B, 0x7F}, + {0x1A1C, 0x10, 0x50}, + {0x1A1D, 0x2D, 0x2F}, + {0x1A1E, 0xC1, 0xC1}, + {0x1A1F, 0xFA, 0xFF}, + {0x1A20, 0x32, 0x3F}, + {0x1A22, 0xC, 0xC}, + {0x1A23, 0x77, 0xFF}, + {0x1A24, 0xC0, 0xFF}, + {0x1A25, 0x2B, 0x7F}, + {0x1A27, 0x2E, 0x2F}, + {0x1A29, 0xF8, 0xF8}, + {0x1A2A, 0x32, 0x3F}, + {0x1A2C, 0xC, 0xC}, + {0x1A2D, 0xED, 0xFF}, + {0x1A2E, 0x10, 0xFF}, + {0x1A2F, 0x0, 0xF}, + {0x1A36, 0x4, 0xC}, + {0x1A37, 0xFE, 0xFF}, + {0x1A39, 0xCD, 0xFF}, + {0x1A3A, 0x7F, 0xFF}, + {0x1A3B, 0x7F, 0xFF}, + {0x1A3C, 0x45, 0xFF}, + {0x1A3D, 0xF0, 0xF0}, + {0x1A45, 0x6, 0x87}, + {0x1A4C, 0x6, 0x87}, + {0x1A53, 0x6, 0x87}, + {0x1A5A, 0x5, 0x87}, + {0x1A5D, 0x0, 0x78}, + {0x1A88, 0x10, 0x50}, + {0x1A89, 0x2D, 0x2F}, + {0x1A8B, 0xF8, 0xF8}, + {0x1A8C, 0x32, 0x3F}, + {0x1A8E, 0xC, 0xC}, + {0x1A8F, 0xED, 0xFF}, + {0x1A90, 0x0, 0xFF}, + {0x1A92, 0x10, 0x50}, + {0x1A93, 0x2D, 0x2F}, + {0x1A94, 0x0, 0x1}, + {0x1A95, 0xFC, 0xFF}, + {0x1A96, 0x32, 0x3F}, + {0x1A98, 0xC, 0xC}, + {0x1A99, 0xED, 0xFF}, + {0x1A9A, 0x0, 0xFF}, + {0x1A9B, 0x0, 0xF}, + {0x1A9C, 0x10, 0x10}, + {0x1A9D, 0x2D, 0x2F}, + {0x1A9E, 0xC1, 0xC1}, + {0x1A9F, 0xFA, 0xFF}, + {0x1AA0, 0x32, 0x3F}, + {0x1AA2, 0xC, 0xC}, + {0x1AA3, 0x77, 0xFF}, + {0x1AA4, 0xC0, 0xFF}, + {0x1AA5, 0x2B, 0x7F}, + {0x1AA6, 0x10, 0x10}, + {0x1AA7, 0x2D, 0x2F}, + {0x1AA8, 0xC1, 0xC1}, + {0x1AA9, 0xFA, 0xFF}, + {0x1AAA, 0x32, 0x3F}, + {0x1AAC, 0xC, 0xC}, + {0x1AAD, 0x77, 0xFF}, + {0x1AAE, 0xC0, 0xFF}, + {0x1AAF, 0x2B, 0x7F}, + {0x1AB7, 0xFC, 0xFE}, + {0x1AB9, 0xCD, 0xFF}, + {0x1ABA, 0xCD, 0xFF}, + {0x1ABB, 0x7F, 0xFF}, + {0x1ABC, 0x7F, 0xFF}, + {0x1ABD, 0xF0, 0xF0}, + {0x1ABE, 0x0, 0x20}, + {0x1AC5, 0x6, 0x87}, + {0x1ACC, 0x6, 0x87}, + {0x1AD3, 0x6, 0x87}, + {0x1ADA, 0x6, 0x87}, + {0x1ADD, 0x10, 0x78}, + {0x1B0D, 0xF, 0xF}, + {0x1B0E, 0x1, 0x1}, + {0x1B11, 0xFF, 0xFF}, + {0x1B14, 0xFF, 0xFF}, + {0x1B17, 0xFF, 0xFF}, + {0x1B1A, 0x1, 0x1}, + {0x1B33, 0x8, 0x8}, + {0x1B88, 0x10, 0x10}, + {0x1B89, 0x0, 0x80}, + {0x1B96, 0x10, 0x10}, + {0x1B97, 0x0, 0x80}, + {0x1BA4, 0x10, 0x10}, + {0x1BA5, 0x0, 0x80}, + {0x1BB2, 0x10, 0x10}, + {0x1BB3, 0x0, 0x80}, + {0x1BC0, 0x10, 0x10}, + {0x1BC1, 0x0, 0x80}, + {0x1BCE, 0x10, 0x10}, + {0x1BCF, 0x0, 0x80}, + {0x1C08, 0x10, 0x10}, + {0x1C09, 0x0, 0x80}, + {0x1C0E, 0x40, 0x40}, + {0x1C16, 0x10, 0x10}, + {0x1C17, 0x0, 0x80}, + {0x1C1C, 0x40, 0x40}, + {0x1C24, 0x10, 0x10}, + {0x1C25, 0x0, 0x80}, + {0x1C32, 0x10, 0x10}, + {0x1C33, 0x0, 0x80}, + {0x1C40, 0x10, 0x10}, + {0x1C41, 0x0, 0x80}, + {0x1C4E, 0x10, 0x10}, + {0x1C4F, 0x0, 0x80}, + {0x1C88, 0x10, 0x10}, + {0x1C89, 0x0, 0x80}, + {0x1C96, 0x10, 0x10}, + {0x1C97, 0x0, 0x80}, + {0x1CA4, 0x10, 0x10}, + {0x1CA5, 0x0, 0x80}, + {0x1CB2, 0x10, 0x10}, + {0x1CB3, 0x0, 0x80}, + {0x1CC0, 0x10, 0x10}, + {0x1CC1, 0x0, 0x80}, + {0x1D08, 0x10, 0x10}, + {0x1D09, 0x0, 0x80}, + {0x1D1E, 0x10, 0x10}, + {0x1D1F, 0x0, 0x80}, + {0x1D23, 0x20, 0x7F}, + {0x1D27, 0xC, 0x7F}, + {0x1D28, 0x19, 0x7F}, + {0x1D88, 0x10, 0x10}, + {0x1D89, 0x0, 0x80}, + {0x1D8D, 0x18, 0x7F}, + {0x1D91, 0x5, 0x7F}, + {0x1D92, 0x19, 0x7F}, + {0x1DA3, 0x10, 0x10}, + {0x1DA4, 0x0, 0x80}, + {0x1DA8, 0x4C, 0x7F}, + {0x1DAC, 0x5, 0x7F}, + {0x1DAD, 0x19, 0x7F}, + {0x1DB8, 0x14, 0x1C}, + {0x1DB9, 0xF, 0xF}, + {0x1DBA, 0xC0, 0xFF}, + {0x1DBC, 0x60, 0xFF}, + {0x1E08, 0x10, 0x10}, + {0x1E09, 0x0, 0x80}, + {0x1E0D, 0x7F, 0x7F}, + {0x1E11, 0xF, 0x7F}, + {0x1E12, 0x14, 0x7F}, + {0x1E1E, 0x10, 0x10}, + {0x1E1F, 0x0, 0x80}, + {0x1E27, 0xF, 0x7F}, + {0x1E28, 0x14, 0x7F}, + {0x1E88, 0x10, 0x10}, + {0x1E89, 0x0, 0x80}, + {0x1E8D, 0x7F, 0x7F}, + {0x1E91, 0x5, 0x7F}, + {0x1E92, 0x19, 0x7F}, + {0x1E9E, 0x10, 0x10}, + {0x1E9F, 0x0, 0x80}, + {0x1EA3, 0x58, 0x7F}, + {0x1EA7, 0xC, 0x7F}, + {0x1EA8, 0xC, 0x7F}, + {0x1F16, 0x2, 0x3}, + {0x1F17, 0x0, 0xF}, + {0x1F1B, 0x2, 0xF}, + {0x1F1E, 0x2, 0x3}, + {0x1F2A, 0x2, 0x3}, + {0x1F2E, 0x2, 0x3}, + {0x1F8A, 0x8, 0xC}, + {0x1F8C, 0x4, 0x6}, + {0x1F8E, 0x4, 0x6}, + {0x1F90, 0x4, 0x6}, + {0x1F94, 0x2, 0x3}, + {0x1F98, 0x1, 0x3}, + {0x1F9C, 0x1, 0x3}, + {0x1FA0, 0x2, 0x3}, + {0x1FA4, 0x8, 0xC}, + {0x1FAB, 0x8, 0xC}, + {0x1FAD, 0x4, 0x6}, + {0x1FB0, 0x0, 0x10}, + {0x2207, 0xE0, 0xE0}, + {0x2208, 0xE0, 0xE0}, + {0x2209, 0xE0, 0xE0}, + {0x220A, 0xE0, 0xE0}, + {0x2214, 0xF0, 0xF0}, + {0x2216, 0x0, 0x7}, + + /* Add UVLO 2.0 setting. also need to modify dts setting for main pmic */ + {0xA5E, 0x2, 0x2}, + {0xA89, 0x4, 0xF}, + {0xA8A, 0x4, 0xF}, + {0xA95, 0x40, 0x40}, + /* + * 1. Set VS1_VOTER_VOSEL = 1.8875V + * 2. Set VS1_VOTER_EN = 0x8 (bit3 for VS1 users) + */ + {0x18A0, 0x97, 0xFF}, + {0x189A, 0x8, 0xFF}, + /* + * 1. Set VS2_VOTER_VOSEL = 1.275V + * 2. Set VS2_VOTER_EN = 0x48 (bit6/3 for VS2 users) + */ + {0x14A0, 0x66, 0xFF}, + {0x149A, 0x48, 0xFF}, + /* + * 1. Set VS3_VOTER_VOSEL = 0.975V + * 2. Set VS3_VOTER_EN = 0x8 (bit3 for VS3 users) + */ + {0x1920, 0x9C, 0xFF}, + {0x191A, 0x8, 0xFF}, +}; + +void pmic_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6363_write_field(init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, 0); + + /* + * TODO: Disable unused modem power in a separate function and + * call that function from mainboard folder. + */ + printk(BIOS_INFO, "%s done\n", __func__); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85127?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf493b802522deba575d98c2ed69a93e94ce3d4e Gerrit-Change-Number: 85127 Gerrit-PatchSet: 28 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email ) Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support ...................................................................... soc/mediatek/mt8196: Add PMIF and PMIC driver support Implement PMIF driver for communication between SoC and PMIC. Develop SPMI driver for communication over the SPMI bus. Add necessary configurations and base addresses to support PMIF. TEST=build pass, check boot log with: [INFO ] mtk_pmif_init: SPMI_MASTER_1, 0 [INFO ] mtk_pmif_init: SPMI_MASTER_0, 0 BUG=b:317009620 Change-Id: I232015f45735ee5278b09d0352410617a1565177 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85126 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/pmif.h A src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/pmif_clk.c A src/soc/mediatek/mt8196/pmif_init.c A src/soc/mediatek/mt8196/pmif_spmi.c 7 files changed, 1,729 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 0410129..f898775 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -30,6 +30,9 @@ romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/pmif_clk.c pmif_clk.c +romstage-y += ../common/pmif.c pmif_init.c +romstage-y += pmif_spmi.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c ramstage-y += ../common/dpm_v2.c @@ -41,6 +44,9 @@ ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c ramstage-y += soc.c +ramstage-y += ../common/pmif_clk.c pmif_clk.c +ramstage-y += ../common/pmif.c pmif_init.c +ramstage-y += pmif_spmi.c ramstage-y += ../common/usb.c usb.c BL31_MAKEARGS += PLAT=mt8196 diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index e4a4107..b252eec 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -34,6 +34,8 @@ CKSYS_GP2_BASE = IO_PHYS + 0x0000C000, APMIXEDSYS_GP2_BASE = IO_PHYS + 0x0000C800, BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, + PMIF_SPI_BASE = IO_PHYS + 0x00024000, + PMICSPI_MST_BASE = IO_PHYS + 0x00025000, BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, GPIO_BASE = IO_PHYS + 0x0002D000, DBGSYS_AO_DEBUG_BASE = IO_PHYS + 0x00031000, diff --git a/src/soc/mediatek/mt8196/include/soc/pmif.h b/src/soc/mediatek/mt8196/include/soc/pmif.h new file mode 100644 index 0000000..a114dc6 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/pmif.h @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __MT8196_SOC_PMIF_H__ +#define __MT8196_SOC_PMIF_H__ + +#include <device/mmio.h> +#include <soc/pmif_common.h> +#include <types.h> + +/* indicate which number SW channel start, by project */ +#define PMIF_SPMI_SW_CHAN BIT(17) +#define PMIF_SPMI_INF 0x579BFF +#define PMIF_SPMI_INF_P 0xFFFFFF + +struct mtk_pmif_regs { + u32 init_done; + u32 reserved1[5]; + u32 inf_busy_sta; + u32 other_busy_sta_0; + u32 other_busy_sta_1; + u32 inf_en; + u32 other_inf_en; + u32 inf_cmd_per[4]; + u32 inf_max_bytecnt_per[4]; + u32 staupd_ctrl; + u32 reserved2[48]; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 reserved3[13]; + u32 arb_en; + u32 reserved4[34]; + u32 lat_cnter_ctrl; + u32 lat_cnter_en; + u32 lat_limit_loading; + u32 lat_limit[23]; + u32 reserved5[86]; + u32 crc_ctrl; + u32 crc_sta; + u32 sig_mode; + u32 pmic_sig_addr; + u32 pmic_sig_val; + u32 reserved6[2]; + u32 cmdissue_en; + u32 reserved7[10]; + u32 timer_ctrl; + u32 timer_sta_0; + u32 timer_sta_1; + u32 sleep_protection_ctrl; + u32 reserved8[5]; + u32 spi_mode_ctrl; + u32 reserved9[2]; + u32 pmic_eint_sta_addr; + u32 reserved10[2]; + u32 irq_event_en_0; + u32 irq_flag_raw_0; + u32 irq_flag_0; + u32 irq_clr_0; + u32 reserved11[244]; + u32 swinf_0_acc; + u32 swinf_0_wdata_31_0; + u32 swinf_0_wdata_63_32; + u32 reserved12[2]; + u32 swinf_0_rdata_31_0; + u32 swinf_0_rdata_63_32; + u32 reserved13[2]; + u32 swinf_0_vld_clr; + u32 swinf_0_sta; + u32 reserved14[5]; + u32 swinf_1_acc; + u32 swinf_1_wdata_31_0; + u32 swinf_1_wdata_63_32; + u32 reserved15[2]; + u32 swinf_1_rdata_31_0; + u32 swinf_1_rdata_63_32; + u32 reserved16[2]; + u32 swinf_1_vld_clr; + u32 swinf_1_sta; + u32 reserved17[5]; + u32 swinf_2_acc; + u32 swinf_2_wdata_31_0; + u32 swinf_2_wdata_63_32; + u32 reserved18[2]; + u32 swinf_2_rdata_31_0; + u32 swinf_2_rdata_63_32; + u32 reserved19[2]; + u32 swinf_2_vld_clr; + u32 swinf_2_sta; + u32 reserved20[5]; + u32 swinf_3_acc; + u32 swinf_3_wdata_31_0; + u32 swinf_3_wdata_63_32; + u32 reserved21[2]; + u32 swinf_3_rdata_31_0; + u32 swinf_3_rdata_63_32; + u32 reserved22[2]; + u32 swinf_3_vld_clr; + u32 swinf_3_sta; + u32 reserved23[133]; +}; + +check_member(mtk_pmif_regs, inf_busy_sta, 0x18); +check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); +check_member(mtk_pmif_regs, arb_en, 0x0150); +check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0); +check_member(mtk_pmif_regs, crc_ctrl, 0x39C); +check_member(mtk_pmif_regs, cmdissue_en, 0x3B8); +check_member(mtk_pmif_regs, timer_ctrl, 0x3E4); +check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408); +check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414); +check_member(mtk_pmif_regs, irq_event_en_0, 0x420); +check_member(mtk_pmif_regs, swinf_0_acc, 0x800); + +#define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0x880) +#define PMIF_SPMI_AP_CHAN_P (PMIF_SPMI_P_BASE + 0x880) +#define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0x880) + +#define mtk_spmi_mst_p ((struct mtk_spmi_mst_reg *)SPMI_MST_P_BASE) + +struct mtk_scp_regs { + u32 reserved[27]; + u32 scp_clk_on_ctrl; +}; + +check_member(mtk_scp_regs, scp_clk_on_ctrl, 0x6C); + +#define mtk_scp ((struct mtk_scp_regs *)(SCP_CFG_BASE + 0x21000)) + +enum { + PMIF_ULPOSC_TARGET_FREQ_MHZ = 260, + PMIF_VLPCK_TARGET_FREQ_MHZ = 520, +}; + +/* calibation miss rate, unit: 0.1% */ +#define CAL_MIS_RATE 20 +#define FREQ_METER_VLP_OSC_CK 24 +#define FREQ_METER_VLP_AD_OSC_SYNC_CK 48 +#define FREQ_METER_VLP_AD_OSC_CK 59 +#define PMIF_USE_FIX_26M_CLK 0 + +/* calibation tolerance rate, unit: 0.1% */ +enum { + CAL_TOL_RATE = 40, + CAL_MAX_VAL = 0x1FF, +}; + +#endif /*__MT8196_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8196/include/soc/spm.h b/src/soc/mediatek/mt8196/include/soc/spm.h new file mode 100644 index 0000000..b0f1264 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/spm.h @@ -0,0 +1,890 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_MT8196_SPM_H +#define SOC_MEDIATEK_MT8196_SPM_H + +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/mtcmos.h> +#include <soc/spm_common.h> +#include <types.h> + +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB BIT(0) + +#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098 +#define SPM_ACK_CHK_3_HW_S1_CNT 1 + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_CK_EN_LSB BIT(2) +#define PCM_SW_RESET_LSB BIT(15) + +/* PCM_CON1 (0x1C001000+0x01C) */ +#define REG_SPM_APB_INTERNAL_EN_LSB BIT(3) +#define REG_PCM_TIMER_EN_LSB BIT(5) +#define REG_PCM_WDT_EN_LSB BIT(8) +#define REG_PCM_WDT_WAKE_LSB BIT(9) +#define REG_SSPM_APB_P2P_EN_LSB BIT(10) +#define REG_MCUPM_APB_P2P_EN_LSB BIT(11) +#define REG_RSV_APB_P2P_EN_LSB BIT(12) +#define RG_PCM_IRQ_MSK_LSB BIT(15) +#define PCM_CON1_PROJECT_CODE_LSB BIT(16) + +/* DDREN_DBC_CON (0x1C001000+0x888) */ +#define REG_DDREN_DBC_EN_LSB BIT(16) + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */ +#define SPM_WAKEUP_EVENT_MASK_BIT0 (1U << 0) +#define SPM_WAKEUP_EVENT_MASK_CSYSPWREQ_B (1U << 11) + +/* SPM_DVFS_MISC (0x10006000+0x4AC) */ +DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2) +DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4) + +/* --- SPM Flag Define --- */ +#define SPM_FLAG_DISABLE_VCORE_DVS BIT(8) +#define SPM_FLAG_DISABLE_DDR_DFS BIT(9) +#define SPM_FLAG_DISABLE_EMI_DFS BIT(10) +#define SPM_FLAG_DISABLE_BUS_DFS BIT(11) +#define SPM_FLAG_RUN_COMMON_SCENARIO BIT(19) + +/* SPM_EVENT_COUNTER_CLEAR (0x1C001000+0x8B8) */ +#define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(0) + +/* SYS_TIMER_CON (0x10006000+0x98C) */ +#define SYS_TIMER_START_EN_LSB BIT(0) + +/* MD32PCM_CFGREG_SW_RSTN (0x10006000+0xA00) */ +DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) + +/************************************** + * Config and Parameter + **************************************/ +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 +#define POWER_ON_VAL1_DEF 0x003ffe24 +#define SPM_WAKEUP_EVENT_MASK_DEF 0xefffffff +#define SPM_BUS_PROTECT_MASK_B_DEF 0xffffffff +#define SPM_BUS_PROTECT2_MASK_B_DEF 0xffffffff +#define MD32PCM_DMA0_CON_VAL 0x0003820e +#define MD32PCM_DMA0_START_VAL 0x00008000 +#define MD32PCM_CFGREG_SW_RSTN_RUN 0x1 +#define SPM_DVFS_LEVEL_DEF 0x00000001 +#define SPM_DVS_DFS_LEVEL_DEF 0x00010001 +#define SPM_RESOURCE_ACK_CON0_DEF 0xffffffff +#define SPM_RESOURCE_ACK_CON1_DEF 0xffffffff +#define SPM_RESOURCE_ACK_CON2_DEF 0xffffffff +#define SPM_RESOURCE_ACK_CON3_DEF 0xffffffff +#define ARMPLL_CLK_SEL_DEF 0x3ff +#define SPM_SYSCLK_SETTLE 0x60fe +#define SPM_INIT_DONE_US 20 + +/************************************** + * Definition and Declaration + **************************************/ +/* SPM_IRQ_MASK */ +#define ISRM_TWAM BIT(2) +#define ISRM_PCM_RETURN BIT(3) +#define ISRM_RET_IRQ0 BIT(8) +#define ISRM_RET_IRQ1 BIT(9) +#define ISRM_RET_IRQ2 BIT(10) +#define ISRM_RET_IRQ3 BIT(11) +#define ISRM_RET_IRQ4 BIT(12) +#define ISRM_RET_IRQ5 BIT(13) +#define ISRM_RET_IRQ6 BIT(14) +#define ISRM_RET_IRQ7 BIT(15) +#define ISRM_RET_IRQ8 BIT(16) +#define ISRM_RET_IRQ9 BIT(17) +#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \ + (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \ + (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \ + (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \ + (ISRM_RET_IRQ1)) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM BIT(2) +#define ISRS_PCM_RETURN BIT(3) +#define ISRC_TWAM ISRS_TWAM +#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* SPM_SWINT */ +#define PCM_SW_INT_ALL 0x3ff + +/* MD32PCM_STA1 define */ +#define R12_CSYSPWREQ_B BIT(24) + +#define SPM_INTERNAL_STATUS_HW_S1 BIT(0) +#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800 +#define SPM_ACK_CHK_3_CON_EN 0x110 +#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2 +#define SPM_ACK_CHK_3_CON_RESULT 0x8000 + +struct pwr_ctrl { + /* for SPM */ + u32 pcm_flags; + u32 pcm_flags_cust; + u32 pcm_flags_cust_set; + u32 pcm_flags_cust_clr; + u32 pcm_flags1; + u32 pcm_flags1_cust; + u32 pcm_flags1_cust_set; + u32 pcm_flags1_cust_clr; + u32 timer_val; + u32 timer_val_cust; + u32 timer_val_ramp_en; + u32 timer_val_ramp_en_sec; + u32 wake_src; + u32 wake_src_cust; + u32 wakelock_timer_val; + u8 wdt_disable; + /* Auto-gen Start */ + + /* SPM_CLK_CON */ + u8 reg_spm_lock_infra_dcm_lsb; + u8 reg_cxo32k_remove_en_lsb; + u8 reg_spm_leave_suspend_merge_mask_lsb; + u8 reg_sysclk0_src_mask_b_lsb; + u8 reg_sysclk1_src_mask_b_lsb; + u8 reg_sysclk2_src_mask_b_lsb; + + /* SPM_AP_STANDBY_CON */ + u8 reg_wfi_op; + u8 reg_wfi_type; + u8 reg_mp0_cputop_idle_mask; + u8 reg_mp1_cputop_idle_mask; + u8 reg_mcusys_idle_mask; + u8 reg_csyspwrup_req_mask_lsb; + u8 reg_wfi_af_sel; + u8 reg_cpu_sleep_wfi; + + /* SPM_SRC_REQ */ + u8 reg_spm_adsp_mailbox_req; + u8 reg_spm_apsrc_req; + u8 reg_spm_ddren_req; + u8 reg_spm_dvfs_req; + u8 reg_spm_emi_req; + u8 reg_spm_f26m_req; + u8 reg_spm_infra_req; + u8 reg_spm_pmic_req; + u8 reg_spm_scp_mailbox_req; + u8 reg_spm_sspm_mailbox_req; + u8 reg_spm_sw_mailbox_req; + u8 reg_spm_vcore_req; + u8 reg_spm_vrf18_req; + u8 adsp_mailbox_state; + u8 apsrc_state; + u8 ddren_state; + u8 dvfs_state; + u8 emi_state; + u8 f26m_state; + u8 infra_state; + u8 pmic_state; + u8 scp_mailbox_state; + u8 sspm_mailbox_state; + u8 sw_mailbox_state; + u8 vcore_state; + u8 vrf18_state; + + /* SPM_SRC_MASK_0 */ + u8 reg_apu_apsrc_req_mask_b; + u8 reg_apu_ddren_req_mask_b; + u8 reg_apu_emi_req_mask_b; + u8 reg_apu_infra_req_mask_b; + u8 reg_apu_pmic_req_mask_b; + u8 reg_apu_srcclkena_mask_b; + u8 reg_apu_vrf18_req_mask_b; + u8 reg_audio_dsp_apsrc_req_mask_b; + u8 reg_audio_dsp_ddren_req_mask_b; + u8 reg_audio_dsp_emi_req_mask_b; + u8 reg_audio_dsp_infra_req_mask_b; + u8 reg_audio_dsp_pmic_req_mask_b; + u8 reg_audio_dsp_srcclkena_mask_b; + u8 reg_audio_dsp_vcore_req_mask_b; + u8 reg_audio_dsp_vrf18_req_mask_b; + u8 reg_cam_apsrc_req_mask_b; + u8 reg_cam_ddren_req_mask_b; + u8 reg_cam_emi_req_mask_b; + u8 reg_cam_infra_req_mask_b; + u8 reg_cam_pmic_req_mask_b; + u8 reg_cam_srcclkena_mask_b; + u8 reg_cam_vrf18_req_mask_b; + + /* SPM_SRC_MASK_1 */ + u32 reg_ccif_apsrc_req_mask_b; + u32 reg_ccif_emi_req_mask_b; + u8 reg_vlpcfg_rsv0_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv0_ddren_req_mask_b; + u8 reg_vlpcfg_rsv0_emi_req_mask_b; + u8 reg_vlpcfg_rsv0_infra_req_mask_b; + u8 reg_vlpcfg_rsv0_pmic_req_mask_b; + u8 reg_vlpcfg_rsv0_srcclkena_mask_b; + u8 reg_vlpcfg_rsv0_vcore_req_mask_b; + u8 reg_vlpcfg_rsv0_vrf18_req_mask_b; + + /* SPM_SRC_MASK_2 */ + u32 reg_ccif_infra_req_mask_b; + u32 reg_ccif_pmic_req_mask_b; + u8 reg_vlpcfg_rsv1_apsrc_req_mask_b; + u8 reg_vlpcfg_rsv1_ddren_req_mask_b; + u8 reg_vlpcfg_rsv1_emi_req_mask_b; + u8 reg_vlpcfg_rsv1_infra_req_mask_b; + u8 reg_vlpcfg_rsv1_pmic_req_mask_b; + u8 reg_vlpcfg_rsv1_srcclkena_mask_b; + u8 reg_vlpcfg_rsv1_vcore_req_mask_b; + u8 reg_vlpcfg_rsv1_vrf18_req_mask_b; + + /* SPM_SRC_MASK_3 */ + u32 reg_ccif_srcclkena_mask_b; + u32 reg_ccif_vrf18_req_mask_b; + u8 reg_ccu_apsrc_req_mask_b; + u8 reg_ccu_ddren_req_mask_b; + u8 reg_ccu_emi_req_mask_b; + u8 reg_ccu_infra_req_mask_b; + u8 reg_ccu_pmic_req_mask_b; + u8 reg_ccu_srcclkena_mask_b; + u8 reg_ccu_vrf18_req_mask_b; + u8 reg_cg_check_apsrc_req_mask_b; + + /* SPM_SRC_MASK_4 */ + u8 reg_cg_check_ddren_req_mask_b; + u8 reg_cg_check_emi_req_mask_b; + u8 reg_cg_check_infra_req_mask_b; + u8 reg_cg_check_pmic_req_mask_b; + u8 reg_cg_check_srcclkena_mask_b; + u8 reg_cg_check_vcore_req_mask_b; + u8 reg_cg_check_vrf18_req_mask_b; + u8 reg_conn_apsrc_req_mask_b; + u8 reg_conn_ddren_req_mask_b; + u8 reg_conn_emi_req_mask_b; + u8 reg_conn_infra_req_mask_b; + u8 reg_conn_pmic_req_mask_b; + u8 reg_conn_srcclkena_mask_b; + u8 reg_conn_srcclkenb_mask_b; + u8 reg_conn_vcore_req_mask_b; + u8 reg_conn_vrf18_req_mask_b; + u8 reg_cpueb_apsrc_req_mask_b; + u8 reg_cpueb_ddren_req_mask_b; + u8 reg_cpueb_emi_req_mask_b; + u8 reg_cpueb_infra_req_mask_b; + u8 reg_cpueb_pmic_req_mask_b; + u8 reg_cpueb_srcclkena_mask_b; + u8 reg_cpueb_vrf18_req_mask_b; + u8 reg_disp0_apsrc_req_mask_b; + u8 reg_disp0_ddren_req_mask_b; + u8 reg_disp0_emi_req_mask_b; + u8 reg_disp0_infra_req_mask_b; + u8 reg_disp0_pmic_req_mask_b; + u8 reg_disp0_srcclkena_mask_b; + u8 reg_disp0_vrf18_req_mask_b; + u8 reg_disp1_apsrc_req_mask_b; + u8 reg_disp1_ddren_req_mask_b; + + /* SPM_SRC_MASK_5 */ + u8 reg_disp1_emi_req_mask_b; + u8 reg_disp1_infra_req_mask_b; + u8 reg_disp1_pmic_req_mask_b; + u8 reg_disp1_srcclkena_mask_b; + u8 reg_disp1_vrf18_req_mask_b; + u8 reg_dpm_apsrc_req_mask_b; + u8 reg_dpm_ddren_req_mask_b; + u8 reg_dpm_emi_req_mask_b; + u8 reg_dpm_infra_req_mask_b; + u8 reg_dpm_pmic_req_mask_b; + u8 reg_dpm_srcclkena_mask_b; + + /* SPM_SRC_MASK_6 */ + u8 reg_dpm_vcore_req_mask_b; + u8 reg_dpm_vrf18_req_mask_b; + u8 reg_dpmaif_apsrc_req_mask_b; + u8 reg_dpmaif_ddren_req_mask_b; + u8 reg_dpmaif_emi_req_mask_b; + u8 reg_dpmaif_infra_req_mask_b; + u8 reg_dpmaif_pmic_req_mask_b; + u8 reg_dpmaif_srcclkena_mask_b; + u8 reg_dpmaif_vrf18_req_mask_b; + u8 reg_dvfsrc_level_req_mask_b; + u8 reg_emisys_apsrc_req_mask_b; + u8 reg_emisys_ddren_req_mask_b; + u8 reg_emisys_emi_req_mask_b; + u8 reg_gce_apsrc_req_mask_b; + u8 reg_gce_ddren_req_mask_b; + u8 reg_gce_emi_req_mask_b; + u8 reg_gce_infra_req_mask_b; + u8 reg_gce_pmic_req_mask_b; + u8 reg_gce_srcclkena_mask_b; + u8 reg_gce_vrf18_req_mask_b; + u8 reg_gpueb_apsrc_req_mask_b; + u8 reg_gpueb_ddren_req_mask_b; + u8 reg_gpueb_emi_req_mask_b; + u8 reg_gpueb_infra_req_mask_b; + u8 reg_gpueb_pmic_req_mask_b; + u8 reg_gpueb_srcclkena_mask_b; + + /* SPM_SRC_MASK_7 */ + u8 reg_gpueb_vrf18_req_mask_b; + u8 reg_hwccf_apsrc_req_mask_b; + u8 reg_hwccf_ddren_req_mask_b; + u8 reg_hwccf_emi_req_mask_b; + u8 reg_hwccf_infra_req_mask_b; + u8 reg_hwccf_pmic_req_mask_b; + u8 reg_hwccf_srcclkena_mask_b; + u8 reg_hwccf_vcore_req_mask_b; + u8 reg_hwccf_vrf18_req_mask_b; + u8 reg_img_apsrc_req_mask_b; + u8 reg_img_ddren_req_mask_b; + u8 reg_img_emi_req_mask_b; + u8 reg_img_infra_req_mask_b; + u8 reg_img_pmic_req_mask_b; + u8 reg_img_srcclkena_mask_b; + u8 reg_img_vrf18_req_mask_b; + u8 reg_infrasys_apsrc_req_mask_b; + u8 reg_infrasys_ddren_req_mask_b; + u8 reg_infrasys_emi_req_mask_b; + u8 reg_infrasys_infra_req_mask_b; + u8 reg_infrasys_vrf18_req_mask_b; + u8 reg_ipic_infra_req_mask_b; + u8 reg_ipic_vrf18_req_mask_b; + u8 reg_mcu_apsrc_req_mask_b; + u8 reg_mcu_ddren_req_mask_b; + u8 reg_mcu_emi_req_mask_b; + u8 reg_mcu_infra_req_mask_b; + u8 reg_mcu_pmic_req_mask_b; + u8 reg_mcu_srcclkena_mask_b; + u8 reg_mcu_vrf18_req_mask_b; + u8 reg_md_apsrc_req_mask_b; + u8 reg_md_ddren_req_mask_b; + + /* SPM_SRC_MASK_8 */ + u8 reg_md_emi_req_mask_b; + u8 reg_md_infra_req_mask_b; + u8 reg_md_pmic_req_mask_b; + u8 reg_md_srcclkena_mask_b; + u8 reg_md_srcclkena1_mask_b; + u8 reg_md_vcore_req_mask_b; + u8 reg_md_vrf18_req_mask_b; + u8 reg_mm_proc_apsrc_req_mask_b; + u8 reg_mm_proc_ddren_req_mask_b; + u8 reg_mm_proc_emi_req_mask_b; + u8 reg_mm_proc_infra_req_mask_b; + u8 reg_mm_proc_pmic_req_mask_b; + u8 reg_mm_proc_srcclkena_mask_b; + u8 reg_mm_proc_vrf18_req_mask_b; + u8 reg_mml0_apsrc_req_mask_b; + u8 reg_mml0_ddren_req_mask_b; + u8 reg_mml0_emi_req_mask_b; + u8 reg_mml0_infra_req_mask_b; + u8 reg_mml0_pmic_req_mask_b; + u8 reg_mml0_srcclkena_mask_b; + u8 reg_mml0_vrf18_req_mask_b; + u8 reg_mml1_apsrc_req_mask_b; + u8 reg_mml1_ddren_req_mask_b; + u8 reg_mml1_emi_req_mask_b; + u8 reg_mml1_infra_req_mask_b; + u8 reg_mml1_pmic_req_mask_b; + u8 reg_mml1_srcclkena_mask_b; + u8 reg_mml1_vrf18_req_mask_b; + u8 reg_ovl0_apsrc_req_mask_b; + u8 reg_ovl0_ddren_req_mask_b; + u8 reg_ovl0_emi_req_mask_b; + u8 reg_ovl0_infra_req_mask_b; + + /* SPM_SRC_MASK_9 */ + u8 reg_ovl0_pmic_req_mask_b; + u8 reg_ovl0_srcclkena_mask_b; + u8 reg_ovl0_vrf18_req_mask_b; + u8 reg_ovl1_apsrc_req_mask_b; + u8 reg_ovl1_ddren_req_mask_b; + u8 reg_ovl1_emi_req_mask_b; + u8 reg_ovl1_infra_req_mask_b; + u8 reg_ovl1_pmic_req_mask_b; + u8 reg_ovl1_srcclkena_mask_b; + u8 reg_ovl1_vrf18_req_mask_b; + u8 reg_pcie0_apsrc_req_mask_b; + u8 reg_pcie0_ddren_req_mask_b; + u8 reg_pcie0_emi_req_mask_b; + u8 reg_pcie0_infra_req_mask_b; + u8 reg_pcie0_pmic_req_mask_b; + u8 reg_pcie0_srcclkena_mask_b; + u8 reg_pcie0_vcore_req_mask_b; + u8 reg_pcie0_vrf18_req_mask_b; + u8 reg_perisys_apsrc_req_mask_b; + u8 reg_perisys_ddren_req_mask_b; + u8 reg_perisys_emi_req_mask_b; + u8 reg_perisys_infra_req_mask_b; + u8 reg_perisys_pmic_req_mask_b; + u8 reg_perisys_srcclkena_mask_b; + u8 reg_perisys_vrf18_req_mask_b; + u8 reg_scp_apsrc_req_mask_b; + u8 reg_scp_ddren_req_mask_b; + u8 reg_scp_emi_req_mask_b; + u8 reg_scp_infra_req_mask_b; + u8 reg_scp_pmic_req_mask_b; + u8 reg_scp_srcclkena_mask_b; + u8 reg_scp_vcore_req_mask_b; + + /* SPM_SRC_MASK_10 */ + u8 reg_scp_vrf18_req_mask_b; + u8 reg_spu_hwrot_apsrc_req_mask_b; + u8 reg_spu_hwrot_ddren_req_mask_b; + u8 reg_spu_hwrot_emi_req_mask_b; + u8 reg_spu_hwrot_infra_req_mask_b; + u8 reg_spu_hwrot_pmic_req_mask_b; + u8 reg_spu_hwrot_srcclkena_mask_b; + u8 reg_spu_hwrot_vrf18_req_mask_b; + u8 reg_spu_ise_apsrc_req_mask_b; + u8 reg_spu_ise_ddren_req_mask_b; + u8 reg_spu_ise_emi_req_mask_b; + u8 reg_spu_ise_infra_req_mask_b; + u8 reg_spu_ise_pmic_req_mask_b; + u8 reg_spu_ise_srcclkena_mask_b; + u8 reg_spu_ise_vrf18_req_mask_b; + u8 reg_srcclkeni_infra_req_mask_b; + u8 reg_srcclkeni_pmic_req_mask_b; + u8 reg_srcclkeni_srcclkena_mask_b; + u8 reg_sspm_apsrc_req_mask_b; + u8 reg_sspm_ddren_req_mask_b; + u8 reg_sspm_emi_req_mask_b; + u8 reg_sspm_infra_req_mask_b; + u8 reg_sspm_pmic_req_mask_b; + u8 reg_sspm_srcclkena_mask_b; + u8 reg_sspm_vrf18_req_mask_b; + u8 reg_ssrsys_apsrc_req_mask_b; + u8 reg_ssrsys_ddren_req_mask_b; + u8 reg_ssrsys_emi_req_mask_b; + u8 reg_ssrsys_infra_req_mask_b; + + /* SPM_SRC_MASK_11 */ + u8 reg_ssrsys_pmic_req_mask_b; + u8 reg_ssrsys_srcclkena_mask_b; + u8 reg_ssrsys_vrf18_req_mask_b; + u8 reg_uart_hub_infra_req_mask_b; + u8 reg_uart_hub_pmic_req_mask_b; + u8 reg_uart_hub_srcclkena_mask_b; + u8 reg_uart_hub_vcore_req_mask_b; + u8 reg_uart_hub_vrf18_req_mask_b; + u8 reg_ufs_apsrc_req_mask_b; + u8 reg_ufs_ddren_req_mask_b; + u8 reg_ufs_emi_req_mask_b; + u8 reg_ufs_infra_req_mask_b; + u8 reg_ufs_pmic_req_mask_b; + u8 reg_ufs_srcclkena_mask_b; + u8 reg_ufs_vrf18_req_mask_b; + u8 reg_vdec_apsrc_req_mask_b; + u8 reg_vdec_ddren_req_mask_b; + u8 reg_vdec_emi_req_mask_b; + u8 reg_vdec_infra_req_mask_b; + u8 reg_vdec_pmic_req_mask_b; + u8 reg_vdec_srcclkena_mask_b; + u8 reg_vdec_vrf18_req_mask_b; + u8 reg_venc_apsrc_req_mask_b; + u8 reg_venc_ddren_req_mask_b; + u8 reg_venc_emi_req_mask_b; + u8 reg_venc_infra_req_mask_b; + u8 reg_venc_pmic_req_mask_b; + u8 reg_venc_srcclkena_mask_b; + u8 reg_venc_vrf18_req_mask_b; + + /* SPM_EVENT_CON_MISC */ + u8 reg_srcclken_fast_resp; + u8 reg_csyspwrup_ack_mask; + + /* SPM_WAKEUP_EVENT_MASK */ + u32 reg_wakeup_event_mask; + + /* SPM_WAKEUP_EVENT_EXT_MASK */ + u32 reg_ext_wakeup_event_mask; + + /* Auto-gen End */ +}; + +struct mtk_spm_regs { + u32 poweron_config_en; + u32 spm_power_on_val[4]; + u32 pcm_pwr_io_en; + u32 pcm_con0; + u32 pcm_con1; + u32 spm_sram_sleep_ctrl; + u32 spm_clk_con; + u32 spm_clk_settle; + u8 reserved0[20]; + u32 spm_sw_rst_con; + u32 spm_sw_rst_con_set; + u32 spm_sw_rst_con_clr; + u8 reserved1[4]; + u32 r_sec_read_mask; + u32 r_one_time_lock_l; + u32 r_one_time_lock_m; + u32 r_one_time_lock_h; + u8 reserved2[36]; + u32 sspm_clk_con; + u32 scp_clk_con; + u8 reserved3[4]; + u32 spm_swint; + u32 spm_swint_set; + u32 spm_swint_clr; + u8 reserved4[20]; + u32 spm_cpu_wakeup_event; + u32 spm_irq_mask; + u8 reserved5[72]; + u32 md32pcm_scu_ctrl[4]; + u32 md32pcm_scu_sta0; + u8 reserved6[20]; + u32 spm_irq_sta; + u8 reserved7[4]; + u32 md32pcm_wakeup_sta; + u32 md32pcm_event_sta; + u8 reserved8[8]; + u32 spm_wakeup_misc; + u8 reserved9[32]; + u32 spm_ck_sta; + u8 reserved10[40]; + u32 md32pcm_sta; + u32 md32pcm_pc; + u8 reserved11[104]; + u32 spm_ap_standby_con; + u32 cpu_wfi_en; + u32 cpu_wfi_en_set; + u32 cpu_wfi_en_clr; + u32 ext_int_wakeup_req; + u32 ext_int_wakeup_req_set; + u32 ext_int_wakeup_req_clr; + u32 mcusys_idle_sta; + u32 cpu_pwr_status; + u32 sw2spm_wakeup; + u32 sw2spm_wakeup_set; + u32 sw2spm_wakeup_clr; + u32 sw2spm_mailbox[4]; + u32 spm2sw_mailbox[4]; + u32 spm2mcupm_con; + u8 reserved12[12]; + u32 spm_mcusys_pwr_con; + u32 spm_cputop_pwr_con; + u32 spm_cpu_pwr_con[8]; + u32 spm_mcupm_spmc_con; + u8 reserved13[20]; + u32 spm_dpm_p2p_sta; + u32 spm_dpm_p2p_con; + u32 spm_dpm_intf_sta; + u32 spm_dpm_wb_con; + u32 pcm_apwdt_latch[20]; + u32 spm_pwrap_con; + u32 spm_pwrap_con_sta; + u32 spm_pmic_spmi_con; + u8 reserved14[4]; + u32 spm_pwrap_cmd[32]; + u32 dvfsrc_event_sta; + u32 spm_force_dvfs; + u32 spm_dvfs_sta; + u32 spm_dvs_dfs_level; + u32 spm_dvfs_level; + u32 spm_dvfs_opp; + u32 spm_ultra_req; + u32 spm_dvfs_con; + u32 spm_sramrc_con; + u32 spm_srclkenrc_con; + u32 spm_dpsw_con; + u32 spm_dpsw_vapu_iso_con; + u32 spm_dpsw_vmm_iso_con; + u32 spm_dpsw_vmd_iso_con; + u32 spm_dpsw_vmodem_iso_con; + u32 spm_dpsw_vcore_iso_con; + u8 reserved15[48]; + u32 ulposc_con; + u32 ap_mdsrc_req; + u32 spm2md_switch_ctrl; + u32 rc_spm_ctrl; + u32 spm2gpupm_con; + u32 spm2apu_con; + u32 spm2efuse_con; + u32 spm2dfd_con; + u32 rsv_pll_con; + u32 emi_slb_con; + u32 spm_suspend_flag_con; + u32 spm2pmsr_con; + u32 spm_topck_rtff_con; + u32 emi_shf_con; + u32 cirq_bypass_con; + u32 aoc_vcore_sram_con; + u32 spm2emi_pdn_ctrl; + u8 reserved16[28]; + u32 reg_module_sw_cg_ddren_req_mask[4]; + u32 reg_module_sw_cg_vrf18_req_mask[4]; + u32 reg_module_sw_cg_infra_req_mask[4]; + u32 reg_module_sw_cg_f26m_req_mask[4]; + u32 reg_module_sw_cg_vcore_req_mask[4]; + u32 reg_pwr_status_ddren_req_mask; + u32 reg_pwr_status_vrf18_req_mask; + u32 reg_pwr_status_infra_req_mask; + u32 reg_pwr_status_f26m_req_mask; + u32 reg_pwr_status_pmic_req_mask; + u32 reg_pwr_status_vcore_req_mask; + u32 reg_pwr_status_msb_ddren_req_mask; + u32 reg_pwr_status_msb_vrf18_req_mask; + u32 reg_pwr_status_msb_infra_req_mask; + u32 reg_pwr_status_msb_f26m_req_mask; + u32 reg_pwr_status_msb_pmic_req_mask; + u32 reg_pwr_status_msb_vcore_req_mask; + u32 reg_module_busy_ddren_req_mask; + u32 reg_module_busy_vrf18_req_mask; + u32 reg_module_busy_infra_req_mask; + u32 reg_module_busy_f26m_req_mask; + u32 reg_module_busy_pmic_req_mask; + u32 reg_module_busy_vcore_req_mask; + u8 reserved17[8]; + u32 sys_timer_con; + u32 sys_timer_value_l; + u32 sys_timer_value_h; + u32 sys_timer_start_l; + u32 sys_timer_start_h; + struct { + u32 latch_l; + u32 latch_h; + } sys_timer_latch[16]; + u32 pcm_timer_val; + u32 pcm_timer_out; + u32 spm_counter[3]; + u32 pcm_wdt_val; + u32 pcm_wdt_out; + u32 pcm_apwdt_latch_20[19]; + u8 reserved18[4]; + u32 spm_sw_flag_0; + u32 spm_sw_debug_0; + u32 spm_sw_flag_1; + u32 spm_sw_debug_1; + u32 spm_sw_rsv[9]; + u32 spm_bk_wake_event; + u32 spm_bk_vtcxo_dur; + u32 spm_bk_wake_misc; + u32 spm_bk_pcm_timer; + u8 reserved19[12]; + u32 spm_rsv_con_0; + u32 spm_rsv_con_1; + u32 spm_rsv_sta_0; + u32 spm_rsv_sta_1; + u32 spm_spare_con; + u32 spm_spare_con_set; + u32 spm_spare_con_clr; + u32 spm_cross_wake_m00_req; + u32 spm_cross_wake_m01_req; + u32 spm_cross_wake_m02_req; + u32 spm_cross_wake_m03_req; + u32 scp_vcore_level; + u32 spm_ddren_ack_sel_con; + u32 spm_sw_flag_2; + u32 spm_sw_debug_2; + u32 spm_dv_con_0; + u32 spm_dv_con_1; + u8 reserved20[8]; + u32 spm_sema_m[8]; + u32 spm2adsp_mailbox; + u32 adsp2spm_mailbox; + u32 spm2pmcu_mailbox[4]; + u32 pmcu2spm_mailbox[4]; + u32 spm2scp_mailbox; + u32 scp2spm_mailbox; + u32 scp_aov_bus_con; + u32 vcore_rtff_ctrl_mask; + u32 vcore_rtff_ctrl_mask_set; + u32 vcore_rtff_ctrl_mask_clr; + u32 spm_sram_srclkeno_mask; + u8 reserved21[256]; + u32 spm_wakeup_sta; + u32 spm_wakeup_ext_sta; + u32 spm_wakeup_event_mask; + u32 spm_wakeup_event_ext_mask; + u32 spm_wakeup_event_sens; + u32 spm_wakeup_event_clear; + u32 spm_src_req; + u32 spm_src_mask[12]; + u32 spm_req_sta[12]; + u32 spm_ipc_wakeup_req; + u32 ipc_wakeup_req_mask_sta; + u32 spm_event_con_misc; + u32 ddren_dbc_con; + u32 spm_resource_ack_con[2]; + u32 spm_resource_ack_mask[9]; + u32 spm_event_counter_clear; + u32 spm_vcore_event_count_sta; + u32 spm_pmic_event_count_sta; + u32 spm_srcclkena_event_count_sta; + u32 spm_infra_event_count_sta; + u32 spm_vrf18_event_count_sta; + u32 spm_emi_event_count_sta; + u32 spm_apsrc_event_count_sta; + u32 spm_ddren_event_count_sta; + u32 pcm_wdt_latch[39]; + u32 pcm_wdt_latch_spare[10]; + u32 dramc_gating_err_latch[6]; + u32 dramc_gating_err_latch_spare_0; + u32 spm_debug_con; + u32 spm_ack_chk_con_0; + u32 spm_ack_chk_sel_0; + u32 spm_ack_chk_timer_0; + u32 spm_ack_chk_sta_0; + u32 spm_ack_chk_con_1; + u32 spm_ack_chk_sel_1; + u32 spm_ack_chk_timer_1; + u32 spm_ack_chk_sta_1; + u32 spm_ack_chk_con_2; + u32 spm_ack_chk_sel_2; + u32 spm_ack_chk_timer_2; + u32 spm_ack_chk_sta_2; + u32 spm_ack_chk_con_3; + u32 spm_ack_chk_sel_3; + u32 spm_ack_chk_timer_3; + u32 spm_ack_chk_sta_3; + u32 md32pcm_cfgreg_sw_rstn; + u8 reserved22[508]; + u32 md32pcm_dma0_src; + u32 md32pcm_dma0_dst; + u32 md32pcm_dma0_wppt; + u32 md32pcm_dma0_wpto; + u32 md32pcm_dma0_count; + u32 md32pcm_dma0_con; + u32 md32pcm_dma0_start; + u8 reserved23[8]; + u32 md32pcm_dma0_rlct; + u8 reserved24[276]; + u32 md32pcm_intc_irq_raw_sta; + u8 reserved25[192]; + u32 md1_pwr_con; + u32 conn_pwr_con; + u32 ifr_pwr_con; + u32 peri_pwr_con; + u32 peri_usb0_pwr_con; + u32 ufs0_pwr_con; + u32 ufs0_phy_pwr_con; + u32 pextp_mac0_pwr_con; + u32 pextp_mac1_pwr_con; + u32 pextp_phy0_pwr_con; + u32 pextp_phy1_pwr_con; + u32 audio_pwr_con; + u32 adsp_core1_pwr_con; + u32 adsp_top_pwr_con; + u32 adsp_infra_pwr_con; + u32 adsp_ao_pwr_con; + u32 isp_traw_pwr_con; + u32 isp_dip1_pwr_con; + u32 isp_main_pwr_con; + u32 isp_vcore_pwr_con; + u32 vde0_pwr_con; + u32 vde1_pwr_con; + u32 vde_vcore0_pwr_con; + u32 vde_vcore1_pwr_con; + u32 ven0_pwr_con; + u32 ven1_pwr_con; + u32 ven2_pwr_con; + u32 cam_mraw_pwr_con; + u32 cam_suba_pwr_con; + u32 cam_subb_pwr_con; + u32 cam_subc_pwr_con; + u32 cam_main_pwr_con; + u32 cam_vcore_pwr_con; + u32 cam_ccu_pwr_con; + u32 cam_ccu_ao_pwr_con; + u32 disp_vcore_pwr_con; + u32 mml0_pwr_con; + u32 mml1_pwr_con; + u32 dis0_pwr_con; + u32 dis1_pwr_con; + u32 ovl0_pwr_con; + u32 ovl1_pwr_con; + u32 mm_infra_pwr_con; + u32 mm_proc_pwr_con; + u32 dp_tx_pwr_con; + u32 scp_pwr_con; + u32 dpyd0_pwr_con; + u32 dpyd1_pwr_con; + u32 dpyd2_pwr_con; + u32 dpyd3_pwr_con; + u32 dpya0_pwr_con; + u32 dpya1_pwr_con; + u32 dpya2_pwr_con; + u32 dpya3_pwr_con; + u32 dpm0_pwr_con; + u32 dpm1_pwr_con; + u32 dpm2_pwr_con; + u32 dpm3_pwr_con; + u32 emi0_pwr_con; + u32 emi1_pwr_con; + u32 cpueb_pwr_con; + u32 csi_rx_pwr_con; + u32 ssrsys_pwr_con; + u32 spu_ise_pwr_con; + u32 spu_hwrot_pwr_con; + u32 mfg0_pwr_con; + u32 unipro_pdn_sram_con; + u32 ufs_sleep_sram_con; + u32 ccu_sleep_sram_con; + u32 mm_infra_ao_pdn_sram_con; + u32 infra_sleep_sram_con; + u32 peri_sleep_sram_con; + u32 nth_emi_slb_sram_con; + u32 nth_emi_slb_sram_ack; + u32 sth_emi_slb_sram_con; + u32 sth_emi_slb_sram_ack; + u32 ssr_sleep_sram_con; + u32 spu_ise_sleep_sram_con; + u32 spu_hwrot_sleep_sram_con; + u32 infra_hre_sram_con; + u32 emi_hre_sram_con; + u32 mm_hre_sram_con; + u32 mml_hre_sram_con; + u32 adsp_hre_sram_con; + u32 efuse_sram_con; + u32 spm_sram_con; + u32 sspm_sram_con; + u32 cpu_buck_iso_con; + u32 md_buck_iso_con; + u32 soc_buck_iso_con; + u32 soc_buck_iso_con_set; + u32 soc_buck_iso_con_clr; + u32 pwr_status; + u32 pwr_status_2nd; + u32 pwr_status_msb; + u32 pwr_status_msb_2nd; + u32 xpu_pwr_status; + u32 xpu_pwr_status_2nd; + u32 dfd_soc_pwr_latch; + u8 reserved26[68]; + u32 spm_twam_con; + u32 spm_twam_window_len; + u32 spm_twam_idle_sel; + u32 spm_twam_last_sta[4]; + u32 spm_twam_curr_sta[4]; + u32 spm_twam_timer_out; +}; + +check_member(mtk_spm_regs, spm_wakeup_misc, 0x140); +check_member(mtk_spm_regs, spm_mcupm_spmc_con, 0x288); +check_member(mtk_spm_regs, spm_dpm_wb_con, 0x2ac); +check_member(mtk_spm_regs, spm_pwrap_cmd[31], 0x38c); +check_member(mtk_spm_regs, spm_dpsw_con, 0x3b8); +check_member(mtk_spm_regs, spm2emi_pdn_ctrl, 0x440); +check_member(mtk_spm_regs, pcm_wdt_out, 0x5ac); +check_member(mtk_spm_regs, spm_sram_srclkeno_mask, 0x6fc); +check_member(mtk_spm_regs, spm_vcore_event_count_sta, 0x8bc); +check_member(mtk_spm_regs, spm_ack_chk_sta_3, 0x9fc); +check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xa00); +check_member(mtk_spm_regs, md32pcm_dma0_src, 0xc00); +check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xc24); +check_member(mtk_spm_regs, soc_buck_iso_con, 0xf64); +check_member(mtk_spm_regs, spm_twam_timer_out, 0xffc); + +static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; + +static const struct power_domain_data disp[] = { + /* TODO: add disp power domains */ +}; + +static const struct power_domain_data audio[] = { + /* TODO: add audio power domains */ +}; + +#endif /* SOC_MEDIATEK_MT8196_SPM_H */ diff --git a/src/soc/mediatek/mt8196/pmif_clk.c b/src/soc/mediatek/mt8196/pmif_clk.c new file mode 100644 index 0000000..2c59dc5 --- /dev/null +++ b/src/soc/mediatek/mt8196/pmif_clk.c @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <assert.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/pmif.h> +#include <soc/pmif_clk_common.h> +#include <soc/pmif_spmi.h> +#include <soc/pmif_sw.h> +#include <soc/spm.h> + +#define OUTSEL_AD_OSC_CK_VAL 0x8 + +/* VLP_TOPCKGEN, VLP_CLK_CFG_UPDATE */ +DEFINE_BIT(PWRAP_ULPOSC_CK_UPDATE, 4) +DEFINE_BIT(SPMI_M_TIA_32K_CK_UPDATE, 5) +DEFINE_BIT(SPMI_M_MST_CK_UPDATE, 9) + +/* VLP_TOPCKGEN, VLP_CLK_CFG_0 */ +DEFINE_BITFIELD(CLK_SCP_SEL, 3, 0) + +/* VLP_TOPCKGEN, VLP_CLK_CFG_1 */ +DEFINE_BITFIELD(CLK_PWRAP_ULPOSC_SEL, 1, 0) +DEFINE_BIT(CLK_PWRAP_ULPOSC_INV, 4) +DEFINE_BIT(PDN_PWRAP_ULPOSC, 7) +DEFINE_BITFIELD(CLK_SPMI_M_TIA_32K_SEL, 10, 8) +DEFINE_BIT(CLK_SPMI_M_TIA_32K_INV, 12) +DEFINE_BIT(PDN_SPMI_M_TIA_32K, 15) + +/* VLP_TOPCKGEN, VLP_CLK_CFG_2 */ +DEFINE_BITFIELD(CLK_SPMI_M_MST_SEL, 9, 8) +DEFINE_BIT(CLK_SPMI_M_MST_INV, 12) +DEFINE_BIT(PDN_SPMI_M_MST, 15) + +/* VLP_TOPCKGEN, ULPOSC1_CON0 */ +DEFINE_BITFIELD(ULPOSC1_CON0, 31, 0) +DEFINE_BITFIELD(OSC1_CALI_LOW, 6, 0) +DEFINE_BITFIELD(OSC1_CALI_HIGHT, 8, 7) +DEFINE_BITFIELD(OSC1_CALI, 8, 0) +DEFINE_BITFIELD(OSC1_IBAND, 15, 9) +DEFINE_BITFIELD(OSC1_FBAND, 20, 16) +DEFINE_BITFIELD(OSC1_DIV, 26, 21) +DEFINE_BIT(OSC1_CP_EN, 27) + +/* VLP_TOPCKGEN, ULPOSC1_CON1 */ +DEFINE_BITFIELD(ULPOSC1_CON1, 31, 0) +DEFINE_BITFIELD(OSC1_32KCALI, 7, 0) +DEFINE_BITFIELD(OSC1_LJ, 15, 8) +DEFINE_BITFIELD(OSC1_RSV, 23, 16) +DEFINE_BITFIELD(OSC1_MOD, 25, 24) +DEFINE_BITFIELD(OSC_OUTSEL, 30, 27) +DEFINE_BIT(OSC1_DIV2_EN, 26) + +/* VLP_TOPCKGEN, ULPOSC1_CON2 */ +DEFINE_BITFIELD(ULPOSC1_CON2, 31, 0) +DEFINE_BITFIELD(OSC1_BIAS, 7, 0) +DEFINE_BITFIELD(OSC_BUF, 15, 8) + +/* TOPRGU, WDT_VLP_SWSYSRST0 */ +DEFINE_BITFIELD(PMIF_RST_B, 11, 10) +DEFINE_BITFIELD(PMIFSPMI_RST_B, 13, 12) +DEFINE_BITFIELD(UNLOCK_KEY, 31, 24) +DEFINE_BIT(TIA_GRST_B, 0) + +/* SPM, POWERON_CONFIG_EN */ +DEFINE_BIT(BCLK_CG_EN, 0) +DEFINE_BITFIELD(PROJECT_CODE, 31, 16) + +/* SPM, ULPOSC_CON */ +DEFINE_BIT(ULPOSC_EN, 0) +DEFINE_BIT(ULPOSC_CG_EN, 2) + +static void pmif_ulposc_config(void) +{ + /* ULPOSC1_CON0 */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[0], OSC1_CP_EN, 0, OSC1_DIV, 0x34, + OSC1_FBAND, 0xA, OSC1_IBAND, 0x53, OSC1_CALI, 0x140); + + /* ULPOSC1_CON1 */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[1], OSC_OUTSEL, 0x2, OSC1_DIV2_EN, 0, + OSC1_MOD, 0, OSC1_RSV, 0, OSC1_LJ, 0xA, OSC1_32KCALI, 0); + + /* ULPOSC1_CON2 */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[2], OSC1_BIAS, 0x4A, OSC_BUF, 0x48); + + printk(BIOS_INFO, "%s: ULPOSC1_CON0: 0x%x, ULPOSC1_CON1: 0x%x, ULPOSC1_CON2: 0x%x\n", + __func__, + READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[0], ULPOSC1_CON0), + READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[1], ULPOSC1_CON1), + READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[2], ULPOSC1_CON2)); +} + +static void pmif_pre_ulposc_cali_bubble(u32 target_clk) +{ + unsigned int cali_val = 0; + unsigned int abs_distance; + unsigned int min_abs_distance = 0xFFFFFFFF; + int min_cali_vali = 0x2; + int64_t freq = 0; + + /* Calculate absolute delta to 260Mhz of 4 different calibration values */ + /* Try RG_OSC1_CALI[8:7] = 0x0 ~ 0x3 */ + for (cali_val = 0; cali_val < 4; cali_val++) { + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[0], OSC1_CALI_HIGHT, cali_val); + freq = (int64_t)(mt_get_vlpck_freq(FREQ_METER_VLP_AD_OSC_SYNC_CK)); + abs_distance = ABS(freq - (target_clk * 1000)); + + /* Memorize the minimum absolute delta and its calibration value */ + if (abs_distance < min_abs_distance) { + min_abs_distance = abs_distance; + min_cali_vali = cali_val; + } + } + + printk(BIOS_INFO, "ULPOSC1 pre-cali for high bits, select cali_val = %#x\n", + min_cali_vali); + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[0], OSC1_CALI_HIGHT, min_cali_vali); +} + +static int pmif_set_osc_outsel(u32 outsel) +{ + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[1], OSC_OUTSEL, outsel); + + if ((READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[1], OSC_OUTSEL)) != outsel) + return -1; + else + return 0; +} + +u32 pmif_get_ulposc_freq_mhz(u32 cali_val) +{ + u32 result = 0; + + /* set calibration value */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_ulposc1_con[0], OSC1_CALI_LOW, cali_val); + udelay(50); + result = mt_get_vlpck_freq(FREQ_METER_VLP_AD_OSC_SYNC_CK); + + return result / 1000; +} + +static int pmif_check_vlpck_freq(u32 target_clk) +{ + u32 freq_mhz; + freq_mhz = mt_get_vlpck_freq(FREQ_METER_VLP_AD_OSC_CK) / 1000; + + /* check if calibrated value is in the range of target value +- 2% */ + if (freq_mhz > (target_clk * (1000 - CAL_MIS_RATE) / 1000) && + freq_mhz < (target_clk * (1000 + CAL_MIS_RATE) / 1000)) + return 0; + + printk(BIOS_ERR, "ULPOSC1 K fail: %dM, PLL_ULPOSC1_CON0/1/2 0x%x 0x%x 0x%x\n", + freq_mhz, + READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[0], ULPOSC1_CON0), + READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[1], ULPOSC1_CON1), + READ32_BITFIELD(&mtk_vlpsys->vlp_ulposc1_con[2], ULPOSC1_CON2)); + return -1; +} + +static void pmif_turn_onoff_ulposc(bool enable) +{ + if (enable) { + /* turn on ulposc */ + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 1); + udelay(100); + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_CG_EN, 1); + } else { + SET32_BITFIELDS(&mtk_spm->ulposc_con, ULPOSC_EN, 0, ULPOSC_CG_EN, 0); + } +} + +static int pmif_init_ulposc(void) +{ + int ret = 0; + /* calibrate ULPOSC1 */ + pmif_ulposc_config(); + /* enable spm swinf */ + SET32_BITFIELDS(&mtk_spm->poweron_config_en, BCLK_CG_EN, 1, + PROJECT_CODE, 0xb16); + pmif_turn_onoff_ulposc(true); + pmif_pre_ulposc_cali_bubble(PMIF_ULPOSC_TARGET_FREQ_MHZ); + ret = pmif_ulposc_cali(PMIF_ULPOSC_TARGET_FREQ_MHZ); + pmif_turn_onoff_ulposc(false); + ret |= pmif_set_osc_outsel(OUTSEL_AD_OSC_CK_VAL); + pmif_turn_onoff_ulposc(true); + ret |= pmif_check_vlpck_freq(PMIF_VLPCK_TARGET_FREQ_MHZ); + + return ret; +} + +int pmif_clk_init(void) +{ + if (pmif_init_ulposc()) + return E_NODEV; + + /* for TIA + * [15]: pdn_spmi_m_tia [12]: clk_spmi_m_tia_inv + * [10:8]: clk_spmi_m_tia_sel: + * 0x0: tck_26m_mx9_ck, 0x1: clkrtc, 0x2: osc_d20, + * 0x3: osc_d14, 0x4: osc_d10 + */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[1].cfg, PDN_SPMI_M_TIA_32K, 0, + CLK_SPMI_M_TIA_32K_INV, 0, CLK_SPMI_M_TIA_32K_SEL, 0x2); + /* for pmif_m/p + * [7]: pdn_pwrap_ulposc [4]: clk_pwrap_ulposc_inv + * [1:0]: clk_pwrap_ulposc_sel: + * 0x0: tck_26m_mx9_ck, 0x1: osc_d20, 0x2: osc_d14, 0x3: osc_d10, + */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[1].cfg, PDN_PWRAP_ULPOSC, 0, + CLK_PWRAP_ULPOSC_INV, 0, CLK_PWRAP_ULPOSC_SEL, 0x1); + /* for spmi_mst_m/p + * [15]: pdn_spmi_m_mst [12]: clk_spmi_m_mst_inv + * [9:8]: clk_spmi_m_mst_sel: + * 0x0: tck_26m_mx9_ck, 0x1: osc_d20, 0x2: osc_d14, 0x3: osc_d10, + */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[2].cfg, PDN_SPMI_M_MST, 0, + CLK_SPMI_M_MST_INV, 0, CLK_SPMI_M_MST_SEL, 0x1); + + /* [9]: spmi_m_mst_ck_update ,[5]: spmi_m_tia_32k_ck_update */ + /* [4]: pwrap_ulposc_ck_update */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg_update[0], SPMI_M_MST_CK_UPDATE, 0x1, + SPMI_M_TIA_32K_CK_UPDATE, 0x1, PWRAP_ULPOSC_CK_UPDATE, 0x1); + + /* pmif use ULPOSC1 clock */ + /* [3]: pmicw_spmi_p_tmr_ck_26M_sel + * [2]: pmicw_spmi_m_tmr_ck_26M_sel + * [1]: spmi_mst_m_p_ulposc_32k_sel + * [0]: pmicw_spmi_m_ck_26M_sel + */ + /* Enable spmi support for ULPOSC off feature, bit[1] always set to 1 */ + SET32_BITFIELDS(&mtk_vlpsys->vlp_clk_cfg[0].set, CLK_SCP_SEL, 0x2); + /* No extra tia clk src mux, default use ULPOSC1 clock + * need to confirm with DE every platform + */ + + /* toggle SPMI-M & SPMI-P sw reset */ + /* [10]: pmifspi_m_rst_b [11]: pmifspi_p_rst_b*/ + /* [12]: pmifspi_m_rst_b [13]: pmifspi_p_rst_b*/ + SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88, PMIFSPMI_RST_B, 0x3, + PMIF_RST_B, 0x3); + SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst0, UNLOCK_KEY, 0x88); + + /* [0]: tia_grst_b */ + SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst1, UNLOCK_KEY, 0x88, TIA_GRST_B, 0x1); + SET32_BITFIELDS(&mtk_rug->wdt_vlp_swsysrst1, UNLOCK_KEY, 0x88); + + printk(BIOS_INFO, "%s: done\n", __func__); + + return 0; +} diff --git a/src/soc/mediatek/mt8196/pmif_init.c b/src/soc/mediatek/mt8196/pmif_init.c new file mode 100644 index 0000000..0fda348 --- /dev/null +++ b/src/soc/mediatek/mt8196/pmif_init.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/pmif.h> +#include <soc/pmif_common.h> +#include <soc/pmif_spi.h> +#include <soc/pmif_spmi.h> +#include <soc/pmif_sw.h> +#include <soc/spmi.h> +#include <timer.h> + +const struct pmif pmif_spmi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPMI_P_BASE, + .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN_P, + .mstid = SPMI_MASTER_0, + .pmifid = PMIF_SPMI, + .write = pmif_spmi_write, + .read = pmif_spmi_read, + .write_field = pmif_spmi_write_field, + .read_field = pmif_spmi_read_field, + .is_pmif_init_done = pmif_check_init_done, + }, { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPMI_BASE, + .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN, + .mstid = SPMI_MASTER_1, + .pmifid = PMIF_SPMI, + .write = pmif_spmi_write, + .read = pmif_spmi_read, + .write_field = pmif_spmi_write_field, + .read_field = pmif_spmi_read_field, + .is_pmif_init_done = pmif_check_init_done, + }, { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPMI_P_BASE, + .ch = (struct chan_regs *)PMIF_SPMI_AP_CHAN_P, + .mstid = SPMI_MASTER_2, + .pmifid = PMIF_SPMI, + .write = pmif_spmi_write, + .read = pmif_spmi_read, + .write_field = pmif_spmi_write_field, + .read_field = pmif_spmi_read_field, + .is_pmif_init_done = pmif_check_init_done, + }, +}; + +const size_t pmif_spmi_arb_count = ARRAY_SIZE(pmif_spmi_arb); + +const struct pmif pmif_spi_arb[] = { + { + .mtk_pmif = (struct mtk_pmif_regs *)PMIF_SPI_BASE, + .ch = (struct chan_regs *)PMIF_SPI_AP_CHAN, + .pmifid = PMIF_SPI, + .write = pmif_spi_write, + .read = pmif_spi_read, + .write_field = pmif_spi_write_field, + .read_field = pmif_spi_read_field, + .is_pmif_init_done = pmif_check_init_done, + }, +}; + +const size_t pmif_spi_arb_count = ARRAY_SIZE(pmif_spi_arb); + +int mtk_pmif_init(void) +{ + int ret; + + ret = pmif_clk_init(); + + if (!ret) { + ret = pmif_spmi_init(get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1)); + printk(BIOS_INFO, "%s: SPMI_MASTER_1, %d\n", __func__, ret); + } + + if (!ret) { + ret = pmif_spmi_init(get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0)); + printk(BIOS_INFO, "%s: SPMI_MASTER_0, %d\n", __func__, ret); + } + + return ret; +} diff --git a/src/soc/mediatek/mt8196/pmif_spmi.c b/src/soc/mediatek/mt8196/pmif_spmi.c new file mode 100644 index 0000000..91f9038 --- /dev/null +++ b/src/soc/mediatek/mt8196/pmif_spmi.c @@ -0,0 +1,350 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <console/console.h> +#include <device/mmio.h> +#include <gpio.h> +#include <soc/addressmap.h> +#include <soc/pll.h> +#include <soc/pmif.h> +#include <soc/pmif_spmi.h> +#include <soc/spmi.h> + +#define SPMI_RCS_CTRL_BASE 0x140084 + +/* TOPCKGEN, CLK_CFG_17 */ +DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8) +DEFINE_BIT(CLK_SPMI_MST_INT, 12) +DEFINE_BIT(PDN_SPMI_MST, 15) + +/* TOPCKGEN, CLK_CFG_UPDATE2 */ +DEFINE_BIT(SPMI_MST_CK_UPDATE, 5) + +/* SPMI_MST, SPMI_SAMPL_CTRL */ +DEFINE_BIT(SAMPL_CK_POL, 0) +DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1) +DEFINE_BITFIELD(SAMPL_CK_DLY_ARB, 6, 4) + +/* PMIF, SPI_MODE_CTRL */ +DEFINE_BIT(VLD_SRCLK_EN_CTRL, 5) +DEFINE_BIT(SPI_MODE_CTRL_PMIF_RDY, 9) +DEFINE_BIT(SPI_MODE_CTRL_SRCLK_EN, 10) +DEFINE_BIT(SPI_MODE_CTRL_SRVOL_EN, 11) + +/* PMIF, SLEEP_PROTECTION_CTRL */ +DEFINE_BIT(SPM_SLEEP_REQ_SEL, 0) +DEFINE_BIT(SCP_SLEEP_REQ_SEL, 9) + +const struct spmi_device spmi_dev[] = { + { + .slvid = SPMI_SLAVE_4, /* MT6363 */ + .mstid = SPMI_MASTER_1, + .type = MAIN_PMIC, + .type_id = MAIN_PMIC_ID, + .hwcid_addr = 0x09, + .hwcid_val = 0x63, + .hwcid_mask = 0xF0, + }, + { + .slvid = SPMI_SLAVE_9, /* MT6685 */ + .mstid = SPMI_MASTER_1, + .type = CLOCK_PMIC, + .type_id = CLOCK_PMIC_ID, + .hwcid_addr = 0x09, + .hwcid_val = 0x85, + .hwcid_mask = 0xF0, + }, + { + .slvid = SPMI_SLAVE_5, /* MT6373 */ + .mstid = SPMI_MASTER_1, + .type = SECOND_PMIC, + .type_id = SECOND_PMIC_ID, + .hwcid_addr = 0x09, + .hwcid_val = 0x73, + .hwcid_mask = 0xF0, + }, + { + .slvid = SPMI_SLAVE_6, /* MT6316 */ + .mstid = SPMI_MASTER_0, + .type = SUB_PMIC, + .type_id = SUB_PMIC_ID, + .hwcid_addr = 0x209, + .hwcid_val = 0x16, + .hwcid_mask = 0xf0, + }, + { + .slvid = SPMI_SLAVE_7, /* MT6316 */ + .mstid = SPMI_MASTER_0, + .type = SUB_PMIC, + .type_id = SUB_PMIC_ID, + .hwcid_addr = 0x209, + .hwcid_val = 0x16, + .hwcid_mask = 0xf0, + }, + { + .slvid = SPMI_SLAVE_8, /* MT6316 */ + .mstid = SPMI_MASTER_0, + .type = SUB_PMIC, + .type_id = SUB_PMIC_ID, + .hwcid_addr = 0x209, + .hwcid_val = 0x16, + .hwcid_mask = 0xf0, + }, + { + .slvid = SPMI_SLAVE_15, /* MT6316 */ + .mstid = SPMI_MASTER_0, + .type = SUB_PMIC, + .type_id = SUB_PMIC_ID, + .hwcid_addr = 0x209, + .hwcid_val = 0x16, + .hwcid_mask = 0xf0, + }, +}; + +static const uint32_t chan_perm[2][4] = { + [SPMI_MASTER_0] = { 0x8888888A, 0x88888888, 0x88888888, 0x88888888 }, + [SPMI_MASTER_1] = { 0x888888AA, 0x88888888, 0x88888888, 0x88888888 }, +}; + +static const uint32_t lat_limit[2][23] = { + [SPMI_MASTER_0] = { 0x3e6, 0x3e6, 0x9, 0x9, 0x3e6, 0x3e6, 0x3e6, 0x3e6, 0x9, 0x3e6, + 0x0, 0x3e6, 0x9, 0x0, 0x0, 0x3e6, 0x3e6, 0x3e6, 0x3e6, 0x0, + 0x3e6, 0x0, 0x3e6 }, + [SPMI_MASTER_1] = { 0x3e6, 0x0, 0x3e6, 0x3e6, 0x26, 0x37, 0x3e6, 0x10, 0x9, 0x23, + 0x0, 0x39, 0x9, 0x0, 0x0, 0x12, 0x3e6, 0x3e6, 0x3e6, 0x0, + 0x1e, 0x0, 0x3e6 }, +}; + +const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev); + +static struct mtk_spmi_mst_reg *get_mst_reg(struct pmif *arb) +{ + if (arb->mstid == SPMI_MASTER_1) + return mtk_spmi_mst; + else if (arb->mstid == SPMI_MASTER_0 || arb->mstid == SPMI_MASTER_2) + return mtk_spmi_mst_p; + else + return NULL; +} + +static int pmif_spmi_config_master(struct pmif *arb) +{ + struct mtk_spmi_mst_reg *reg = get_mst_reg(arb); + if (!reg) { + printk(BIOS_ERR, "%s: get_mst_reg get null pointer\n", __func__); + return -1; + } + + write32(&reg->mst_req_en, 1); + write32(&reg->grp_id_en, 0xC00); + /* enable multi-master and rcs support */ + write32(&reg->rcs_ctrl, SPMI_RCS_CTRL_BASE + arb->mstid); + printk(BIOS_INFO, "%s: mstid=%d done\n", __func__, arb->mstid); + return 0; +} + +void pmif_spmi_config(struct pmif *arb) +{ + _Static_assert(ARRAY_SIZE(chan_perm[0]) == ARRAY_SIZE(arb->mtk_pmif->inf_cmd_per), + "Inconsistent array size for chan_perm and inf_cmd_per"); + const uint32_t *perm = chan_perm[arb->mstid % 2]; + /* + * all cmd permission for per channel + * [0]: Command 0 Permitted + * [1]: Command 1 Permitted + * [2]: Command 2 Permitted + * [3]: Command 3 Permitted + */ + /* PER_0[8:0]: CH0 or CH1 for MD DVFS HW, backward compatible for swrgo */ + for (int i = 0; i < ARRAY_SIZE(arb->mtk_pmif->inf_cmd_per); i++) + write32(&arb->mtk_pmif->inf_cmd_per[i], perm[i]); +} + +void pmif_spmi_iocfg(void) +{ + /* SPMI_M 10mA */ + gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA); + gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA); + /* SPMI_P 14mA */ + gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA); + gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA); + printk(BIOS_INFO, "%s done\n", __func__); +} + +static int spmi_read_check(struct pmif *arb, const struct spmi_device *dev) +{ + u32 rdata = 0; + + arb->read(arb, dev->slvid, dev->hwcid_addr, &rdata); + if ((rdata & dev->hwcid_mask) != (dev->hwcid_val & dev->hwcid_mask)) { + printk(BIOS_WARNING, "%s next, slvid:%d rdata = 0x%x\n", + __func__, dev->slvid, rdata); + return -E_NODEV; + } + + printk(BIOS_INFO, "%s next, slvid:%d rdata = 0x%x.\n", __func__, dev->slvid, rdata); + return 0; +} + +static int spmi_cali_rd_clock_polarity(struct pmif *arb, const struct spmi_device *dev) +{ + size_t i; + bool success = false; + const struct cali cali_data[] = { + {SPMI_CK_DLY_1T, SPMI_CK_POL_NEG}, + {SPMI_CK_DLY_1T, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_POS}, + {SPMI_CK_NO_DLY, SPMI_CK_POL_NEG}, + {SPMI_CK_DLY_2T, SPMI_CK_POL_POS}, + {SPMI_CK_DLY_2T, SPMI_CK_POL_NEG}, + }; + + struct mtk_spmi_mst_reg *reg = get_mst_reg(arb); + if (!reg) { + printk(BIOS_ERR, "%s: get_mst_reg get null pointer\n", __func__); + return -1; + } + + /* Indicate sampling clock polarity, 1: Positive 0: Negative */ + for (i = 0; i < ARRAY_SIZE(cali_data); i++) { + SET32_BITFIELDS(&reg->mst_sampl, SAMPL_CK_DLY, cali_data[i].dly, + SAMPL_CK_POL, cali_data[i].pol); + SET32_BITFIELDS(&reg->mst_sampl, SAMPL_CK_DLY_ARB, cali_data[i].dly + 1); + printk(BIOS_DEBUG, "dly:%d, pol:%d, sampl:0x%x\n", + cali_data[i].dly, cali_data[i].pol, read32(&reg->mst_sampl)); + if (spmi_read_check(arb, dev) == 0) { + success = true; + break; + } + } + + if (!success) + die("ERROR - calibration fail for SPMI clk"); + + return 0; +} + +static int spmi_config_slave(struct pmif *arb, const struct spmi_device *dev) +{ + u32 wdata; + + /* set RG_RCS_ADDR=slave id */ + wdata = dev->slvid; + arb->write(arb, dev->slvid, 0x419, wdata); /* rcs_slvid_addr: 0x419 */ + + /* set RG_RCS_ENABLE=1, RG_RCS_ID=Master ID */ + wdata = 0x5 | (dev->mstid << 4); + arb->write(arb, dev->slvid, 0x418, wdata); /* rcs_slvid_en: 0x418 */ + + return 0; +} + +static int spmi_mst_init(struct pmif *arb) +{ + int i; + + if (!arb) { + printk(BIOS_ERR, "%s: null pointer for pmif dev\n", __func__); + return -E_INVAL; + } + + if (!CONFIG(PMIF_SPMI_IOCFG_DEFAULT_SETTING)) + pmif_spmi_iocfg(); + + if (pmif_spmi_config_master(arb)) + return -1; + + for (i = 0; i < spmi_dev_cnt; i++) { + if ((arb->mstid % 2) == spmi_dev[i].mstid) { + spmi_cali_rd_clock_polarity(arb, &spmi_dev[i]); /* spmi_cali */ + spmi_config_slave(arb, &spmi_dev[i]); + } + } + + return 0; +} + +static void pmif_spmi_force_normal_mode(struct pmif *arb) +{ + /* listen srclken_0 only for entering normal or sleep mode */ + SET32_BITFIELDS(&arb->mtk_pmif->spi_mode_ctrl, + VLD_SRCLK_EN_CTRL, 0, + SPI_MODE_CTRL_PMIF_RDY, 1, + SPI_MODE_CTRL_SRCLK_EN, 0, + SPI_MODE_CTRL_SRVOL_EN, 0); + + /* disable spm/scp sleep request */ + SET32_BITFIELDS(&arb->mtk_pmif->sleep_protection_ctrl, SPM_SLEEP_REQ_SEL, 1, + SCP_SLEEP_REQ_SEL, 1); + printk(BIOS_INFO, "%s done\n", __func__); +} + +static void pmif_spmi_enable_swinf(struct pmif *arb) +{ + write32(&arb->mtk_pmif->inf_en, PMIF_SPMI_SW_CHAN); + write32(&arb->mtk_pmif->arb_en, PMIF_SPMI_SW_CHAN); + printk(BIOS_INFO, "%s done\n", __func__); +} + +static void pmif_spmi_enable_cmd_issue(struct pmif *arb, bool en) +{ + /* Enable cmdIssue */ + write32(&arb->mtk_pmif->cmdissue_en, en); + printk(BIOS_INFO, "%s done\n", __func__); +} + +static void pmif_spmi_enable(struct pmif *arb) +{ + _Static_assert(ARRAY_SIZE(lat_limit[0]) == ARRAY_SIZE(arb->mtk_pmif->lat_limit), + "Inconsistent array size for lat_limit and arb->mtk_pmif->lat_limit"); + const uint32_t *lat_limit_value = lat_limit[arb->mstid % 2]; + u32 pmif_spmi_inf; + int i; + + if (arb->mstid % 2) + pmif_spmi_inf = PMIF_SPMI_INF; + else + pmif_spmi_inf = PMIF_SPMI_INF_P; + + pmif_spmi_config(arb); + + /* set bytecnt max limitation, 0:1 byte, 1:2 bytes */ + for (i = 0; i < ARRAY_SIZE(arb->mtk_pmif->inf_max_bytecnt_per); i++) + write32(&arb->mtk_pmif->inf_max_bytecnt_per[i], 0x11111111); + + /* Add latency limitation for all channels, method 2 */ + /* Latency unit = (LAT_UNIT_SEL + 1)T of TMR_CK, LAT_UNIT_SEL=25;Lat unit=26T ~=1us */ + write32(&arb->mtk_pmif->lat_cnter_ctrl, 0x32); + if (arb->mstid % 2) + write32(&arb->mtk_pmif->lat_cnter_en, pmif_spmi_inf); + for (i = 0; i < ARRAY_SIZE(arb->mtk_pmif->lat_limit); i++) + write32(&arb->mtk_pmif->lat_limit[i], lat_limit_value[i]); + write32(&arb->mtk_pmif->lat_limit_loading, pmif_spmi_inf); + + /* Disable STAUPD_ITEM_EN */ + write32(&arb->mtk_pmif->staupd_ctrl, 0x1030000); + + write32(&arb->mtk_pmif->inf_en, pmif_spmi_inf); + write32(&arb->mtk_pmif->arb_en, pmif_spmi_inf); + write32(&arb->mtk_pmif->timer_ctrl, 0x3); + write32(&arb->mtk_pmif->init_done, 1); + printk(BIOS_INFO, "%s init done: 0x%x\n", __func__, read32(&arb->mtk_pmif->init_done)); +} + +int pmif_spmi_init(struct pmif *arb) +{ + if (arb->is_pmif_init_done(arb) != 0) { + pmif_spmi_force_normal_mode(arb); + pmif_spmi_enable_swinf(arb); + pmif_spmi_enable_cmd_issue(arb, true); + pmif_spmi_enable(arb); + if (arb->is_pmif_init_done(arb)) + return -E_NODEV; + } + + if (spmi_mst_init(arb)) { + printk(BIOS_ERR, "[%s] failed to init SPMI master\n", __func__); + return -E_NODEV; + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232015f45735ee5278b09d0352410617a1565177 Gerrit-Change-Number: 85126 Gerrit-PatchSet: 23 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Yidi Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... soc/mediatek/mt8196: Add mtcmos init support Add mtcmos init code and APIs for controlling power domain. TEST=build pass and driver init ok BUG=b:317009620 Signed-off-by: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84497 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/memlayout.ld A src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h A src/soc/mediatek/mt8196/mtcmos.c 5 files changed, 839 insertions(+), 1 deletion(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b3a0834..0410129 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -16,6 +16,7 @@ bootblock-y += ../common/early_init.c bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += ../common/mmu_operations.c +bootblock-y += mtcmos.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 365a4e0..a864bff 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -6,6 +6,7 @@ #include <soc/lastbus_v2.h> #include <soc/mmu_operations.h> #include <soc/pll.h> +#include <soc/spm_mtcmos.h> #include <soc/wdt.h> void bootblock_soc_init(void) @@ -15,6 +16,8 @@ lastbus_init(); mtk_wdt_init(); mt_pll_init(); + mtcmos_init(); mt_pll_post_init(); + mtcmos_post_init(); early_init_clear(); } diff --git a/src/soc/mediatek/mt8196/include/soc/memlayout.ld b/src/soc/mediatek/mt8196/include/soc/memlayout.ld index 1529a69..83e80b6 100644 --- a/src/soc/mediatek/mt8196/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8196/include/soc/memlayout.ld @@ -46,7 +46,7 @@ DRAM_INIT_CODE(0x02000000, 600K) #else /* The beginning 4K of SRAM_L2C is reserved for BOOTROM until BOOTBLOCK is started. */ - BOOTBLOCK(0x02001000, 78K) + BOOTBLOCK(0x02001000, 85K) #endif OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x02096000, 272K) PRERAM_CBFS_CACHE(0x020DA000, 48K) diff --git a/src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h b/src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h new file mode 100644 index 0000000..5cad800c9 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/spm_mtcmos.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8196_SPM_MTCMOS_H +#define SOC_MEDIATEK_MT8196_SPM_MTCMOS_H + +#include <commonlib/list.h> + +enum mtcmos_state { + MTCMOS_POWER_DOWN, + MTCMOS_POWER_ON, +}; + +enum mtcmos_id { + MTCMOS_ID_SSUSB_DP_PHY_P0, + MTCMOS_ID_SSUSB_P0, + MTCMOS_ID_SSUSB_P1, + MTCMOS_ID_SSUSB_P23, + MTCMOS_ID_SSUSB_PHY_P2, + MTCMOS_ID_UFS0_SHUTDOWN, + MTCMOS_ID_UFS0_PHY, + MTCMOS_ID_PEXTP_MAC0, + MTCMOS_ID_PEXTP_MAC1, + MTCMOS_ID_PEXTP_MAC2, + MTCMOS_ID_PEXTP_PHY0, + MTCMOS_ID_PEXTP_PHY1, + MTCMOS_ID_PEXTP_PHY2, + MTCMOS_ID_AUDIO, + MTCMOS_ID_ADSP_TOP_SHUTDOWN, + MTCMOS_ID_ADSP_INFRA, + MTCMOS_ID_ADSP_AO, + MTCMOS_ID_MM_PROC_SHUTDOWN, + MTCMOS_ID_SSRSYS, + MTCMOS_ID_DISP_VCORE, + MTCMOS_ID_DIS0_SHUTDOWN, + MTCMOS_ID_DIS1_SHUTDOWN, + MTCMOS_ID_OVL0_SHUTDOWN, + MTCMOS_ID_OVL1_SHUTDOWN, + MTCMOS_ID_DISP_EDPTX_SHUTDOWN, + MTCMOS_ID_DISP_DPTX_SHUTDOWN, + MTCMOS_ID_MM_INFRA0, + MTCMOS_ID_MM_INFRA1, + MTCMOS_ID_MM_INFRA_AO, + MTCMOS_ID_DSI_PHY0, + MTCMOS_ID_DSI_PHY1, + MTCMOS_ID_DSI_PHY2, + MTCMOS_ID_NUM, +}; + +struct mtcmos_cb { + int (*pre_on)(void); + int (*pre_off)(void); + int (*post_on)(void); + int (*post_off)(void); +}; + +int mtcmos_cb_register(enum mtcmos_id id, const struct mtcmos_cb *cb); +void mtcmos_ctrl(enum mtcmos_id id, enum mtcmos_state state); +void mtcmos_init(void); +void mtcmos_post_init(void); + +#endif diff --git a/src/soc/mediatek/mt8196/mtcmos.c b/src/soc/mediatek/mt8196/mtcmos.c new file mode 100644 index 0000000..367e74b --- /dev/null +++ b/src/soc/mediatek/mt8196/mtcmos.c @@ -0,0 +1,773 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file is created based on MTCMOS_SW_NOTE.xlsx + */ + +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/mtcmos.h> +#include <soc/pll.h> +#include <soc/spm_mtcmos.h> +#include <timer.h> + +#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->caps & (_x)) + +#define POWERON_CONFIG_EN ((void *)(SPM_BASE + 0x0000)) + +#define SPM_PROJECT_CODE 0xB16 + +#define SET_BUS_PROTECT 1 +#define RELEASE_BUS_PROTECT 0 + +#define WAIT_VOTE_TIMEOUT 20000 + +#define SPM_PBUS_BUS_PROTECT_EN_SET ((void *)(SPM_PBUS_BASE + 0x00DC)) +#define SPM_PBUS_BUS_PROTECT_EN_CLR ((void *)(SPM_PBUS_BASE + 0x00E0)) +#define SPM_PBUS_BUS_PROTECT_RDY_STA ((void *)(SPM_PBUS_BASE + 0x0208)) +#define SPM_PBUS_BUS_MSB_PROTECT_EN_SET ((void *)(SPM_PBUS_BASE + 0x00E8)) +#define SPM_PBUS_BUS_MSB_PROTECT_EN_CLR ((void *)(SPM_PBUS_BASE + 0x00EC)) +#define SPM_PBUS_BUS_MSB_PROTECT_RDY_STA ((void *)(SPM_PBUS_BASE + 0x020C)) + +#define MM_BUCK_ISO_CON_CLR ((void *)(MMPC_BASE + 0x00C8)) +#define DISP_AO_PWR_CON ((void *)(MMPC_BASE + 0x00E8)) +#define MMPC_BUS_PROTECT_EN_1_CLR ((void *)(MMPC_BASE + 0x0188)) + +#define MMVOTE_MTCMOS_0_SET ((void *)(MMVOTE_BASE + 0x0218)) +#define MMVOTE_MTCMOS_0_CLR ((void *)(MMVOTE_BASE + 0x021C)) +#define MMVOTE_MTCMOS_0_DONE ((void *)(MMVOTE_BASE + 0x141C)) +#define MMVOTE_MTCMOS_0_PM_ACK ((void *)(MMVOTE_BASE + 0x5514)) +#define MMVOTE_MTCMOS_1_SET ((void *)(MMVOTE_BASE + 0x0220)) +#define MMVOTE_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x0224)) +#define MMVOTE_MTCMOS_1_DONE ((void *)(MMVOTE_BASE + 0x142C)) +#define MMVOTE_MTCMOS_1_PM_ACK ((void *)(MMVOTE_BASE + 0x5518)) +#define MMINFRA_MTCMOS_1_SET ((void *)(MMVOTE_BASE + 0x43220)) +#define MMINFRA_MTCMOS_1_CLR ((void *)(MMVOTE_BASE + 0x43224)) + +#define DISP_VDISP_AO_CONFIG_CG 0x3E800108 +#define DISP_DPC_DISP0_MTCMOS_CFG 0x3E8F0500 +#define DISP_DPC_DISP1_MTCMOS_CFG 0x3E8F0580 +#define DISP_DPC_OVL0_MTCMOS_CFG 0x3E8F0600 +#define DISP_DPC_OVL1_MTCMOS_CFG 0x3E8F0680 +#define DISP_DPC_MML0_MTCMOS_CFG 0x3E8F0B00 +#define DISP_DPC_MML1_MTCMOS_CFG 0x3E8F0700 +#define DISP_DPC_EDP_MTCMOS_CFG 0x3E8F0C00 +#define DISP_DPC_EPTX_MTCMOS_CFG 0x3E8F0D00 + +#define MMINFRA0_VOTE_BIT 1 +#define MMINFRA1_VOTE_BIT 2 +#define MMINFRA_AO_VOTE_BIT 3 +#define DSI_PHY0_VOTE_BIT 7 +#define DSI_PHY1_VOTE_BIT 8 +#define DSI_PHY2_VOTE_BIT 9 +#define DISP_VCORE_VOTE_BIT 24 +#define DISP0_VOTE_BIT 25 +#define DISP1_VOTE_BIT 26 +#define OVL0_VOTE_BIT 27 +#define OVL1_VOTE_BIT 28 +#define DISP_EDPTX_VOTE_BIT 29 +#define DISP_DPTX_VOTE_BIT 30 + +#define MTK_SCPD_SRAM_ISO BIT(0) +#define MTK_SCPD_SRAM_SLP BIT(2) +#define MTK_SCPD_RTFF_DELAY BIT(6) +#define MTK_SCPD_NO_SRAM BIT(8) + +#define PWR_RST_B BIT(0) +#define PWR_ISO BIT(1) +#define PWR_ON BIT(2) +#define PWR_ON_2ND BIT(3) +#define PWR_CLK_DIS BIT(4) +#define SRAM_CKISO BIT(5) +#define SRAM_ISOINT_B BIT(6) +#define SRAM_PDN BIT(8) +#define SRAM_SLP BIT(9) +#define SRAM_PDN_ACK BIT(12) +#define SRAM_SLP_ACK BIT(13) +#define PWR_RTFF_SAVE BIT(24) +#define PWR_RTFF_SAVE_FLAG BIT(27) +#define PWR_ACK BIT(30) +#define PWR_ACK_2ND BIT(31) + +#define ACK_DELAY_US 10 +#define ACK_DELAY_TIMES 10000 + +#define ADSP_AO_PROT_STEP1_SHIFT 23 +#define ADSP_INFRA_PROT_STEP1_SHIFT 22 +#define ADSP_TOP_PROT_STEP1_SHIFT 21 +#define AUDIO_PROT_STEP1_SHIFT 19 +#define MM_PROC_PROT_STEP1_SHIFT 24 +#define PEXTP_MAC0_PROT_STEP1_SHIFT 13 +#define PEXTP_MAC1_PROT_STEP1_SHIFT 14 +#define PEXTP_MAC2_PROT_STEP1_SHIFT 15 +#define PEXTP_PHY0_PROT_STEP1_SHIFT 16 +#define PEXTP_PHY1_PROT_STEP1_SHIFT 17 +#define PEXTP_PHY2_PROT_STEP1_SHIFT 18 +#define SSRSYS_PROT_STEP1_SHIFT 10 +#define SSUSB_DP_PHY_P0_PROT_STEP1_SHIFT 6 +#define SSUSB_P0_PROT_STEP1_SHIFT 7 +#define SSUSB_P1_PROT_STEP1_SHIFT 8 +#define SSUSB_P23_PROT_STEP1_SHIFT 9 +#define SSUSB_PHY_P2_PROT_STEP1_SHIFT 10 +#define UFS0_PHY_PROT_STEP1_SHIFT 12 +#define UFS0_PROT_STEP1_SHIFT 11 + +struct mtcmos_bus_prot { + u32 *bp_en_set; + u32 *bp_en_clr; + u32 *bp_rdy; + u8 bit; +}; + +struct mtcmos_data { + const struct mtcmos_bus_prot *bp_table; + u32 *ctl_addr; + u32 caps; + u32 bp_num; + const struct mtcmos_cb *cb; +}; + +struct mtcmos_vote_data { + u32 *set_addr; + u32 *clr_addr; + u32 *done_addr; + u32 *ack_addr; + u8 vote_bit; + const struct mtcmos_cb *cb; +}; + +static const struct mtcmos_bus_prot ssusb_dp_phy_p0_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_DP_PHY_P0_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ssusb_p0_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_P0_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ssusb_p1_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_P1_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ssusb_p23_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_P23_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ssusb_phy_p2_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, SSUSB_PHY_P2_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ufs0_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, UFS0_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ufs0_phy_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, UFS0_PHY_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot pextp_mac0_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_MAC0_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot pextp_mac1_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_MAC1_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot pextp_mac2_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_MAC2_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot pextp_phy0_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_PHY0_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot pextp_phy1_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_PHY1_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot pextp_phy2_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, PEXTP_PHY2_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot audio_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, AUDIO_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot adsp_top_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, ADSP_TOP_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot adsp_infra_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, ADSP_INFRA_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot adsp_ao_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, ADSP_AO_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot mm_proc_bp[] = { + { SPM_PBUS_BUS_PROTECT_EN_SET, SPM_PBUS_BUS_PROTECT_EN_CLR, + SPM_PBUS_BUS_PROTECT_RDY_STA, MM_PROC_PROT_STEP1_SHIFT }, +}; + +static const struct mtcmos_bus_prot ssrsys_bp[] = { + { SPM_PBUS_BUS_MSB_PROTECT_EN_SET, SPM_PBUS_BUS_MSB_PROTECT_EN_CLR, + SPM_PBUS_BUS_MSB_PROTECT_RDY_STA, SSRSYS_PROT_STEP1_SHIFT }, +}; + +static struct mtcmos_data mds[MTCMOS_ID_NUM] = { + [MTCMOS_ID_SSUSB_DP_PHY_P0] = { + ssusb_dp_phy_p0_bp, &mtk_spm_mtcmos->ssusb_dp_phy_p0_pwr_con, + MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_SSUSB_P0] = { + ssusb_p0_bp, &mtk_spm_mtcmos->ssusb_p0_pwr_con, 0, 1 + }, + [MTCMOS_ID_SSUSB_P1] = { + ssusb_p1_bp, &mtk_spm_mtcmos->ssusb_p1_pwr_con, 0, 1 + }, + [MTCMOS_ID_SSUSB_P23] = { + ssusb_p23_bp, &mtk_spm_mtcmos->ssusb_p23_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_SSUSB_PHY_P2] = { + ssusb_phy_p2_bp, &mtk_spm_mtcmos->ssusb_phy_p2_pwr_con, 0, 1 + }, + [MTCMOS_ID_UFS0_SHUTDOWN] = { + ufs0_bp, &mtk_spm_mtcmos->ufs0_pwr_con, 0, 1 + }, + [MTCMOS_ID_UFS0_PHY] = { + ufs0_phy_bp, &mtk_spm_mtcmos->ufs0_phy_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_PEXTP_MAC0] = { + pextp_mac0_bp, &mtk_spm_mtcmos->pextp_mac0_pwr_con, 0, 1 + }, + [MTCMOS_ID_PEXTP_MAC1] = { + pextp_mac1_bp, &mtk_spm_mtcmos->pextp_mac1_pwr_con, 0, 1 + }, + [MTCMOS_ID_PEXTP_MAC2] = { + pextp_mac2_bp, &mtk_spm_mtcmos->pextp_mac2_pwr_con, 0, 1 + }, + [MTCMOS_ID_PEXTP_PHY0] = { + pextp_phy0_bp, &mtk_spm_mtcmos->pextp_phy0_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_PEXTP_PHY1] = { + pextp_phy1_bp, &mtk_spm_mtcmos->pextp_phy1_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_PEXTP_PHY2] = { + pextp_phy2_bp, &mtk_spm_mtcmos->pextp_phy2_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_AUDIO] = { + audio_bp, &mtk_spm_mtcmos->audio_pwr_con, 0, 1 + }, + [MTCMOS_ID_ADSP_TOP_SHUTDOWN] = { + adsp_top_bp, &mtk_spm_mtcmos->adsp_top_pwr_con, 0, 1 + }, + [MTCMOS_ID_ADSP_INFRA] = { + adsp_infra_bp, &mtk_spm_mtcmos->adsp_infra_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_ADSP_AO] = { + adsp_ao_bp, &mtk_spm_mtcmos->adsp_ao_pwr_con, MTK_SCPD_NO_SRAM, 1 + }, + [MTCMOS_ID_MM_PROC_SHUTDOWN] = { + mm_proc_bp, &mtk_spm_mtcmos->mm_proc_pwr_con, 0, 1 + }, + [MTCMOS_ID_SSRSYS] = { + ssrsys_bp, &mtk_spm_mtcmos->ssrsys_pwr_con, 0, 1 + }, +}; + +static struct mtcmos_vote_data vote_mds[MTCMOS_ID_NUM] = { + [MTCMOS_ID_DISP_VCORE] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, DISP_VCORE_VOTE_BIT + }, + [MTCMOS_ID_DIS0_SHUTDOWN] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, DISP0_VOTE_BIT + }, + [MTCMOS_ID_DIS1_SHUTDOWN] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, DISP1_VOTE_BIT + }, + [MTCMOS_ID_OVL0_SHUTDOWN] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, OVL0_VOTE_BIT + }, + [MTCMOS_ID_OVL1_SHUTDOWN] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, OVL1_VOTE_BIT + }, + [MTCMOS_ID_DISP_EDPTX_SHUTDOWN] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, DISP_EDPTX_VOTE_BIT + }, + [MTCMOS_ID_DISP_DPTX_SHUTDOWN] = { + MMVOTE_MTCMOS_0_SET, MMVOTE_MTCMOS_0_CLR, MMVOTE_MTCMOS_0_DONE, + MMVOTE_MTCMOS_0_PM_ACK, DISP_DPTX_VOTE_BIT + }, + [MTCMOS_ID_MM_INFRA0] = { + MMINFRA_MTCMOS_1_SET, MMINFRA_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE, + MMVOTE_MTCMOS_1_PM_ACK, MMINFRA0_VOTE_BIT + }, + [MTCMOS_ID_MM_INFRA1] = { + MMINFRA_MTCMOS_1_SET, MMINFRA_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE, + MMVOTE_MTCMOS_1_PM_ACK, MMINFRA1_VOTE_BIT + }, + [MTCMOS_ID_MM_INFRA_AO] = { + MMINFRA_MTCMOS_1_SET, MMINFRA_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE, + MMVOTE_MTCMOS_1_PM_ACK, MMINFRA_AO_VOTE_BIT + }, + [MTCMOS_ID_DSI_PHY0] = { + MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE, + MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY0_VOTE_BIT + }, + [MTCMOS_ID_DSI_PHY1] = { + MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE, + MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY1_VOTE_BIT + }, + [MTCMOS_ID_DSI_PHY2] = { + MMVOTE_MTCMOS_1_SET, MMVOTE_MTCMOS_1_CLR, MMVOTE_MTCMOS_1_DONE, + MMVOTE_MTCMOS_1_PM_ACK, DSI_PHY2_VOTE_BIT + }, +}; + +int mtcmos_cb_register(enum mtcmos_id id, const struct mtcmos_cb *cb) +{ + if (id >= MTCMOS_ID_NUM) { + printk(BIOS_ERR, "id(%d) is invalid\n", id); + return -1; + } + + if (id <= MTCMOS_ID_SSRSYS) + mds[id].cb = cb; + else + vote_mds[id].cb = cb; + + return 0; +} + +static int mtcmos_wait_for_state(u32 *reg, u32 mask, bool onoff) +{ + u32 expect = onoff ? mask : 0; + + if (!retry(ACK_DELAY_TIMES, (read32(reg) & mask) == expect, udelay(ACK_DELAY_US))) { + printk(BIOS_ERR, "%s(%p, %#x, %d) reg_val=%#x timeout\n", + __func__, reg, mask, onoff, read32(reg)); + return -1; + } + + return 0; +} + +static int mtcmos_bus_prot_ctrl(const struct mtcmos_bus_prot *bp_table, bool set) +{ + u32 *ctrl_addr; + u32 mask = BIT(bp_table->bit); + + if (set) + ctrl_addr = bp_table->bp_en_set; + else + ctrl_addr = bp_table->bp_en_clr; + + write32(ctrl_addr, mask); + + if (set) + return mtcmos_wait_for_state(bp_table->bp_rdy, mask, set); + + return 0; +} + +static int mtcmos_setclr_bus_prot(const struct mtcmos_bus_prot *bp_table, u32 bp_num, bool set) +{ + int step_idx; + int ret; + int i; + + for (i = 0; i < bp_num; i++) { + step_idx = set ? i : bp_num - 1 - i; + ret = mtcmos_bus_prot_ctrl(&bp_table[step_idx], set); + if (ret) { + printk(BIOS_ERR, "mtcmos_bus_prot_ctrl set fail: %d\n", ret); + mtcmos_bus_prot_ctrl(&bp_table[step_idx], !set); + return ret; + } + } + + return 0; +} + +static int mtcmos_sram_on(enum mtcmos_id id, const struct mtcmos_data *md) +{ + u32 *ctl_addr = md->ctl_addr; + int ret = 0; + + if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_SLP)) { + setbits32(ctl_addr, SRAM_SLP); + ret = mtcmos_wait_for_state(ctl_addr, SRAM_SLP_ACK, true); + } else { + clrbits32(ctl_addr, SRAM_PDN); + ret = mtcmos_wait_for_state(ctl_addr, SRAM_PDN_ACK, false); + } + if (ret) + return ret; + + if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_ISO)) { + setbits32(ctl_addr, SRAM_ISOINT_B); + udelay(1); + clrbits32(ctl_addr, SRAM_CKISO); + } + + return 0; +} + +static int mtcmos_sram_off(enum mtcmos_id id, const struct mtcmos_data *md) +{ + u32 *ctl_addr = md->ctl_addr; + + if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_ISO)) { + setbits32(ctl_addr, SRAM_CKISO); + clrbits32(ctl_addr, SRAM_ISOINT_B); + udelay(1); + } + + if (MTK_SCPD_CAPS(md, MTK_SCPD_SRAM_SLP)) { + clrbits32(ctl_addr, SRAM_SLP); + return mtcmos_wait_for_state(ctl_addr, SRAM_SLP_ACK, false); + } else { + setbits32(ctl_addr, SRAM_PDN); + return mtcmos_wait_for_state(ctl_addr, SRAM_PDN_ACK, true); + } +} + +static int mtcmos_onoff(enum mtcmos_id id, enum mtcmos_state state) +{ + const struct mtcmos_data *md = &mds[id]; + u32 *ctl_addr = md->ctl_addr; + int ret = 0; + + if (state == MTCMOS_POWER_DOWN) { + if (md->cb && md->cb->pre_off) { + ret = md->cb->pre_off(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call pre_off fail(%d)\n", id, ret); + return ret; + } + } + + ret = mtcmos_setclr_bus_prot(md->bp_table, md->bp_num, SET_BUS_PROTECT); + if (ret) + return ret; + + if (!MTK_SCPD_CAPS(md, MTK_SCPD_NO_SRAM)) { + ret = mtcmos_sram_off(id, md); + if (ret) + return ret; + } + + setbits32(ctl_addr, PWR_ISO); + setbits32(ctl_addr, PWR_CLK_DIS); + clrbits32(ctl_addr, PWR_RST_B); + clrbits32(ctl_addr, PWR_ON); + ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK, state); + if (ret) + return ret; + + clrbits32(ctl_addr, PWR_ON_2ND); + ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK_2ND, state); + if (ret) + return ret; + + if (md->cb && md->cb->post_off) { + ret = md->cb->post_off(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call post_off fail(%d)\n", id, ret); + return ret; + } + } + } else { + if (md->cb && md->cb->pre_on) { + ret = md->cb->pre_on(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call pre_on fail(%d)\n", id, ret); + return ret; + } + } + + setbits32(ctl_addr, PWR_ON); + ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK, state); + if (ret) + return ret; + udelay(50); + + setbits32(ctl_addr, PWR_ON_2ND); + ret = mtcmos_wait_for_state(ctl_addr, PWR_ACK_2ND, state); + if (ret) + return ret; + + clrbits32(ctl_addr, PWR_CLK_DIS); + clrbits32(ctl_addr, PWR_ISO); + + if (MTK_SCPD_CAPS(md, MTK_SCPD_RTFF_DELAY)) + udelay(10); + + setbits32(ctl_addr, PWR_RST_B); + if (!MTK_SCPD_CAPS(md, MTK_SCPD_NO_SRAM)) { + ret = mtcmos_sram_on(id, md); + if (ret) + return ret; + } + + ret = mtcmos_setclr_bus_prot(md->bp_table, md->bp_num, RELEASE_BUS_PROTECT); + if (ret) + return ret; + + if (md->cb && md->cb->post_on) { + ret = md->cb->post_on(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call post_on fail(%d)\n", id, ret); + return ret; + } + } + } + + return 0; +} + +static int mtcmos_vote_onoff(enum mtcmos_id id, enum mtcmos_state state) +{ + const struct mtcmos_vote_data *md = &vote_mds[id]; + u32 vote_bit = BIT(md->vote_bit); + int ret = 0; + + if (state == MTCMOS_POWER_DOWN) { + if (md->cb && md->cb->pre_off) { + ret = md->cb->pre_off(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call pre_off fail(%d)\n", id, ret); + return ret; + } + } + + write32(md->clr_addr, vote_bit); + if (!wait_us(WAIT_VOTE_TIMEOUT, ((read32(md->done_addr) & vote_bit) != 0 && + (read32(md->ack_addr) & vote_bit) == vote_bit))) { + printk(BIOS_ERR, "mtcmos_vote disable %d timeout\n", id); + return -1; + } + + if (md->cb && md->cb->post_off) { + ret = md->cb->post_off(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call post_off fail(%d)\n", id, ret); + return ret; + } + } + } else { + if (md->cb && md->cb->pre_on) { + ret = md->cb->pre_on(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call pre_on fail(%d)\n", id, ret); + return ret; + } + } + + write32(md->set_addr, vote_bit); + if (!wait_us(WAIT_VOTE_TIMEOUT, ((read32(md->done_addr) & vote_bit) != 0 && + (read32(md->ack_addr) & vote_bit) == vote_bit))) { + printk(BIOS_ERR, "mtcmos_vote enable %d timeout\n", id); + return ret; + } + + if (md->cb && md->cb->post_on) { + ret = md->cb->post_on(); + if (ret) { + printk(BIOS_ERR, "mtcmos(%d) call post_on fail(%d)\n", id, ret); + return ret; + } + } + } + + return 0; +} + +static void mtcmos_spm_clr_rtff_flag(void) +{ + clrbits32(&mtk_spm_mtcmos->conn_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ssusb_dp_phy_p0_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ssusb_p0_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ssusb_p1_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ssusb_p23_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ssusb_phy_p2_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ufs0_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ufs0_phy_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->pextp_mac0_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->pextp_mac1_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->pextp_mac2_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->pextp_phy0_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->pextp_phy1_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->pextp_phy2_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->audio_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->adsp_infra_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->adsp_ao_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->mm_proc_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->ssrsys_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->spu_ise_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->spu_hwrot_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->hsgmii0_pwr_con, PWR_RTFF_SAVE_FLAG); + clrbits32(&mtk_spm_mtcmos->hsgmii1_pwr_con, PWR_RTFF_SAVE_FLAG); +} + +static int mtcmos_disp_vcore_pre_on(void) +{ + write32(MM_BUCK_ISO_CON_CLR, BIT(0)); + write32(MM_BUCK_ISO_CON_CLR, BIT(1)); + write32(MM_BUCK_ISO_CON_CLR, BIT(2)); + + write32(DISP_AO_PWR_CON, 0x1); + + return 0; +} + +static int mtcmos_disp_vcore_post_on(void) +{ + write32(MMPC_BUS_PROTECT_EN_1_CLR, BIT(6) | BIT(7)); + + write32p(DISP_VDISP_AO_CONFIG_CG, 0xFFFFFFFF); + + setbits32p(DISP_DPC_DISP0_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_DISP1_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_OVL0_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_OVL1_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_MML0_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_MML1_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_EDP_MTCMOS_CFG, BIT(4)); + setbits32p(DISP_DPC_EPTX_MTCMOS_CFG, BIT(4)); + + return 0; +} + +static struct mtcmos_cb disp_vcore_cb = { + .pre_on = mtcmos_disp_vcore_pre_on, + .post_on = mtcmos_disp_vcore_post_on, +}; + +void mtcmos_protect_display_bus(void) +{ + /* empty implementation for user common flow */ +} + +void mtcmos_display_power_on(void) +{ + mtcmos_ctrl(MTCMOS_ID_DIS0_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DIS1_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_OVL0_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_OVL1_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DISP_EDPTX_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DISP_DPTX_SHUTDOWN, MTCMOS_POWER_ON); +} + +void mtcmos_ctrl(enum mtcmos_id id, enum mtcmos_state state) +{ + int ret = 0; + + if (id >= MTCMOS_ID_NUM) { + printk(BIOS_ERR, "id(%d) is invalid\n", id); + return; + } + + if (id <= MTCMOS_ID_SSRSYS) + ret = mtcmos_onoff(id, state); + else + ret = mtcmos_vote_onoff(id, state); + + if (ret) + printk(BIOS_ERR, "%s(%u, %u) fail, ret=%d\n", __func__, id, state, ret); +} + +void mtcmos_init(void) +{ + write32(POWERON_CONFIG_EN, (SPM_PROJECT_CODE << 16) | BIT(0)); + + mtcmos_spm_clr_rtff_flag(); + + mtcmos_ctrl(MTCMOS_ID_SSUSB_P0, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_SSUSB_DP_PHY_P0, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_SSUSB_P1, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_SSUSB_P23, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_SSUSB_PHY_P2, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_UFS0_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_UFS0_PHY, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_PEXTP_MAC0, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_PEXTP_MAC1, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_PEXTP_MAC2, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_PEXTP_PHY0, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_PEXTP_PHY1, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_PEXTP_PHY2, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_ADSP_TOP_SHUTDOWN, MTCMOS_POWER_DOWN); + mtcmos_ctrl(MTCMOS_ID_AUDIO, MTCMOS_POWER_DOWN); + mtcmos_ctrl(MTCMOS_ID_ADSP_INFRA, MTCMOS_POWER_DOWN); + mtcmos_ctrl(MTCMOS_ID_ADSP_AO, MTCMOS_POWER_DOWN); + mtcmos_ctrl(MTCMOS_ID_ADSP_AO, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_ADSP_INFRA, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_AUDIO, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_ADSP_TOP_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_MM_PROC_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_SSRSYS, MTCMOS_POWER_ON); +} + +void mtcmos_post_init(void) +{ + if (mtcmos_cb_register(MTCMOS_ID_DISP_VCORE, &disp_vcore_cb)) + printk(BIOS_ERR, "register disp_vcore failed\n"); + + mtcmos_ctrl(MTCMOS_ID_MM_INFRA_AO, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_MM_INFRA0, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_MM_INFRA1, MTCMOS_POWER_ON); + + mtcmos_ctrl(MTCMOS_ID_DISP_VCORE, MTCMOS_POWER_ON); + write32(&mtk_disp->clk_cfg[0].clr, 0x00000007); + + mtcmos_ctrl(MTCMOS_ID_DIS0_SHUTDOWN, MTCMOS_POWER_ON); + write32(&mtk_mmsys->clk_cfg[0].clr, 0xFFFFFFFF); + write32(&mtk_mmsys->clk_cfg[1].clr, 0x07FFFFFF); + + mtcmos_ctrl(MTCMOS_ID_DIS1_SHUTDOWN, MTCMOS_POWER_ON); + write32(&mtk_mmsys1->clk_cfg[0].clr, 0xFFFFFFFF); + write32(&mtk_mmsys1->clk_cfg[1].clr, 0x1FF3FFFF); + + mtcmos_ctrl(MTCMOS_ID_OVL0_SHUTDOWN, MTCMOS_POWER_ON); + write32(&mtk_ovlsys->clk_cfg[0].clr, 0xFFFFFFFF); + write32(&mtk_ovlsys->clk_cfg[1].clr, 0x7FFFFFFF); + + mtcmos_ctrl(MTCMOS_ID_OVL1_SHUTDOWN, MTCMOS_POWER_ON); + write32(&mtk_ovlsys1->clk_cfg[0].clr, 0xFFFFFFFF); + write32(&mtk_ovlsys1->clk_cfg[1].clr, 0x7FFFFFFF); + + mtcmos_ctrl(MTCMOS_ID_DISP_EDPTX_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DISP_DPTX_SHUTDOWN, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DSI_PHY0, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DSI_PHY1, MTCMOS_POWER_ON); + mtcmos_ctrl(MTCMOS_ID_DSI_PHY2, MTCMOS_POWER_ON); + + /* vmm buck isolation off */ + write32(MM_BUCK_ISO_CON_CLR, BIT(4)); + write32(MM_BUCK_ISO_CON_CLR, BIT(5)); + write32(MM_BUCK_ISO_CON_CLR, BIT(6)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 41 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yidi Lin (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Xiwen Shao, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 20: (1 comment) File src/soc/mediatek/mt8196/tracker.c: https://review.coreboot.org/c/coreboot/+/84929/comment/e5adb138_116a6bb6?us… : PS12, Line 71: ( > Done Not done. Please examine whole patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 20 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 12 Dec 2024 01:15:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jarried Lin <jarried.lin(a)mediatek.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Adding device id for Crashlog and Telemetry
by Jamie Ryu (Code Review) 12 Dec '24

12 Dec '24

Attention is currently required from: Sowmya Aralguppe. Jamie Ryu has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/85372?usp=email ) Change subject: soc/intel/pantherlake: Adding device id for Crashlog and Telemetry ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2959623986108a2c5e3dce16e892913a42d71755 Gerrit-Change-Number: 85372 Gerrit-PatchSet: 8 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 23:38:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr/acpi: Fix regression
by Paul Menzel (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85562?usp=email ) Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85562/comment/397c9073_327fb4cd?us… : PS3, Line 7: Fix regression > It does fix a regression Yes, but it’s too generic in my opinion. -- To view, visit https://review.coreboot.org/c/coreboot/+/85562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658 Gerrit-Change-Number: 85562 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 11 Dec 2024 22:32:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
by Paul Menzel (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Ana Carolina Cabral. Paul Menzel has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85498/comment/0a95b17f_895b70c5?us… : PS4, Line 9: Fix VDD_MEM_VID[0,1] pin assignments that was causing boot issues. It’d be great if you explained the issue with ABL, mentioned in the comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 4 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Wed, 11 Dec 2024 22:15:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
by Felix Held (Code Review) 11 Dec '24

11 Dec '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] ...................................................................... mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] Fix VDD_MEM_VID[0,1] pin assignments that was causing boot issues. Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Signed-off-by: Ana Carolina Cabral <ana.cabral(a)amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85498 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/birman/gpio.c M src/mainboard/amd/birman_plus/gpio.c 2 files changed, 4 insertions(+), 8 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/birman/gpio.c b/src/mainboard/amd/birman/gpio.c index 74d929d..348f76a 100644 --- a/src/mainboard/amd/birman/gpio.c +++ b/src/mainboard/amd/birman/gpio.c @@ -29,8 +29,7 @@ PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), /* SD_CARD_PRSNT_L */ PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ - /* VDD_MEM_VID0 */ - PAD_GPO(GPIO_10, HIGH), + /* GPIO_10: VDD_MEM_VID0 - Controlled by firmware outside of coreboot (ABL) */ /* HP_MIC_DET_L */ PAD_GPI(GPIO_11, PULL_UP), /* ALIGN_FLAG_MU_L */ @@ -76,8 +75,7 @@ /* USB2_HDR_P0/1_SMI */ PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), /* GPIO_41: Not available */ - /* VDD_MEM_VID1 */ - PAD_GPO(GPIO_42, HIGH), + /* GPIO_42: VDD_MEM_VID1 - Controlled by firmware outside of coreboot (ABL) */ /* GPIO_43 - GPIO_66: Not available */ /* SPI_ROM_REQ */ PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), diff --git a/src/mainboard/amd/birman_plus/gpio.c b/src/mainboard/amd/birman_plus/gpio.c index 74d929d..348f76a 100644 --- a/src/mainboard/amd/birman_plus/gpio.c +++ b/src/mainboard/amd/birman_plus/gpio.c @@ -29,8 +29,7 @@ PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), /* SD_CARD_PRSNT_L */ PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ - /* VDD_MEM_VID0 */ - PAD_GPO(GPIO_10, HIGH), + /* GPIO_10: VDD_MEM_VID0 - Controlled by firmware outside of coreboot (ABL) */ /* HP_MIC_DET_L */ PAD_GPI(GPIO_11, PULL_UP), /* ALIGN_FLAG_MU_L */ @@ -76,8 +75,7 @@ /* USB2_HDR_P0/1_SMI */ PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), /* GPIO_41: Not available */ - /* VDD_MEM_VID1 */ - PAD_GPO(GPIO_42, HIGH), + /* GPIO_42: VDD_MEM_VID1 - Controlled by firmware outside of coreboot (ABL) */ /* GPIO_43 - GPIO_66: Not available */ /* SPI_ROM_REQ */ PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 4 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls
by Marshall Dawson (Code Review) 11 Dec '24

11 Dec '24

Attention is currently required from: Ana Carolina Cabral, Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, Matt DeVillier, Nick Kochlowski, Paul Menzel. Marshall Dawson has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/84915?usp=email ) Change subject: driver/amd/opensil: Add PHX OpenSIL POC TP2/TP3 calls ...................................................................... Patch Set 9: (2 comments) File src/drivers/amd/opensil/amd_silicon_init.c: https://review.coreboot.org/c/coreboot/+/84915/comment/6a3f0e88_74e4c43d?us… : PS8, Line 29: BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, call_opensil_xSIM_timepoint, (void *)XSIM_TIMEPOINT_2); : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, call_opensil_xSIM_timepoint, (void *)XSIM_TIMEPOINT_3); : BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, call_opensil_xSIM_timepoint, (void *)XSIM_TIMEPOINT_3); > Do these TP2/TP3 calls need to be conditioned to execute only when PHX is selected? Or will this be […] They'll be common to all File src/drivers/amd/opensil/amd_silicon_init.c: https://review.coreboot.org/c/coreboot/+/84915/comment/131051e6_d807881f?us… : PS9, Line 30: call_opensil_xSIM_timepoint, : (void *)(uintptr_t)XSIM_TIMEPOINT_2); Just a nit on style, I'd put these arguments on the same line vs. having 2 linebreaks in the statement. Same below too. -- To view, visit https://review.coreboot.org/c/coreboot/+/84915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38 Gerrit-Change-Number: 84915 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Ana Carolina Cabral Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 11 Dec 2024 20:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nick Kochlowski <nickkochlowski(a)gmail.com>

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